Chip data file updates for MCC chiplet
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I24b66e385c8a6c413eca1fec12cf797f1ae5e529
diff --git a/xml/p10/node_mc_ustl_fir_p10_10.xml b/xml/p10/node_mc_ustl_fir_p10_10.xml
index af22fbc..a9cd1d5 100644
--- a/xml/p10/node_mc_ustl_fir_p10_10.xml
+++ b/xml/p10/node_mc_ustl_fir_p10_10.xml
@@ -15,12 +15,69 @@
<action attn_type="UCS" config="110"/>
<action attn_type="HA" config="001"/>
</local_fir>
+ <register name="MC_USTL_ERR_RPT_0">
+ <instance addr="0x0C010E0E" reg_inst="0"/>
+ <instance addr="0x0C010E4E" reg_inst="1"/>
+ <instance addr="0x0D010E0E" reg_inst="2"/>
+ <instance addr="0x0D010E4E" reg_inst="3"/>
+ <instance addr="0x0E010E0E" reg_inst="4"/>
+ <instance addr="0x0E010E4E" reg_inst="5"/>
+ <instance addr="0x0F010E0E" reg_inst="6"/>
+ <instance addr="0x0F010E4E" reg_inst="7"/>
+ </register>
+ <register name="MC_USTL_LOL_DROP">
+ <instance addr="0x0C010E11" reg_inst="0"/>
+ <instance addr="0x0C010E51" reg_inst="1"/>
+ <instance addr="0x0D010E11" reg_inst="2"/>
+ <instance addr="0x0D010E51" reg_inst="3"/>
+ <instance addr="0x0E010E11" reg_inst="4"/>
+ <instance addr="0x0E010E51" reg_inst="5"/>
+ <instance addr="0x0F010E11" reg_inst="6"/>
+ <instance addr="0x0F010E51" reg_inst="7"/>
+ </register>
+ <register name="MC_USTL_LOL_MASK">
+ <instance addr="0x0C010E12" reg_inst="0"/>
+ <instance addr="0x0C010E52" reg_inst="1"/>
+ <instance addr="0x0D010E12" reg_inst="2"/>
+ <instance addr="0x0D010E52" reg_inst="3"/>
+ <instance addr="0x0E010E12" reg_inst="4"/>
+ <instance addr="0x0E010E52" reg_inst="5"/>
+ <instance addr="0x0F010E12" reg_inst="6"/>
+ <instance addr="0x0F010E52" reg_inst="7"/>
+ </register>
+ <register name="MC_USTL_FAIL_MASK">
+ <instance addr="0x0C010E13" reg_inst="0"/>
+ <instance addr="0x0C010E53" reg_inst="1"/>
+ <instance addr="0x0D010E13" reg_inst="2"/>
+ <instance addr="0x0D010E53" reg_inst="3"/>
+ <instance addr="0x0E010E13" reg_inst="4"/>
+ <instance addr="0x0E010E53" reg_inst="5"/>
+ <instance addr="0x0F010E13" reg_inst="6"/>
+ <instance addr="0x0F010E53" reg_inst="7"/>
+ </register>
+ <register name="MC_USTL_ERR_RPT_1">
+ <instance addr="0x0C010E16" reg_inst="0"/>
+ <instance addr="0x0C010E56" reg_inst="1"/>
+ <instance addr="0x0D010E16" reg_inst="2"/>
+ <instance addr="0x0D010E56" reg_inst="3"/>
+ <instance addr="0x0E010E16" reg_inst="4"/>
+ <instance addr="0x0E010E56" reg_inst="5"/>
+ <instance addr="0x0F010E16" reg_inst="6"/>
+ <instance addr="0x0F010E56" reg_inst="7"/>
+ </register>
+ <capture_group node_inst="0:7">
+ <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_0" />
+ <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_DROP" />
+ <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_MASK" />
+ <capture_register reg_inst="0:7" reg_name="MC_USTL_FAIL_MASK" />
+ <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_1" />
+ </capture_group>
<bit pos="0">Unexpected Flit Data showed up for Chana</bit>
<bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
<bit pos="2">A unsupported template for a command flit for chana</bit>
<bit pos="3">A unsupported template for a command flit for chanb</bit>
- <bit pos="4">Reserved.</bit>
- <bit pos="5">Reserved.</bit>
+ <bit pos="4">Reserved</bit>
+ <bit pos="5">Reserved</bit>
<bit pos="6">WDF CE detected on buffer output</bit>
<bit pos="7">WDF UE detected on buffer output</bit>
<bit pos="8">WDF SUE detected on buffer output</bit>
@@ -31,7 +88,7 @@
<bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
<bit pos="14">Parity Error detected in WDF for CL pop</bit>
<bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
- <bit pos="16">WDF UE detected a parity error on the CMT interface from USTL, cmd parity err, or buffer manager parity error</bit>
+ <bit pos="16">WDF CMD parity errror</bit>
<bit pos="17">Unused</bit>
<bit pos="18">Unused</bit>
<bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
@@ -40,8 +97,8 @@
<bit pos="22">WRT SUE detected on buffer output</bit>
<bit pos="23">WRT detected a scom sequencer error</bit>
<bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
- <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer.</bit>
- <bit pos="26">No buffer error; Buffer manager parity error.</bit>
+ <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer</bit>
+ <bit pos="26">No buffer error; Buffer manager parity error</bit>
<bit pos="27">A fail response set as checkstop occurred for chana</bit>
<bit pos="28">A fail response set as checkstop occurred for chanb</bit>
<bit pos="29">A fail response set as recoverable occurred for chana</bit>
@@ -64,8 +121,8 @@
<bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
<bit pos="47">valid bad data or SUE received channel a</bit>
<bit pos="48">Valid bad data or SUE received chanb</bit>
- <bit pos="49">Data is valid in data buffers without a matching response, or more than 2 data flits with template 9</bit>
- <bit pos="50">Data is valid in data buffers without a matching response,or more than 2 data flits with template 9</bit>
+ <bit pos="49">ChanA excessive data error</bit>
+ <bit pos="50">ChanB excessive data error</bit>
<bit pos="51">Commit state where commit data is not marked as valid</bit>
<bit pos="52">Commit state where commit data is not marked as valid</bit>
<bit pos="53">A fifo in the ustl chana overflowed</bit>
@@ -74,7 +131,7 @@
<bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
<bit pos="57">Fatal register parity error</bit>
<bit pos="58">recov register parity error</bit>
- <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
- <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
- <bit pos="61">USTL spare FIR bits</bit>
+ <bit pos="59">ChanA response invalid(dlength and/or dpart received)</bit>
+ <bit pos="60">ChanB response invalid(dlength and/or dpart received)</bit>
+ <bit pos="61">spare</bit>
</attn_node>