diff --git a/xml/p10/node_mc_dstl_fir.xml b/xml/p10/node_mc_dstl_fir.xml
index 15251de..2b04af8 100644
--- a/xml/p10/node_mc_dstl_fir.xml
+++ b/xml/p10/node_mc_dstl_fir.xml
@@ -15,45 +15,69 @@
         <action attn_type="UCS" config="110"/>
         <action attn_type="HA" config="001"/>
     </local_fir>
-    <bit pos="0">AFU initiated Checkstop on Subchannel A</bit>
-    <bit pos="1">AFU initiated Recoverable Attention on Subchannel A</bit>
-    <bit pos="2">AFU initiated Special Attention on Subchannel A</bit>
-    <bit pos="3">AFU initiated Application Interrupt Attention on Subchannel A</bit>
-    <bit pos="4">AFU initiated Checkstop on Subchannel B</bit>
-    <bit pos="5">AFU initiated Recoverable Attention on Subchannel B</bit>
-    <bit pos="6">AFU initiated Special Attention on Subchannel B</bit>
-    <bit pos="7">AFU initiated Application Interrupt Attention on Subchannel B</bit>
-    <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL.</bit>
-    <bit pos="9">A credit reset was attempted while rd and wdf buffers in use.</bit>
-    <bit pos="10">DSTL Configuration Register has taken a recoverable parity error.</bit>
-    <bit pos="11">DSTL Configuration Register has taken a fatal parity error.</bit>
-    <bit pos="12">DSTL Subchannel A, a counter took an underflow or overflow error.</bit>
-    <bit pos="13">DSTL Subchannel B, a counter took an underflow or overflow error.</bit>
-    <bit pos="14">DSTL Subchannel A timed out having valid commands and not sending any flits.</bit>
-    <bit pos="15">DSTL Subchannel B timed out having valid commands and not sending any flits.</bit>
-    <bit pos="16">DSTL has detected that attached buffer on subchannel A has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
-    <bit pos="17">DSTL has detected that attached buffer on subchannel B has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
-    <bit pos="18">DSTL Subchannel A observed link going down.</bit>
-    <bit pos="19">DSTL Subchannel B observed link going down.</bit>
-    <bit pos="20">DSTL Subchannel A has entered the fail state.</bit>
-    <bit pos="21">DSTL Subchannel B has entered the fail state.</bit>
-    <bit pos="22">Channel timeout has occured on Subchannel A index.</bit>
-    <bit pos="23">Channel timeout has occured on Subchannel B index.</bit>
-    <bit pos="24">Error info from decrypt</bit>
-    <bit pos="25">Error info from decrypt</bit>
-    <bit pos="26">Error info from decrypt</bit>
-    <bit pos="27">Error info from decrypt</bit>
-    <bit pos="28">Error info from decrypt</bit>
-    <bit pos="29">Error info from encrypt</bit>
-    <bit pos="30">Error info from encrypt</bit>
-    <bit pos="31">Error info from encrypt</bit>
-    <bit pos="32">Error info from encrypt</bit>
-    <bit pos="33">On Subchhanel A, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
-    <bit pos="34">On Subchhanel B, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
-    <bit pos="35">A parity error local to Subchhanel A occurred.</bit>
-    <bit pos="36">A parity error local to Subchhanel B occurred.</bit>
-    <bit pos="37">Spare FIR bit 37.</bit>
-    <bit pos="38">Spare FIR bit 38.</bit>
-    <bit pos="39">Indicates that this subchannel has significant traffic flow.</bit>
-    <bit pos="40">Indicates that this subchannel has significant traffic flow.</bit>
+    <register name="MC_DSTL_ERR_RPT">
+        <instance addr="0x0C010D0C" reg_inst="0"/>
+        <instance addr="0x0C010D4C" reg_inst="1"/>
+        <instance addr="0x0D010D0C" reg_inst="2"/>
+        <instance addr="0x0D010D4C" reg_inst="3"/>
+        <instance addr="0x0E010D0C" reg_inst="4"/>
+        <instance addr="0x0E010D4C" reg_inst="5"/>
+        <instance addr="0x0F010D0C" reg_inst="6"/>
+        <instance addr="0x0F010D4C" reg_inst="7"/>
+    </register>
+    <register name="MC_DSTL_CFG2">
+        <instance addr="0x0C010D0E" reg_inst="0"/>
+        <instance addr="0x0C010D4E" reg_inst="1"/>
+        <instance addr="0x0D010D0E" reg_inst="2"/>
+        <instance addr="0x0D010D4E" reg_inst="3"/>
+        <instance addr="0x0E010D0E" reg_inst="4"/>
+        <instance addr="0x0E010D4E" reg_inst="5"/>
+        <instance addr="0x0F010D0E" reg_inst="6"/>
+        <instance addr="0x0F010D4E" reg_inst="7"/>
+    </register>
+    <capture_group node_inst="0:7">
+        <capture_register reg_inst="0:7" reg_name="MC_DSTL_ERR_RPT" />
+        <capture_register reg_inst="0:7" reg_name="MC_DSTL_CFG2" />
+    </capture_group>
+    <bit pos="0">Subchannel A AFU initiated Checkstop</bit>
+    <bit pos="1">Subchannel A AFU initiated Recoverable Attention</bit>
+    <bit pos="2">Subchannel A AFU initiated Special Attention</bit>
+    <bit pos="3">Subchannel A AFU initiated Application Interrupt Attention</bit>
+    <bit pos="4">Subchannel B AFU initiated Checkstop</bit>
+    <bit pos="5">Subchannel B AFU initiated Recoverable Attention</bit>
+    <bit pos="6">Subchannel B AFU initiated Special Attention</bit>
+    <bit pos="7">Subchannel B AFU initiated Application Interrupt Attention</bit>
+    <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL</bit>
+    <bit pos="9">A credit reset was attempted while rd and wdf buffers in use</bit>
+    <bit pos="10">Config reg recoverable parity error</bit>
+    <bit pos="11">Config reg fatal parity error</bit>
+    <bit pos="12">Subchannel A counter error</bit>
+    <bit pos="13">Subchannel B counter error</bit>
+    <bit pos="14">Subchannel A valid cmd timeout error</bit>
+    <bit pos="15">Subchannel B valid cmd timeout error</bit>
+    <bit pos="16">Subchannel A buffer overuse error</bit>
+    <bit pos="17">Subchannel B buffer overuse error</bit>
+    <bit pos="18">Subchannel A DL link down</bit>
+    <bit pos="19">Subchannel B DL link down</bit>
+    <bit pos="20">Subchannel A has entered the fail state</bit>
+    <bit pos="21">Subchannel B has entered the fail state</bit>
+    <bit pos="22">Subchannel A Channel timeout</bit>
+    <bit pos="23">Subchannel B Channel timeout</bit>
+    <bit pos="24">decrypt err: scom reg has parity error</bit>
+    <bit pos="25">decrypt err: attempt to write or access key when locked</bit>
+    <bit pos="26">decrypt err: address pipe parity error</bit>
+    <bit pos="27">decrypt err: CL to decrypt parity error on valid tag</bit>
+    <bit pos="28">decrypt err: parity error on USTL decrypt DMX interface</bit>
+    <bit pos="29">encrypt err: scom reg has parity error</bit>
+    <bit pos="30">encrypt err: attempt to write or access key when locked</bit>
+    <bit pos="31">encrypt err: parity error on address encryption rounds</bit>
+    <bit pos="32">encrypt err: parity error on data encryption rounds</bit>
+    <bit pos="33">Subchannel A AFU Application Interrupt Attention while another in process</bit>
+    <bit pos="34">Subchannel B AFU Application Interrupt Attention while another in process</bit>
+    <bit pos="35">A parity error local to Subchhanel A occurred</bit>
+    <bit pos="36">A parity error local to Subchhanel B occurred</bit>
+    <bit pos="37">reserved</bit>
+    <bit pos="38">reserved</bit>
+    <bit pos="39">Subchannel A has significant traffic flow</bit>
+    <bit pos="40">Subchannel B has significant traffic flow</bit>
 </attn_node>
diff --git a/xml/p10/node_mc_dstl_fir_p10_10.xml b/xml/p10/node_mc_dstl_fir_p10_10.xml
index 5de66eb..f3b373f 100644
--- a/xml/p10/node_mc_dstl_fir_p10_10.xml
+++ b/xml/p10/node_mc_dstl_fir_p10_10.xml
@@ -15,43 +15,67 @@
         <action attn_type="UCS" config="110"/>
         <action attn_type="HA" config="001"/>
     </local_fir>
-    <bit pos="0">AFU initiated Checkstop on Subchannel A</bit>
-    <bit pos="1">AFU initiated Recoverable Attention on Subchannel A</bit>
-    <bit pos="2">AFU initiated Special Attention on Subchannel A</bit>
-    <bit pos="3">AFU initiated Application Interrupt Attention on Subchannel A</bit>
-    <bit pos="4">AFU initiated Checkstop on Subchannel B</bit>
-    <bit pos="5">AFU initiated Recoverable Attention on Subchannel B</bit>
-    <bit pos="6">AFU initiated Special Attention on Subchannel B</bit>
-    <bit pos="7">AFU initiated Application Interrupt Attention on Subchannel B</bit>
-    <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL.</bit>
-    <bit pos="9">A credit reset was attempted while rd and wdf buffers in use.</bit>
-    <bit pos="10">DSTL Configuration Register has taken a recoverable parity error.</bit>
-    <bit pos="11">DSTL Configuration Register has taken a fatal parity error.</bit>
-    <bit pos="12">DSTL Subchannel A, a counter took an underflow or overflow error.</bit>
-    <bit pos="13">DSTL Subchannel B, a counter took an underflow or overflow error.</bit>
-    <bit pos="14">DSTL Subchannel A timed out having valid commands and not sending any flits.</bit>
-    <bit pos="15">DSTL Subchannel B timed out having valid commands and not sending any flits.</bit>
-    <bit pos="16">DSTL has detected that attached buffer on subchannel A has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
-    <bit pos="17">DSTL has detected that attached buffer on subchannel B has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
-    <bit pos="18">DSTL Subchannel A observed link going down.</bit>
-    <bit pos="19">DSTL Subchannel B observed link going down.</bit>
-    <bit pos="20">DSTL Subchannel A has entered the fail state.</bit>
-    <bit pos="21">DSTL Subchannel B has entered the fail state.</bit>
-    <bit pos="22">Channel timeout has occured on Subchannel A index.</bit>
-    <bit pos="23">Channel timeout has occured on Subchannel B index.</bit>
-    <bit pos="24">Error info from decrypt</bit>
-    <bit pos="25">Error info from decrypt</bit>
-    <bit pos="26">Error info from decrypt</bit>
-    <bit pos="27">Error info from decrypt</bit>
-    <bit pos="28">Error info from decrypt</bit>
-    <bit pos="29">Error info from encrypt</bit>
-    <bit pos="30">Error info from encrypt</bit>
-    <bit pos="31">Error info from encrypt</bit>
-    <bit pos="32">Error info from encrypt</bit>
-    <bit pos="33">On Subchhanel A, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
-    <bit pos="34">On Subchhanel B, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
-    <bit pos="35">A parity error local to Subchhanel A occurred.</bit>
-    <bit pos="36">A parity error local to Subchhanel B occurred.</bit>
-    <bit pos="37">Spare FIR bit 37.</bit>
-    <bit pos="38">Spare FIR bit 38.</bit>
+    <register name="MC_DSTL_ERR_RPT">
+        <instance addr="0x0C010D0C" reg_inst="0"/>
+        <instance addr="0x0C010D4C" reg_inst="1"/>
+        <instance addr="0x0D010D0C" reg_inst="2"/>
+        <instance addr="0x0D010D4C" reg_inst="3"/>
+        <instance addr="0x0E010D0C" reg_inst="4"/>
+        <instance addr="0x0E010D4C" reg_inst="5"/>
+        <instance addr="0x0F010D0C" reg_inst="6"/>
+        <instance addr="0x0F010D4C" reg_inst="7"/>
+    </register>
+    <register name="MC_DSTL_CFG2">
+        <instance addr="0x0C010D0E" reg_inst="0"/>
+        <instance addr="0x0C010D4E" reg_inst="1"/>
+        <instance addr="0x0D010D0E" reg_inst="2"/>
+        <instance addr="0x0D010D4E" reg_inst="3"/>
+        <instance addr="0x0E010D0E" reg_inst="4"/>
+        <instance addr="0x0E010D4E" reg_inst="5"/>
+        <instance addr="0x0F010D0E" reg_inst="6"/>
+        <instance addr="0x0F010D4E" reg_inst="7"/>
+    </register>
+    <capture_group node_inst="0:7">
+        <capture_register reg_inst="0:7" reg_name="MC_DSTL_ERR_RPT" />
+        <capture_register reg_inst="0:7" reg_name="MC_DSTL_CFG2" />
+    </capture_group>
+    <bit pos="0">Subchannel A AFU initiated Checkstop</bit>
+    <bit pos="1">Subchannel A AFU initiated Recoverable Attention</bit>
+    <bit pos="2">Subchannel A AFU initiated Special Attention</bit>
+    <bit pos="3">Subchannel A AFU initiated Application Interrupt Attention</bit>
+    <bit pos="4">Subchannel B AFU initiated Checkstop</bit>
+    <bit pos="5">Subchannel B AFU initiated Recoverable Attention</bit>
+    <bit pos="6">Subchannel B AFU initiated Special Attention</bit>
+    <bit pos="7">Subchannel B AFU initiated Application Interrupt Attention</bit>
+    <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL</bit>
+    <bit pos="9">A credit reset was attempted while rd and wdf buffers in use</bit>
+    <bit pos="10">Config reg recoverable parity error</bit>
+    <bit pos="11">Config reg fatal parity error</bit>
+    <bit pos="12">Subchannel A counter error</bit>
+    <bit pos="13">Subchannel B counter error</bit>
+    <bit pos="14">Subchannel A valid cmd timeout error</bit>
+    <bit pos="15">Subchannel B valid cmd timeout error</bit>
+    <bit pos="16">Subchannel A buffer overuse error</bit>
+    <bit pos="17">Subchannel B buffer overuse error</bit>
+    <bit pos="18">Subchannel A DL link down</bit>
+    <bit pos="19">Subchannel B DL link down</bit>
+    <bit pos="20">Subchannel A has entered the fail state</bit>
+    <bit pos="21">Subchannel B has entered the fail state</bit>
+    <bit pos="22">Subchannel A Channel timeout</bit>
+    <bit pos="23">Subchannel B Channel timeout</bit>
+    <bit pos="24">decrypt err: scom reg has parity error</bit>
+    <bit pos="25">decrypt err: attempt to write or access key when locked</bit>
+    <bit pos="26">decrypt err: address pipe parity error</bit>
+    <bit pos="27">decrypt err: CL to decrypt parity error on valid tag</bit>
+    <bit pos="28">decrypt err: parity error on USTL decrypt DMX interface</bit>
+    <bit pos="29">encrypt err: scom reg has parity error</bit>
+    <bit pos="30">encrypt err: attempt to write or access key when locked</bit>
+    <bit pos="31">encrypt err: parity error on address encryption rounds</bit>
+    <bit pos="32">encrypt err: parity error on data encryption rounds</bit>
+    <bit pos="33">Subchannel A AFU Application Interrupt Attention while another in process</bit>
+    <bit pos="34">Subchannel B AFU Application Interrupt Attention while another in process</bit>
+    <bit pos="35">A parity error local to Subchhanel A occurred</bit>
+    <bit pos="36">A parity error local to Subchhanel B occurred</bit>
+    <bit pos="37">reserved</bit>
+    <bit pos="38">reserved</bit>
 </attn_node>
diff --git a/xml/p10/node_mc_ustl_fir.xml b/xml/p10/node_mc_ustl_fir.xml
index 1dd54bf..d0e7425 100644
--- a/xml/p10/node_mc_ustl_fir.xml
+++ b/xml/p10/node_mc_ustl_fir.xml
@@ -15,12 +15,69 @@
         <action attn_type="UCS" config="110"/>
         <action attn_type="HA" config="001"/>
     </local_fir>
+    <register name="MC_USTL_ERR_RPT_0">
+        <instance addr="0x0C010E0E" reg_inst="0"/>
+        <instance addr="0x0C010E4E" reg_inst="1"/>
+        <instance addr="0x0D010E0E" reg_inst="2"/>
+        <instance addr="0x0D010E4E" reg_inst="3"/>
+        <instance addr="0x0E010E0E" reg_inst="4"/>
+        <instance addr="0x0E010E4E" reg_inst="5"/>
+        <instance addr="0x0F010E0E" reg_inst="6"/>
+        <instance addr="0x0F010E4E" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_LOL_DROP">
+        <instance addr="0x0C010E11" reg_inst="0"/>
+        <instance addr="0x0C010E51" reg_inst="1"/>
+        <instance addr="0x0D010E11" reg_inst="2"/>
+        <instance addr="0x0D010E51" reg_inst="3"/>
+        <instance addr="0x0E010E11" reg_inst="4"/>
+        <instance addr="0x0E010E51" reg_inst="5"/>
+        <instance addr="0x0F010E11" reg_inst="6"/>
+        <instance addr="0x0F010E51" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_LOL_MASK">
+        <instance addr="0x0C010E12" reg_inst="0"/>
+        <instance addr="0x0C010E52" reg_inst="1"/>
+        <instance addr="0x0D010E12" reg_inst="2"/>
+        <instance addr="0x0D010E52" reg_inst="3"/>
+        <instance addr="0x0E010E12" reg_inst="4"/>
+        <instance addr="0x0E010E52" reg_inst="5"/>
+        <instance addr="0x0F010E12" reg_inst="6"/>
+        <instance addr="0x0F010E52" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_FAIL_MASK">
+        <instance addr="0x0C010E13" reg_inst="0"/>
+        <instance addr="0x0C010E53" reg_inst="1"/>
+        <instance addr="0x0D010E13" reg_inst="2"/>
+        <instance addr="0x0D010E53" reg_inst="3"/>
+        <instance addr="0x0E010E13" reg_inst="4"/>
+        <instance addr="0x0E010E53" reg_inst="5"/>
+        <instance addr="0x0F010E13" reg_inst="6"/>
+        <instance addr="0x0F010E53" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_ERR_RPT_1">
+        <instance addr="0x0C010E16" reg_inst="0"/>
+        <instance addr="0x0C010E56" reg_inst="1"/>
+        <instance addr="0x0D010E16" reg_inst="2"/>
+        <instance addr="0x0D010E56" reg_inst="3"/>
+        <instance addr="0x0E010E16" reg_inst="4"/>
+        <instance addr="0x0E010E56" reg_inst="5"/>
+        <instance addr="0x0F010E16" reg_inst="6"/>
+        <instance addr="0x0F010E56" reg_inst="7"/>
+    </register>
+    <capture_group node_inst="0:7">
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_0" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_DROP" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_MASK" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_FAIL_MASK" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_1" />
+    </capture_group>
     <bit pos="0">Unexpected Flit Data showed up for Chana</bit>
     <bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
     <bit pos="2">A unsupported template for a command flit for chana</bit>
     <bit pos="3">A unsupported template for a command flit for chanb</bit>
-    <bit pos="4">Reserved.</bit>
-    <bit pos="5">Reserved.</bit>
+    <bit pos="4">Reserved</bit>
+    <bit pos="5">Reserved</bit>
     <bit pos="6">WDF CE detected on buffer output</bit>
     <bit pos="7">WDF UE detected on buffer output</bit>
     <bit pos="8">WDF SUE detected on buffer output</bit>
@@ -31,7 +88,7 @@
     <bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
     <bit pos="14">Parity Error detected in WDF for CL pop</bit>
     <bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
-    <bit pos="16">WDF UE detected a parity error on the CMT interface from USTL, cmd parity err, or buffer manager parity error</bit>
+    <bit pos="16">WDF CMD parity errror</bit>
     <bit pos="17">Unused</bit>
     <bit pos="18">Unused</bit>
     <bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
@@ -40,8 +97,8 @@
     <bit pos="22">WRT SUE detected on buffer output</bit>
     <bit pos="23">WRT detected a scom sequencer error</bit>
     <bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
-    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer.</bit>
-    <bit pos="26">No buffer error; Buffer manager parity error.</bit>
+    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer</bit>
+    <bit pos="26">No buffer error; Buffer manager parity error</bit>
     <bit pos="27">A fail response set as checkstop occurred for chana</bit>
     <bit pos="28">A fail response set as checkstop occurred for chanb</bit>
     <bit pos="29">A fail response set as recoverable occurred for chana</bit>
@@ -54,8 +111,8 @@
     <bit pos="36">flit data pariry error from dl for chanb</bit>
     <bit pos="37">internal fifo parity error for chana</bit>
     <bit pos="38">internal fifo parity error for chanb</bit>
-    <bit pos="39">Bad response detected from chana. See cerrrpts and USTLBADRESP reg for more info.</bit>
-    <bit pos="40">Bad response detected from chanb. See cerrrpts and USTLBADRESP reg for more info</bit>
+    <bit pos="39">Unexpected read or write response received, chana</bit>
+    <bit pos="40">Unexpected read or write response received, chanb</bit>
     <bit pos="41">Bad data set for data that is not valid chana</bit>
     <bit pos="42">Bad data set for data that is not valid chanb</bit>
     <bit pos="43">Memory read data returned in template 0, chana</bit>
@@ -64,8 +121,8 @@
     <bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
     <bit pos="47">valid bad data or SUE received channel a</bit>
     <bit pos="48">Valid bad data or SUE received chanb</bit>
-    <bit pos="49">Data is valid in data buffers without a matching response, or more than 2 data flits with template 9</bit>
-    <bit pos="50">Data is valid in data buffers without a matching response,or more than 2 data flits with template 9</bit>
+    <bit pos="49">ChanA excessive data error</bit>
+    <bit pos="50">ChanB excessive data error</bit>
     <bit pos="51">Commit state where commit data is not marked as valid</bit>
     <bit pos="52">Commit state where commit data is not marked as valid</bit>
     <bit pos="53">A fifo in the ustl chana overflowed</bit>
@@ -74,7 +131,7 @@
     <bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
     <bit pos="57">Fatal register parity error</bit>
     <bit pos="58">recov register parity error</bit>
-    <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
-    <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
+    <bit pos="59">ChanA response invalid(dlength and/or dpart received)</bit>
+    <bit pos="60">ChanB response invalid(dlength and/or dpart received)</bit>
     <bit pos="61">Parity error on command bus between DSTL-USTL used for chan fail command tracking</bit>
 </attn_node>
diff --git a/xml/p10/node_mc_ustl_fir_p10_10.xml b/xml/p10/node_mc_ustl_fir_p10_10.xml
index af22fbc..a9cd1d5 100644
--- a/xml/p10/node_mc_ustl_fir_p10_10.xml
+++ b/xml/p10/node_mc_ustl_fir_p10_10.xml
@@ -15,12 +15,69 @@
         <action attn_type="UCS" config="110"/>
         <action attn_type="HA" config="001"/>
     </local_fir>
+    <register name="MC_USTL_ERR_RPT_0">
+        <instance addr="0x0C010E0E" reg_inst="0"/>
+        <instance addr="0x0C010E4E" reg_inst="1"/>
+        <instance addr="0x0D010E0E" reg_inst="2"/>
+        <instance addr="0x0D010E4E" reg_inst="3"/>
+        <instance addr="0x0E010E0E" reg_inst="4"/>
+        <instance addr="0x0E010E4E" reg_inst="5"/>
+        <instance addr="0x0F010E0E" reg_inst="6"/>
+        <instance addr="0x0F010E4E" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_LOL_DROP">
+        <instance addr="0x0C010E11" reg_inst="0"/>
+        <instance addr="0x0C010E51" reg_inst="1"/>
+        <instance addr="0x0D010E11" reg_inst="2"/>
+        <instance addr="0x0D010E51" reg_inst="3"/>
+        <instance addr="0x0E010E11" reg_inst="4"/>
+        <instance addr="0x0E010E51" reg_inst="5"/>
+        <instance addr="0x0F010E11" reg_inst="6"/>
+        <instance addr="0x0F010E51" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_LOL_MASK">
+        <instance addr="0x0C010E12" reg_inst="0"/>
+        <instance addr="0x0C010E52" reg_inst="1"/>
+        <instance addr="0x0D010E12" reg_inst="2"/>
+        <instance addr="0x0D010E52" reg_inst="3"/>
+        <instance addr="0x0E010E12" reg_inst="4"/>
+        <instance addr="0x0E010E52" reg_inst="5"/>
+        <instance addr="0x0F010E12" reg_inst="6"/>
+        <instance addr="0x0F010E52" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_FAIL_MASK">
+        <instance addr="0x0C010E13" reg_inst="0"/>
+        <instance addr="0x0C010E53" reg_inst="1"/>
+        <instance addr="0x0D010E13" reg_inst="2"/>
+        <instance addr="0x0D010E53" reg_inst="3"/>
+        <instance addr="0x0E010E13" reg_inst="4"/>
+        <instance addr="0x0E010E53" reg_inst="5"/>
+        <instance addr="0x0F010E13" reg_inst="6"/>
+        <instance addr="0x0F010E53" reg_inst="7"/>
+    </register>
+    <register name="MC_USTL_ERR_RPT_1">
+        <instance addr="0x0C010E16" reg_inst="0"/>
+        <instance addr="0x0C010E56" reg_inst="1"/>
+        <instance addr="0x0D010E16" reg_inst="2"/>
+        <instance addr="0x0D010E56" reg_inst="3"/>
+        <instance addr="0x0E010E16" reg_inst="4"/>
+        <instance addr="0x0E010E56" reg_inst="5"/>
+        <instance addr="0x0F010E16" reg_inst="6"/>
+        <instance addr="0x0F010E56" reg_inst="7"/>
+    </register>
+    <capture_group node_inst="0:7">
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_0" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_DROP" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_LOL_MASK" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_FAIL_MASK" />
+        <capture_register reg_inst="0:7" reg_name="MC_USTL_ERR_RPT_1" />
+    </capture_group>
     <bit pos="0">Unexpected Flit Data showed up for Chana</bit>
     <bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
     <bit pos="2">A unsupported template for a command flit for chana</bit>
     <bit pos="3">A unsupported template for a command flit for chanb</bit>
-    <bit pos="4">Reserved.</bit>
-    <bit pos="5">Reserved.</bit>
+    <bit pos="4">Reserved</bit>
+    <bit pos="5">Reserved</bit>
     <bit pos="6">WDF CE detected on buffer output</bit>
     <bit pos="7">WDF UE detected on buffer output</bit>
     <bit pos="8">WDF SUE detected on buffer output</bit>
@@ -31,7 +88,7 @@
     <bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
     <bit pos="14">Parity Error detected in WDF for CL pop</bit>
     <bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
-    <bit pos="16">WDF UE detected a parity error on the CMT interface from USTL, cmd parity err, or buffer manager parity error</bit>
+    <bit pos="16">WDF CMD parity errror</bit>
     <bit pos="17">Unused</bit>
     <bit pos="18">Unused</bit>
     <bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
@@ -40,8 +97,8 @@
     <bit pos="22">WRT SUE detected on buffer output</bit>
     <bit pos="23">WRT detected a scom sequencer error</bit>
     <bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
-    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer.</bit>
-    <bit pos="26">No buffer error; Buffer manager parity error.</bit>
+    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer</bit>
+    <bit pos="26">No buffer error; Buffer manager parity error</bit>
     <bit pos="27">A fail response set as checkstop occurred for chana</bit>
     <bit pos="28">A fail response set as checkstop occurred for chanb</bit>
     <bit pos="29">A fail response set as recoverable occurred for chana</bit>
@@ -64,8 +121,8 @@
     <bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
     <bit pos="47">valid bad data or SUE received channel a</bit>
     <bit pos="48">Valid bad data or SUE received chanb</bit>
-    <bit pos="49">Data is valid in data buffers without a matching response, or more than 2 data flits with template 9</bit>
-    <bit pos="50">Data is valid in data buffers without a matching response,or more than 2 data flits with template 9</bit>
+    <bit pos="49">ChanA excessive data error</bit>
+    <bit pos="50">ChanB excessive data error</bit>
     <bit pos="51">Commit state where commit data is not marked as valid</bit>
     <bit pos="52">Commit state where commit data is not marked as valid</bit>
     <bit pos="53">A fifo in the ustl chana overflowed</bit>
@@ -74,7 +131,7 @@
     <bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
     <bit pos="57">Fatal register parity error</bit>
     <bit pos="58">recov register parity error</bit>
-    <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
-    <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
-    <bit pos="61">USTL spare FIR bits</bit>
+    <bit pos="59">ChanA response invalid(dlength and/or dpart received)</bit>
+    <bit pos="60">ChanB response invalid(dlength and/or dpart received)</bit>
+    <bit pos="61">spare</bit>
 </attn_node>