Chip data updates for MC chiplet
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ia87913891ffdc5284abce3672195d2bfef0b0b55
diff --git a/xml/p10/node_mc_fir.xml b/xml/p10/node_mc_fir.xml
index 1f2e6e2..9dc209d 100644
--- a/xml/p10/node_mc_fir.xml
+++ b/xml/p10/node_mc_fir.xml
@@ -11,28 +11,51 @@
<action attn_type="UCS" config="110"/>
<action attn_type="HA" config="001"/>
</local_fir>
- <bit pos="0">If '1', a MC recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
- <bit pos="1">If 1, a MC non-recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
- <bit pos="2">If '1', an PowerBus protocol error was detected. (for example, a HPC_WR is snooped when a HPC_WR to the same address is active).</bit>
- <bit pos="3">If '1', a command was issued to inband address space using a</bit>
- <bit pos="4">If '1', an address match on more that one Memory BAR was detected.</bit>
- <bit pos="5">Commandlist early hang trigger activated</bit>
- <bit pos="6">Reserved[6].</bit>
- <bit pos="7">Reserved[7].</bit>
- <bit pos="8">If '1', a command list state machine has timed out.</bit>
- <bit pos="9">Reserved[9].</bit>
- <bit pos="10">Reserved[10].</bit>
- <bit pos="11">If '1', a MCS WAT0 event has occurred.</bit>
- <bit pos="12">If '1', a MCS WAT1 event has occurred.</bit>
- <bit pos="13">If '1', a MCS WAT2 event has occurred.</bit>
- <bit pos="14">If '1', a MCS WAT3 event has occurred.</bit>
+ <register name="MC_ERR_RPT0">
+ <instance addr="0x0C010C1E" reg_inst="0"/>
+ <instance addr="0x0D010C1E" reg_inst="1"/>
+ <instance addr="0x0E010C1E" reg_inst="2"/>
+ <instance addr="0x0F010C1E" reg_inst="3"/>
+ </register>
+ <register name="MC_ERR_RPT1">
+ <instance addr="0x0C010C1F" reg_inst="0"/>
+ <instance addr="0x0D010C1F" reg_inst="1"/>
+ <instance addr="0x0E010C1F" reg_inst="2"/>
+ <instance addr="0x0F010C1F" reg_inst="3"/>
+ </register>
+ <register name="MC_ERR_RPT2">
+ <instance addr="0x0C010C1A" reg_inst="0"/>
+ <instance addr="0x0D010C1A" reg_inst="1"/>
+ <instance addr="0x0E010C1A" reg_inst="2"/>
+ <instance addr="0x0F010C1A" reg_inst="3"/>
+ </register>
+ <capture_group node_inst="0:3">
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT0" />
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT1" />
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT2" />
+ </capture_group>
+ <bit pos="0">MC internal recoverable error</bit>
+ <bit pos="1">MC internal non-recoverable error</bit>
+ <bit pos="2">MC powerbus protocol error</bit>
+ <bit pos="3">MC inband bar with incorrect ttype</bit>
+ <bit pos="4">MC multiple BAR hit</bit>
+ <bit pos="5">Command list early hang trigger activated</bit>
+ <bit pos="6">reserved</bit>
+ <bit pos="7">reserved</bit>
+ <bit pos="8">Command list state machine timeout</bit>
+ <bit pos="9">reserved</bit>
+ <bit pos="10">reserved</bit>
+ <bit pos="11">WAT0 event occurred</bit>
+ <bit pos="12">WAT1 event occurred</bit>
+ <bit pos="13">WAT2 event occurred</bit>
+ <bit pos="14">WAT3 event occurred</bit>
<bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
<bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
- <bit pos="17">Parity Error in WAT/Debug config register.</bit>
+ <bit pos="17">Parity Error in WAT/Debug config register</bit>
<bit pos="18">PBI received overcommit signal from READ0</bit>
<bit pos="19">PBI received ocercommit signal from READ1</bit>
<bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
- <bit pos="21">Reserved[21].</bit>
- <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
- <bit pos="23">Caused by multiple sync commands being received by an MC at a time, or while one is pending</bit>
+ <bit pos="21">reserved</bit>
+ <bit pos="22">Secure mem facility access privilege error by originating thread</bit>
+ <bit pos="23">Multiple sync cmds received by an MC, or while one is pending</bit>
</attn_node>
diff --git a/xml/p10/node_mc_fir_p10_10.xml b/xml/p10/node_mc_fir_p10_10.xml
index cac4ae2..e53b851 100644
--- a/xml/p10/node_mc_fir_p10_10.xml
+++ b/xml/p10/node_mc_fir_p10_10.xml
@@ -11,28 +11,51 @@
<action attn_type="UCS" config="110"/>
<action attn_type="HA" config="001"/>
</local_fir>
- <bit pos="0">If '1', a MC recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
- <bit pos="1">If 1, a MC non-recoverable error was detected. See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
- <bit pos="2">If '1', an PowerBus protocol error was detected. (for example, a HPC_WR is snooped when a HPC_WR to the same address is active).</bit>
- <bit pos="3">If '1', a command was issued to inband address space using a</bit>
- <bit pos="4">If '1', an address match on more that one Memory BAR was detected.</bit>
- <bit pos="5">If set, the ECC syndrome for PowerBus write data is non-zero (for chan0/1 in pbi01, chann2/3 in pbi23)</bit>
- <bit pos="6">Reserved[6].</bit>
- <bit pos="7">Reserved[7].</bit>
- <bit pos="8">If '1', a command list state machine has timed out.</bit>
- <bit pos="9">Reserved[9].</bit>
- <bit pos="10">Reserved[10].</bit>
- <bit pos="11">If '1', a MCS WAT0 event has occurred.</bit>
- <bit pos="12">If '1', a MCS WAT1 event has occurred.</bit>
- <bit pos="13">If '1', a MCS WAT2 event has occurred.</bit>
- <bit pos="14">If '1', a MCS WAT3 event has occurred.</bit>
+ <register name="MC_ERR_RPT0">
+ <instance addr="0x0C010C1E" reg_inst="0"/>
+ <instance addr="0x0D010C1E" reg_inst="1"/>
+ <instance addr="0x0E010C1E" reg_inst="2"/>
+ <instance addr="0x0F010C1E" reg_inst="3"/>
+ </register>
+ <register name="MC_ERR_RPT1">
+ <instance addr="0x0C010C1F" reg_inst="0"/>
+ <instance addr="0x0D010C1F" reg_inst="1"/>
+ <instance addr="0x0E010C1F" reg_inst="2"/>
+ <instance addr="0x0F010C1F" reg_inst="3"/>
+ </register>
+ <register name="MC_ERR_RPT2">
+ <instance addr="0x0C010C1A" reg_inst="0"/>
+ <instance addr="0x0D010C1A" reg_inst="1"/>
+ <instance addr="0x0E010C1A" reg_inst="2"/>
+ <instance addr="0x0F010C1A" reg_inst="3"/>
+ </register>
+ <capture_group node_inst="0:3">
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT0" />
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT1" />
+ <capture_register reg_inst="0:3" reg_name="MC_ERR_RPT2" />
+ </capture_group>
+ <bit pos="0">MC internal recoverable error</bit>
+ <bit pos="1">MC internal non-recoverable error</bit>
+ <bit pos="2">MC powerbus protocol error</bit>
+ <bit pos="3">MC inband bar with incorrect ttype</bit>
+ <bit pos="4">MC multiple BAR hit</bit>
+ <bit pos="5">Non-zero ECC syndrome for PowerBus write data</bit>
+ <bit pos="6">reserved</bit>
+ <bit pos="7">reserved</bit>
+ <bit pos="8">Command list state machine timeout</bit>
+ <bit pos="9">reserved</bit>
+ <bit pos="10">reserved</bit>
+ <bit pos="11">WAT0 event occurred</bit>
+ <bit pos="12">WAT1 event occurred</bit>
+ <bit pos="13">WAT2 event occurred</bit>
+ <bit pos="14">WAT3 event occurred</bit>
<bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
<bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
- <bit pos="17">Parity Error in WAT/Debug config register.</bit>
- <bit pos="18">Reserved[18].</bit>
- <bit pos="19">Reserved[19].</bit>
+ <bit pos="17">Parity Error in WAT/Debug config register</bit>
+ <bit pos="18">reserved</bit>
+ <bit pos="19">reserved</bit>
<bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
- <bit pos="21">Reserved[21].</bit>
- <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
- <bit pos="23">Caused by multiple sync commands being received by an MC at a time, or while one is pending</bit>
+ <bit pos="21">reserved</bit>
+ <bit pos="22">Secure mem facility access privilege error by originating thread</bit>
+ <bit pos="23">Multiple sync cmds received by an MC, or while one is pending</bit>
</attn_node>
diff --git a/xml/p10/node_mc_misc_fir.xml b/xml/p10/node_mc_misc_fir.xml
index 7178c37..90732ce 100644
--- a/xml/p10/node_mc_misc_fir.xml
+++ b/xml/p10/node_mc_misc_fir.xml
@@ -11,16 +11,25 @@
<action attn_type="UCS" config="110"/>
<action attn_type="HA" config="001"/>
</local_fir>
- <bit pos="0">WAT Debug Bus Attention. This is a way for the WAT debug bus to trigger an attention.</bit>
- <bit pos="1">SCOM DBGSRC Register parity Error. Indicates that control register for Debug logic has taken a parity error.</bit>
- <bit pos="2">SCOM Recoverable Register Parity Error. This bit is set when a recoverable parity error on SCOM registers AACR or MCDBG_SCOM_CFG takes place. These register errors are config-related, unable to corrupt data or mainline.</bit>
- <bit pos="3">Spare fir; hooked up to the parity error dectect of the SPARE scom register</bit>
- <bit pos="4">Indicates that an application interrupt was received from the OCMB on</bit>
- <bit pos="5">Indicates that an application interrupt was received from the OCMB on</bit>
- <bit pos="6">Indicates that an application interrupt was received from the OCMB on</bit>
- <bit pos="7">Indicates that an application interrupt was received from the OCMB on</bit>
- <bit pos="8">Parity Error taken on MCEBUSEN[0,1,2,3] regs.</bit>
- <bit pos="9">Parity Error taken on WAT* Regs.</bit>
- <bit pos="10">Reserved Fir Bit 10.</bit>
- <bit pos="11">Reserved Fir Bit 11.</bit>
+ <register name="MC_MISC_ERR_RPT">
+ <instance addr="0x0C010FE7" reg_inst="0"/>
+ <instance addr="0x0D010FE7" reg_inst="1"/>
+ <instance addr="0x0E010FE7" reg_inst="2"/>
+ <instance addr="0x0F010FE7" reg_inst="3"/>
+ </register>
+ <capture_group node_inst="0:3">
+ <capture_register reg_inst="0:3" reg_name="MC_MISC_ERR_RPT" />
+ </capture_group>
+ <bit pos="0">WAT Debug Bus Attention</bit>
+ <bit pos="1">SCOM DBGSRC Register parity Error</bit>
+ <bit pos="2">SCOM Recoverable Register Parity Error</bit>
+ <bit pos="3">spare</bit>
+ <bit pos="4">Application interrupt received from OCMB on channel 0, subchannel A</bit>
+ <bit pos="5">Application interrupt received from OCMB on channel 0, subchannel B</bit>
+ <bit pos="6">Application interrupt received from OCMB on channel 1, subchannel A</bit>
+ <bit pos="7">Application interrupt received from OCMB on channel 1, subchannel B</bit>
+ <bit pos="8">Parity Error taken on MCEBUSEN[0,1,2,3] regs</bit>
+ <bit pos="9">Parity Error taken on WAT* Regs</bit>
+ <bit pos="10">Reserved</bit>
+ <bit pos="11">Reserved</bit>
</attn_node>