Split remaining chiplet XML files by attn type
This really isn't necessary, but since most of the other chiplet files
are split, this change is only to maintain consistency.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ieb4b5eea582e0c3dbc010cdb2c0bac1dc89386fe
diff --git a/xml/p10/node_cfir_iohs_ha.xml b/xml/p10/node_cfir_iohs_ha.xml
new file mode 100644
index 0000000..5fe6507
--- /dev/null
+++ b/xml/p10/node_cfir_iohs_ha.xml
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_HA" reg_type="SCOM">
+ <register name="CFIR_IOHS_HA">
+ <instance addr="0x18040004" reg_inst="0"/>
+ <instance addr="0x19040004" reg_inst="1"/>
+ <instance addr="0x1A040004" reg_inst="2"/>
+ <instance addr="0x1B040004" reg_inst="3"/>
+ <instance addr="0x1C040004" reg_inst="4"/>
+ <instance addr="0x1D040004" reg_inst="5"/>
+ <instance addr="0x1E040004" reg_inst="6"/>
+ <instance addr="0x1F040004" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_HA_MASK">
+ <instance addr="0x18040044" reg_inst="0"/>
+ <instance addr="0x19040044" reg_inst="1"/>
+ <instance addr="0x1A040044" reg_inst="2"/>
+ <instance addr="0x1B040044" reg_inst="3"/>
+ <instance addr="0x1C040044" reg_inst="4"/>
+ <instance addr="0x1D040044" reg_inst="5"/>
+ <instance addr="0x1E040044" reg_inst="6"/>
+ <instance addr="0x1F040044" reg_inst="7"/>
+ </register>
+ <rule attn_type="HA" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_HA"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_HA_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_iohs_ucs.xml b/xml/p10/node_cfir_iohs_ucs.xml
new file mode 100644
index 0000000..05e771c
--- /dev/null
+++ b/xml/p10/node_cfir_iohs_ucs.xml
@@ -0,0 +1,33 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_UCS" reg_type="SCOM">
+ <register name="CFIR_IOHS_UCS">
+ <instance addr="0x18040003" reg_inst="0"/>
+ <instance addr="0x19040003" reg_inst="1"/>
+ <instance addr="0x1A040003" reg_inst="2"/>
+ <instance addr="0x1B040003" reg_inst="3"/>
+ <instance addr="0x1C040003" reg_inst="4"/>
+ <instance addr="0x1D040003" reg_inst="5"/>
+ <instance addr="0x1E040003" reg_inst="6"/>
+ <instance addr="0x1F040003" reg_inst="7"/>
+ </register>
+ <register name="CFIR_IOHS_UCS_MASK">
+ <instance addr="0x18040043" reg_inst="0"/>
+ <instance addr="0x19040043" reg_inst="1"/>
+ <instance addr="0x1A040043" reg_inst="2"/>
+ <instance addr="0x1B040043" reg_inst="3"/>
+ <instance addr="0x1C040043" reg_inst="4"/>
+ <instance addr="0x1D040043" reg_inst="5"/>
+ <instance addr="0x1E040043" reg_inst="6"/>
+ <instance addr="0x1F040043" reg_inst="7"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0:7">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_IOHS_UCS"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_IOHS_UCS_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_iohs_ucs_ha.xml b/xml/p10/node_cfir_iohs_ucs_ha.xml
deleted file mode 100644
index 8f6ce62..0000000
--- a/xml/p10/node_cfir_iohs_ucs_ha.xml
+++ /dev/null
@@ -1,62 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_UCS_HA" reg_type="SCOM">
- <register name="CFIR_IOHS_UCS">
- <instance addr="0x18040003" reg_inst="0"/>
- <instance addr="0x19040003" reg_inst="1"/>
- <instance addr="0x1A040003" reg_inst="2"/>
- <instance addr="0x1B040003" reg_inst="3"/>
- <instance addr="0x1C040003" reg_inst="4"/>
- <instance addr="0x1D040003" reg_inst="5"/>
- <instance addr="0x1E040003" reg_inst="6"/>
- <instance addr="0x1F040003" reg_inst="7"/>
- </register>
- <register name="CFIR_IOHS_UCS_MASK">
- <instance addr="0x18040043" reg_inst="0"/>
- <instance addr="0x19040043" reg_inst="1"/>
- <instance addr="0x1A040043" reg_inst="2"/>
- <instance addr="0x1B040043" reg_inst="3"/>
- <instance addr="0x1C040043" reg_inst="4"/>
- <instance addr="0x1D040043" reg_inst="5"/>
- <instance addr="0x1E040043" reg_inst="6"/>
- <instance addr="0x1F040043" reg_inst="7"/>
- </register>
- <register name="CFIR_IOHS_HA">
- <instance addr="0x18040004" reg_inst="0"/>
- <instance addr="0x19040004" reg_inst="1"/>
- <instance addr="0x1A040004" reg_inst="2"/>
- <instance addr="0x1B040004" reg_inst="3"/>
- <instance addr="0x1C040004" reg_inst="4"/>
- <instance addr="0x1D040004" reg_inst="5"/>
- <instance addr="0x1E040004" reg_inst="6"/>
- <instance addr="0x1F040004" reg_inst="7"/>
- </register>
- <register name="CFIR_IOHS_HA_MASK">
- <instance addr="0x18040044" reg_inst="0"/>
- <instance addr="0x19040044" reg_inst="1"/>
- <instance addr="0x1A040044" reg_inst="2"/>
- <instance addr="0x1B040044" reg_inst="3"/>
- <instance addr="0x1C040044" reg_inst="4"/>
- <instance addr="0x1D040044" reg_inst="5"/>
- <instance addr="0x1E040044" reg_inst="6"/>
- <instance addr="0x1F040044" reg_inst="7"/>
- </register>
- <rule attn_type="UCS" node_inst="0:7">
- <expr type="and">
- <expr type="reg" value1="CFIR_IOHS_UCS"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_IOHS_UCS_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <rule attn_type="HA" node_inst="0:7">
- <expr type="and">
- <expr type="reg" value1="CFIR_IOHS_HA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_IOHS_HA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
-</attn_node>
diff --git a/xml/p10/node_cfir_mc_ucs_ha.xml b/xml/p10/node_cfir_mc_ha.xml
similarity index 63%
rename from xml/p10/node_cfir_mc_ucs_ha.xml
rename to xml/p10/node_cfir_mc_ha.xml
index 730c504..5b82c6c 100644
--- a/xml/p10/node_cfir_mc_ucs_ha.xml
+++ b/xml/p10/node_cfir_mc_ha.xml
@@ -1,17 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_UCS_HA" reg_type="SCOM">
- <register name="CFIR_MC_UCS">
- <instance addr="0x0C040003" reg_inst="0"/>
- <instance addr="0x0D040003" reg_inst="1"/>
- <instance addr="0x0E040003" reg_inst="2"/>
- <instance addr="0x0F040003" reg_inst="3"/>
- </register>
- <register name="CFIR_MC_UCS_MASK">
- <instance addr="0x0C040043" reg_inst="0"/>
- <instance addr="0x0D040043" reg_inst="1"/>
- <instance addr="0x0E040043" reg_inst="2"/>
- <instance addr="0x0F040043" reg_inst="3"/>
- </register>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_HA" reg_type="SCOM">
<register name="CFIR_MC_HA">
<instance addr="0x0C040004" reg_inst="0"/>
<instance addr="0x0D040004" reg_inst="1"/>
@@ -24,15 +12,6 @@
<instance addr="0x0E040044" reg_inst="2"/>
<instance addr="0x0F040044" reg_inst="3"/>
</register>
- <rule attn_type="UCS" node_inst="0:3">
- <expr type="and">
- <expr type="reg" value1="CFIR_MC_UCS"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_MC_UCS_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
<rule attn_type="HA" node_inst="0:3">
<expr type="and">
<expr type="reg" value1="CFIR_MC_HA"/>
diff --git a/xml/p10/node_cfir_mc_ucs_ha.xml b/xml/p10/node_cfir_mc_ucs.xml
similarity index 63%
copy from xml/p10/node_cfir_mc_ucs_ha.xml
copy to xml/p10/node_cfir_mc_ucs.xml
index 730c504..fa50cae 100644
--- a/xml/p10/node_cfir_mc_ucs_ha.xml
+++ b/xml/p10/node_cfir_mc_ucs.xml
@@ -1,5 +1,5 @@
<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_UCS_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_UCS" reg_type="SCOM">
<register name="CFIR_MC_UCS">
<instance addr="0x0C040003" reg_inst="0"/>
<instance addr="0x0D040003" reg_inst="1"/>
@@ -12,18 +12,6 @@
<instance addr="0x0E040043" reg_inst="2"/>
<instance addr="0x0F040043" reg_inst="3"/>
</register>
- <register name="CFIR_MC_HA">
- <instance addr="0x0C040004" reg_inst="0"/>
- <instance addr="0x0D040004" reg_inst="1"/>
- <instance addr="0x0E040004" reg_inst="2"/>
- <instance addr="0x0F040004" reg_inst="3"/>
- </register>
- <register name="CFIR_MC_HA_MASK">
- <instance addr="0x0C040044" reg_inst="0"/>
- <instance addr="0x0D040044" reg_inst="1"/>
- <instance addr="0x0E040044" reg_inst="2"/>
- <instance addr="0x0F040044" reg_inst="3"/>
- </register>
<rule attn_type="UCS" node_inst="0:3">
<expr type="and">
<expr type="reg" value1="CFIR_MC_UCS"/>
@@ -33,15 +21,6 @@
<expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
</expr>
</rule>
- <rule attn_type="HA" node_inst="0:3">
- <expr type="and">
- <expr type="reg" value1="CFIR_MC_HA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_MC_HA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
<bit child_node="MC_LOCAL_FIR" node_inst="0,1,2,3" pos="4">Attention from MC_LOCAL_FIR</bit>
<bit child_node="MC_DSTL_FIR" node_inst="0,2,4,6" pos="5">Attention from MC_DSTL_FIR 0</bit>
<bit child_node="MC_USTL_FIR" node_inst="0,2,4,6" pos="6">Attention from MC_USTL_FIR 0</bit>
diff --git a/xml/p10/node_cfir_pci_ha.xml b/xml/p10/node_cfir_pci_ha.xml
new file mode 100644
index 0000000..9aae28e
--- /dev/null
+++ b/xml/p10/node_cfir_pci_ha.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_HA" reg_type="SCOM">
+ <register name="CFIR_PCI_HA">
+ <instance addr="0x08040004" reg_inst="0"/>
+ <instance addr="0x09040004" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_HA_MASK">
+ <instance addr="0x08040044" reg_inst="0"/>
+ <instance addr="0x09040044" reg_inst="1"/>
+ </register>
+ <rule attn_type="HA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_HA"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_HA_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_spa.xml b/xml/p10/node_cfir_pci_spa.xml
new file mode 100644
index 0000000..a57ddc6
--- /dev/null
+++ b/xml/p10/node_cfir_pci_spa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_SPA" reg_type="SCOM">
+ <register name="CFIR_PCI_SPA">
+ <instance addr="0x08040002" reg_inst="0"/>
+ <instance addr="0x09040002" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PCI_SPA_MASK">
+ <instance addr="0x08040042" reg_inst="0"/>
+ <instance addr="0x09040042" reg_inst="1"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PCI_SPA"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PCI_SPA_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_spa_ha.xml b/xml/p10/node_cfir_pci_spa_ha.xml
deleted file mode 100644
index 21f8adb..0000000
--- a/xml/p10/node_cfir_pci_spa_ha.xml
+++ /dev/null
@@ -1,38 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_SPA_HA" reg_type="SCOM">
- <register name="CFIR_PCI_SPA">
- <instance addr="0x08040002" reg_inst="0"/>
- <instance addr="0x09040002" reg_inst="1"/>
- </register>
- <register name="CFIR_PCI_SPA_MASK">
- <instance addr="0x08040042" reg_inst="0"/>
- <instance addr="0x09040042" reg_inst="1"/>
- </register>
- <register name="CFIR_PCI_HA">
- <instance addr="0x08040004" reg_inst="0"/>
- <instance addr="0x09040004" reg_inst="1"/>
- </register>
- <register name="CFIR_PCI_HA_MASK">
- <instance addr="0x08040044" reg_inst="0"/>
- <instance addr="0x09040044" reg_inst="1"/>
- </register>
- <rule attn_type="SPA" node_inst="0:1">
- <expr type="and">
- <expr type="reg" value1="CFIR_PCI_SPA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_PCI_SPA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <rule attn_type="HA" node_inst="0:1">
- <expr type="and">
- <expr type="reg" value1="CFIR_PCI_HA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_PCI_HA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <bit child_node="PCI_LOCAL_FIR" node_inst="0,1" pos="4">Attention from PCI_LOCAL_FIR</bit>
-</attn_node>
diff --git a/xml/p10/node_cfir_tp_ha.xml b/xml/p10/node_cfir_tp_ha.xml
new file mode 100644
index 0000000..9649730
--- /dev/null
+++ b/xml/p10/node_cfir_tp_ha.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_HA" reg_type="SCOM">
+ <register name="CFIR_TP_HA">
+ <instance addr="0x01040004" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_HA_MASK">
+ <instance addr="0x01040044" reg_inst="0"/>
+ </register>
+ <rule attn_type="HA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_HA"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_HA_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_tp_spa.xml b/xml/p10/node_cfir_tp_spa.xml
new file mode 100644
index 0000000..c3d3b37
--- /dev/null
+++ b/xml/p10/node_cfir_tp_spa.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_SPA" reg_type="SCOM">
+ <register name="CFIR_TP_SPA">
+ <instance addr="0x01040002" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_SPA_MASK">
+ <instance addr="0x01040042" reg_inst="0"/>
+ </register>
+ <rule attn_type="SPA" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_SPA"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_SPA_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_tp_spa_ucs_ha.xml b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
deleted file mode 100644
index f189f01..0000000
--- a/xml/p10/node_cfir_tp_spa_ucs_ha.xml
+++ /dev/null
@@ -1,49 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_SPA_UCS_HA" reg_type="SCOM">
- <register name="CFIR_TP_SPA">
- <instance addr="0x01040002" reg_inst="0"/>
- </register>
- <register name="CFIR_TP_SPA_MASK">
- <instance addr="0x01040042" reg_inst="0"/>
- </register>
- <register name="CFIR_TP_UCS">
- <instance addr="0x01040003" reg_inst="0"/>
- </register>
- <register name="CFIR_TP_UCS_MASK">
- <instance addr="0x01040043" reg_inst="0"/>
- </register>
- <register name="CFIR_TP_HA">
- <instance addr="0x01040004" reg_inst="0"/>
- </register>
- <register name="CFIR_TP_HA_MASK">
- <instance addr="0x01040044" reg_inst="0"/>
- </register>
- <rule attn_type="SPA" node_inst="0">
- <expr type="and">
- <expr type="reg" value1="CFIR_TP_SPA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_TP_SPA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <rule attn_type="UCS" node_inst="0">
- <expr type="and">
- <expr type="reg" value1="CFIR_TP_UCS"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_TP_UCS_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <rule attn_type="HA" node_inst="0">
- <expr type="and">
- <expr type="reg" value1="CFIR_TP_HA"/>
- <expr type="not">
- <expr type="reg" value1="CFIR_TP_HA_MASK"/>
- </expr>
- <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
- </expr>
- </rule>
- <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
-</attn_node>
diff --git a/xml/p10/node_cfir_tp_ucs.xml b/xml/p10/node_cfir_tp_ucs.xml
new file mode 100644
index 0000000..e265fe3
--- /dev/null
+++ b/xml/p10/node_cfir_tp_ucs.xml
@@ -0,0 +1,19 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_UCS" reg_type="SCOM">
+ <register name="CFIR_TP_UCS">
+ <instance addr="0x01040003" reg_inst="0"/>
+ </register>
+ <register name="CFIR_TP_UCS_MASK">
+ <instance addr="0x01040043" reg_inst="0"/>
+ </register>
+ <rule attn_type="UCS" node_inst="0">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_TP_UCS"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_TP_UCS_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="TP_LOCAL_FIR" node_inst="0" pos="4">Attention from TP_LOCAL_FIR</bit>
+</attn_node>
diff --git a/xml/p10/node_gfir_ha.xml b/xml/p10/node_gfir_ha.xml
index d3b96b2..5497b65 100644
--- a/xml/p10/node_gfir_ha.xml
+++ b/xml/p10/node_gfir_ha.xml
@@ -6,27 +6,27 @@
<rule attn_type="HA" node_inst="0">
<expr type="reg" value1="GFIR_HA"/>
</rule>
- <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+ <bit child_node="CFIR_TP_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
<bit child_node="CFIR_N0_HA" node_inst="0" pos="2">Attention from N0 chiplet</bit>
<bit child_node="CFIR_N1_HA" node_inst="0" pos="3">Attention from N1 chiplet</bit>
- <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
- <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+ <bit child_node="CFIR_PCI_HA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+ <bit child_node="CFIR_PCI_HA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+ <bit child_node="CFIR_MC_HA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+ <bit child_node="CFIR_MC_HA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+ <bit child_node="CFIR_MC_HA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+ <bit child_node="CFIR_MC_HA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
<bit child_node="CFIR_PAUE_HA" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
<bit child_node="CFIR_PAUE_HA" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
<bit child_node="CFIR_PAUW_HA" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
<bit child_node="CFIR_PAUW_HA" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+ <bit child_node="CFIR_IOHS_HA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
<bit child_node="CFIR_EQ_HA" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
<bit child_node="CFIR_EQ_HA" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
<bit child_node="CFIR_EQ_HA" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>
diff --git a/xml/p10/node_gfir_spa.xml b/xml/p10/node_gfir_spa.xml
index ea66b91..f178a86 100644
--- a/xml/p10/node_gfir_spa.xml
+++ b/xml/p10/node_gfir_spa.xml
@@ -6,11 +6,11 @@
<rule attn_type="SPA" node_inst="0">
<expr type="reg" value1="GFIR_SPA"/>
</rule>
- <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+ <bit child_node="CFIR_TP_SPA" node_inst="0" pos="1">Attention from TP chiplet</bit>
<bit child_node="CFIR_N0_SPA" node_inst="0" pos="2">Attention from N0 chiplet</bit>
<bit child_node="CFIR_N1_SPA" node_inst="0" pos="3">Attention from N1 chiplet</bit>
- <bit child_node="CFIR_PCI_SPA_HA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
- <bit child_node="CFIR_PCI_SPA_HA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
+ <bit child_node="CFIR_PCI_SPA" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
+ <bit child_node="CFIR_PCI_SPA" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
<bit child_node="CFIR_MC_SPA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
<bit child_node="CFIR_MC_SPA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
<bit child_node="CFIR_MC_SPA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
diff --git a/xml/p10/node_gfir_ucs.xml b/xml/p10/node_gfir_ucs.xml
index 3e19406..ce1d04c 100644
--- a/xml/p10/node_gfir_ucs.xml
+++ b/xml/p10/node_gfir_ucs.xml
@@ -6,27 +6,27 @@
<rule attn_type="UCS" node_inst="0">
<expr type="reg" value1="GFIR_UCS"/>
</rule>
- <bit child_node="CFIR_TP_SPA_UCS_HA" node_inst="0" pos="1">Attention from TP chiplet</bit>
+ <bit child_node="CFIR_TP_UCS" node_inst="0" pos="1">Attention from TP chiplet</bit>
<bit child_node="CFIR_N0_UCS" node_inst="0" pos="2">Attention from N0 chiplet</bit>
<bit child_node="CFIR_N1_UCS" node_inst="0" pos="3">Attention from N1 chiplet</bit>
<bit child_node="CFIR_PCI_UCS" node_inst="0" pos="8">Attention from PCI 0 chiplet</bit>
<bit child_node="CFIR_PCI_UCS" node_inst="1" pos="9">Attention from PCI 1 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
- <bit child_node="CFIR_MC_UCS_HA" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
+ <bit child_node="CFIR_MC_UCS" node_inst="0" pos="12">Attention from MC 0 chiplet</bit>
+ <bit child_node="CFIR_MC_UCS" node_inst="1" pos="13">Attention from MC 1 chiplet</bit>
+ <bit child_node="CFIR_MC_UCS" node_inst="2" pos="14">Attention from MC 2 chiplet</bit>
+ <bit child_node="CFIR_MC_UCS" node_inst="3" pos="15">Attention from MC 3 chiplet</bit>
<bit child_node="CFIR_PAUE_UCS" node_inst="0" pos="16">Attention from PAU 0 chiplet</bit>
<bit child_node="CFIR_PAUE_UCS" node_inst="1" pos="17">Attention from PAU 1 chiplet</bit>
<bit child_node="CFIR_PAUW_UCS" node_inst="0" pos="18">Attention from PAU 2 chiplet</bit>
<bit child_node="CFIR_PAUW_UCS" node_inst="1" pos="19">Attention from PAU 3 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
- <bit child_node="CFIR_IOHS_UCS_HA" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="0" pos="24">Attention from IOHS 0 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="1" pos="25">Attention from IOHS 1 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="2" pos="26">Attention from IOHS 2 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="3" pos="27">Attention from IOHS 3 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="4" pos="28">Attention from IOHS 4 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="5" pos="29">Attention from IOHS 5 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="6" pos="30">Attention from IOHS 6 chiplet</bit>
+ <bit child_node="CFIR_IOHS_UCS" node_inst="7" pos="31">Attention from IOHS 7 chiplet</bit>
<bit child_node="CFIR_EQ_UCS" node_inst="0" pos="32">Attention from EQ 0 chiplet</bit>
<bit child_node="CFIR_EQ_UCS" node_inst="1" pos="33">Attention from EQ 1 chiplet</bit>
<bit child_node="CFIR_EQ_UCS" node_inst="2" pos="34">Attention from EQ 2 chiplet</bit>