commit 7c8faa1405313088e5e9716a0b1601993d93a2cc
author Zane Shelley <zshelle@us.ibm.com> Mon Oct 28 22:26:28 2019 -0500
committer Zane Shelley <zshelle@us.ibm.com> Thu Oct 31 12:27:02 2019 -0500
tree 2077ac43896609888a51240769862e25c0b85246
parent c477199812321648c62f29f0a9372d8303224c09

The Road to Clang-Format part 6

Whitespace: The Voyage Home

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I94f8f7a5ef54e149991daeaf798eaf6a0c8ba59c

src/register/hei_hardware_register.cpp

diff --git a/src/register/hei_hardware_register.cpp b/src/register/hei_hardware_register.cpp
old mode 100755
new mode 100644
index 6b66eb9..7df5a3e
--- a/src/register/hei_hardware_register.cpp
+++ b/src/register/hei_hardware_register.cpp
@@ -33,8 +33,8 @@
     // will be created in the cache, if it does not exist, when the cache is
     // accessed below.
 
-    if ((REG_ACCESS_NONE != getAccessLevel()) &&
-        (REG_ACCESS_WO   != getAccessLevel()))
+    auto al = getAccessLevel();
+    if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al))
     {
         read(i_chip);
     }
@@ -55,8 +55,8 @@
     // will be created in the cache, if it does not exist, when the cache is
     // accessed below.
 
-    if ((REG_ACCESS_NONE != getAccessLevel()) &&
-        (REG_ACCESS_WO   != getAccessLevel()))
+    auto al = getAccessLevel();
+    if ((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al))
     {
         read(i_chip);
     }
@@ -78,8 +78,8 @@
     if (i_force || !queryCache(i_chip))
     {
         // This register must be readable.
-        HEI_ASSERT((REG_ACCESS_NONE != getAccessLevel()) &&
-                   (REG_ACCESS_WO   != getAccessLevel()));
+        auto al = getAccessLevel();
+        HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_WO != al));
 
         // Get the buffer from the register cache.
         BitString& bs = accessCache(i_chip);
@@ -119,8 +119,8 @@
     verifyAccessorChip(i_chip);
 
     // This register must be writable.
-    HEI_ASSERT((REG_ACCESS_NONE != getAccessLevel()) &&
-               (REG_ACCESS_RO   != getAccessLevel()));
+    auto al = getAccessLevel();
+    HEI_ASSERT((REG_ACCESS_NONE != al) && (REG_ACCESS_RO != al));
 
     // An entry for this register must exist in the cache.
     HEI_ASSERT(queryCache(i_chip));
@@ -182,6 +182,7 @@
     if (!query(i_chip, i_hwReg))
     {
         BitString* bs = new BitStringBuffer{i_hwReg->getSize() * 8};
+
         iv_cache[i_chip][i_hwReg] = bs;
     }