Chip data file updates for N1 chiplet

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I45457b4d9bc74781b364cf3b062928e1396e82e2
diff --git a/xml/p10/node_psihb_fir.xml b/xml/p10/node_psihb_fir.xml
index fa6cde8..e4edc34 100644
--- a/xml/p10/node_psihb_fir.xml
+++ b/xml/p10/node_psihb_fir.xml
@@ -19,18 +19,18 @@
     <bit pos="11">PB parity error</bit>
     <bit pos="12">FSP tried access to trusted space</bit>
     <bit pos="13">Unexpected PB CRESP or DATA</bit>
-    <bit pos="14">Spare firs tied to zero</bit>
-    <bit pos="15">Spare firs tied to zero</bit>
-    <bit pos="16">Spare firs tied to zero</bit>
-    <bit pos="17">Spare firs tied to zero</bit>
-    <bit pos="18">Spare firs tied to zero</bit>
-    <bit pos="19">Spare firs tied to zero</bit>
-    <bit pos="20">Spare firs tied to zero</bit>
+    <bit pos="14">reserved</bit>
+    <bit pos="15">reserved</bit>
+    <bit pos="16">reserved</bit>
+    <bit pos="17">reserved</bit>
+    <bit pos="18">reserved</bit>
+    <bit pos="19">reserved</bit>
+    <bit pos="20">reserved</bit>
     <bit pos="21">PSI global error bit 0</bit>
     <bit pos="22">PSI global error bit 1</bit>
     <bit pos="23">Upstream error</bit>
-    <bit pos="24">Spare fir</bit>
-    <bit pos="25">Spare fir</bit>
-    <bit pos="26">Spare fir</bit>
+    <bit pos="24">spare</bit>
+    <bit pos="25">spare</bit>
+    <bit pos="26">spare</bit>
     <bit pos="27">fir parity Error</bit>
 </attn_node>