| <?xml version="1.0" encoding="UTF-8"?> |
| <attn_node model_ec="P10_20" name="EQ_CORE_FIR" reg_type="SCOM"> |
| <register name="EQ_CORE_FIR"> |
| <instance addr="0x20028440" reg_inst="0"/> |
| <instance addr="0x20024440" reg_inst="1"/> |
| <instance addr="0x20022440" reg_inst="2"/> |
| <instance addr="0x20021440" reg_inst="3"/> |
| <instance addr="0x21028440" reg_inst="4"/> |
| <instance addr="0x21024440" reg_inst="5"/> |
| <instance addr="0x21022440" reg_inst="6"/> |
| <instance addr="0x21021440" reg_inst="7"/> |
| <instance addr="0x22028440" reg_inst="8"/> |
| <instance addr="0x22024440" reg_inst="9"/> |
| <instance addr="0x22022440" reg_inst="10"/> |
| <instance addr="0x22021440" reg_inst="11"/> |
| <instance addr="0x23028440" reg_inst="12"/> |
| <instance addr="0x23024440" reg_inst="13"/> |
| <instance addr="0x23022440" reg_inst="14"/> |
| <instance addr="0x23021440" reg_inst="15"/> |
| <instance addr="0x24028440" reg_inst="16"/> |
| <instance addr="0x24024440" reg_inst="17"/> |
| <instance addr="0x24022440" reg_inst="18"/> |
| <instance addr="0x24021440" reg_inst="19"/> |
| <instance addr="0x25028440" reg_inst="20"/> |
| <instance addr="0x25024440" reg_inst="21"/> |
| <instance addr="0x25022440" reg_inst="22"/> |
| <instance addr="0x25021440" reg_inst="23"/> |
| <instance addr="0x26028440" reg_inst="24"/> |
| <instance addr="0x26024440" reg_inst="25"/> |
| <instance addr="0x26022440" reg_inst="26"/> |
| <instance addr="0x26021440" reg_inst="27"/> |
| <instance addr="0x27028440" reg_inst="28"/> |
| <instance addr="0x27024440" reg_inst="29"/> |
| <instance addr="0x27022440" reg_inst="30"/> |
| <instance addr="0x27021440" reg_inst="31"/> |
| </register> |
| <register name="EQ_CORE_FIR_MASK"> |
| <instance addr="0x20028443" reg_inst="0"/> |
| <instance addr="0x20024443" reg_inst="1"/> |
| <instance addr="0x20022443" reg_inst="2"/> |
| <instance addr="0x20021443" reg_inst="3"/> |
| <instance addr="0x21028443" reg_inst="4"/> |
| <instance addr="0x21024443" reg_inst="5"/> |
| <instance addr="0x21022443" reg_inst="6"/> |
| <instance addr="0x21021443" reg_inst="7"/> |
| <instance addr="0x22028443" reg_inst="8"/> |
| <instance addr="0x22024443" reg_inst="9"/> |
| <instance addr="0x22022443" reg_inst="10"/> |
| <instance addr="0x22021443" reg_inst="11"/> |
| <instance addr="0x23028443" reg_inst="12"/> |
| <instance addr="0x23024443" reg_inst="13"/> |
| <instance addr="0x23022443" reg_inst="14"/> |
| <instance addr="0x23021443" reg_inst="15"/> |
| <instance addr="0x24028443" reg_inst="16"/> |
| <instance addr="0x24024443" reg_inst="17"/> |
| <instance addr="0x24022443" reg_inst="18"/> |
| <instance addr="0x24021443" reg_inst="19"/> |
| <instance addr="0x25028443" reg_inst="20"/> |
| <instance addr="0x25024443" reg_inst="21"/> |
| <instance addr="0x25022443" reg_inst="22"/> |
| <instance addr="0x25021443" reg_inst="23"/> |
| <instance addr="0x26028443" reg_inst="24"/> |
| <instance addr="0x26024443" reg_inst="25"/> |
| <instance addr="0x26022443" reg_inst="26"/> |
| <instance addr="0x26021443" reg_inst="27"/> |
| <instance addr="0x27028443" reg_inst="28"/> |
| <instance addr="0x27024443" reg_inst="29"/> |
| <instance addr="0x27022443" reg_inst="30"/> |
| <instance addr="0x27021443" reg_inst="31"/> |
| </register> |
| <register name="EQ_CORE_FIR_ACT0"> |
| <instance addr="0x20028446" reg_inst="0"/> |
| <instance addr="0x20024446" reg_inst="1"/> |
| <instance addr="0x20022446" reg_inst="2"/> |
| <instance addr="0x20021446" reg_inst="3"/> |
| <instance addr="0x21028446" reg_inst="4"/> |
| <instance addr="0x21024446" reg_inst="5"/> |
| <instance addr="0x21022446" reg_inst="6"/> |
| <instance addr="0x21021446" reg_inst="7"/> |
| <instance addr="0x22028446" reg_inst="8"/> |
| <instance addr="0x22024446" reg_inst="9"/> |
| <instance addr="0x22022446" reg_inst="10"/> |
| <instance addr="0x22021446" reg_inst="11"/> |
| <instance addr="0x23028446" reg_inst="12"/> |
| <instance addr="0x23024446" reg_inst="13"/> |
| <instance addr="0x23022446" reg_inst="14"/> |
| <instance addr="0x23021446" reg_inst="15"/> |
| <instance addr="0x24028446" reg_inst="16"/> |
| <instance addr="0x24024446" reg_inst="17"/> |
| <instance addr="0x24022446" reg_inst="18"/> |
| <instance addr="0x24021446" reg_inst="19"/> |
| <instance addr="0x25028446" reg_inst="20"/> |
| <instance addr="0x25024446" reg_inst="21"/> |
| <instance addr="0x25022446" reg_inst="22"/> |
| <instance addr="0x25021446" reg_inst="23"/> |
| <instance addr="0x26028446" reg_inst="24"/> |
| <instance addr="0x26024446" reg_inst="25"/> |
| <instance addr="0x26022446" reg_inst="26"/> |
| <instance addr="0x26021446" reg_inst="27"/> |
| <instance addr="0x27028446" reg_inst="28"/> |
| <instance addr="0x27024446" reg_inst="29"/> |
| <instance addr="0x27022446" reg_inst="30"/> |
| <instance addr="0x27021446" reg_inst="31"/> |
| </register> |
| <register name="EQ_CORE_FIR_ACT1"> |
| <instance addr="0x20028447" reg_inst="0"/> |
| <instance addr="0x20024447" reg_inst="1"/> |
| <instance addr="0x20022447" reg_inst="2"/> |
| <instance addr="0x20021447" reg_inst="3"/> |
| <instance addr="0x21028447" reg_inst="4"/> |
| <instance addr="0x21024447" reg_inst="5"/> |
| <instance addr="0x21022447" reg_inst="6"/> |
| <instance addr="0x21021447" reg_inst="7"/> |
| <instance addr="0x22028447" reg_inst="8"/> |
| <instance addr="0x22024447" reg_inst="9"/> |
| <instance addr="0x22022447" reg_inst="10"/> |
| <instance addr="0x22021447" reg_inst="11"/> |
| <instance addr="0x23028447" reg_inst="12"/> |
| <instance addr="0x23024447" reg_inst="13"/> |
| <instance addr="0x23022447" reg_inst="14"/> |
| <instance addr="0x23021447" reg_inst="15"/> |
| <instance addr="0x24028447" reg_inst="16"/> |
| <instance addr="0x24024447" reg_inst="17"/> |
| <instance addr="0x24022447" reg_inst="18"/> |
| <instance addr="0x24021447" reg_inst="19"/> |
| <instance addr="0x25028447" reg_inst="20"/> |
| <instance addr="0x25024447" reg_inst="21"/> |
| <instance addr="0x25022447" reg_inst="22"/> |
| <instance addr="0x25021447" reg_inst="23"/> |
| <instance addr="0x26028447" reg_inst="24"/> |
| <instance addr="0x26024447" reg_inst="25"/> |
| <instance addr="0x26022447" reg_inst="26"/> |
| <instance addr="0x26021447" reg_inst="27"/> |
| <instance addr="0x27028447" reg_inst="28"/> |
| <instance addr="0x27024447" reg_inst="29"/> |
| <instance addr="0x27022447" reg_inst="30"/> |
| <instance addr="0x27021447" reg_inst="31"/> |
| </register> |
| <register name="EQ_CORE_FIR_WOF"> |
| <instance addr="0x20028448" reg_inst="0"/> |
| <instance addr="0x20024448" reg_inst="1"/> |
| <instance addr="0x20022448" reg_inst="2"/> |
| <instance addr="0x20021448" reg_inst="3"/> |
| <instance addr="0x21028448" reg_inst="4"/> |
| <instance addr="0x21024448" reg_inst="5"/> |
| <instance addr="0x21022448" reg_inst="6"/> |
| <instance addr="0x21021448" reg_inst="7"/> |
| <instance addr="0x22028448" reg_inst="8"/> |
| <instance addr="0x22024448" reg_inst="9"/> |
| <instance addr="0x22022448" reg_inst="10"/> |
| <instance addr="0x22021448" reg_inst="11"/> |
| <instance addr="0x23028448" reg_inst="12"/> |
| <instance addr="0x23024448" reg_inst="13"/> |
| <instance addr="0x23022448" reg_inst="14"/> |
| <instance addr="0x23021448" reg_inst="15"/> |
| <instance addr="0x24028448" reg_inst="16"/> |
| <instance addr="0x24024448" reg_inst="17"/> |
| <instance addr="0x24022448" reg_inst="18"/> |
| <instance addr="0x24021448" reg_inst="19"/> |
| <instance addr="0x25028448" reg_inst="20"/> |
| <instance addr="0x25024448" reg_inst="21"/> |
| <instance addr="0x25022448" reg_inst="22"/> |
| <instance addr="0x25021448" reg_inst="23"/> |
| <instance addr="0x26028448" reg_inst="24"/> |
| <instance addr="0x26024448" reg_inst="25"/> |
| <instance addr="0x26022448" reg_inst="26"/> |
| <instance addr="0x26021448" reg_inst="27"/> |
| <instance addr="0x27028448" reg_inst="28"/> |
| <instance addr="0x27024448" reg_inst="29"/> |
| <instance addr="0x27022448" reg_inst="30"/> |
| <instance addr="0x27021448" reg_inst="31"/> |
| </register> |
| <register name="HV_PR_STATE"> |
| <instance addr="0x2002840D" reg_inst="0"/> |
| <instance addr="0x2002440D" reg_inst="1"/> |
| <instance addr="0x2002240D" reg_inst="2"/> |
| <instance addr="0x2002140D" reg_inst="3"/> |
| <instance addr="0x2102840D" reg_inst="4"/> |
| <instance addr="0x2102440D" reg_inst="5"/> |
| <instance addr="0x2102240D" reg_inst="6"/> |
| <instance addr="0x2102140D" reg_inst="7"/> |
| <instance addr="0x2202840D" reg_inst="8"/> |
| <instance addr="0x2202440D" reg_inst="9"/> |
| <instance addr="0x2202240D" reg_inst="10"/> |
| <instance addr="0x2202140D" reg_inst="11"/> |
| <instance addr="0x2302840D" reg_inst="12"/> |
| <instance addr="0x2302440D" reg_inst="13"/> |
| <instance addr="0x2302240D" reg_inst="14"/> |
| <instance addr="0x2302140D" reg_inst="15"/> |
| <instance addr="0x2402840D" reg_inst="16"/> |
| <instance addr="0x2402440D" reg_inst="17"/> |
| <instance addr="0x2402240D" reg_inst="18"/> |
| <instance addr="0x2402140D" reg_inst="19"/> |
| <instance addr="0x2502840D" reg_inst="20"/> |
| <instance addr="0x2502440D" reg_inst="21"/> |
| <instance addr="0x2502240D" reg_inst="22"/> |
| <instance addr="0x2502140D" reg_inst="23"/> |
| <instance addr="0x2602840D" reg_inst="24"/> |
| <instance addr="0x2602440D" reg_inst="25"/> |
| <instance addr="0x2602240D" reg_inst="26"/> |
| <instance addr="0x2602140D" reg_inst="27"/> |
| <instance addr="0x2702840D" reg_inst="28"/> |
| <instance addr="0x2702440D" reg_inst="29"/> |
| <instance addr="0x2702240D" reg_inst="30"/> |
| <instance addr="0x2702140D" reg_inst="31"/> |
| </register> |
| <register name="PC_FIR_HOLD_OUT"> |
| <instance addr="0x20028451" reg_inst="0"/> |
| <instance addr="0x20024451" reg_inst="1"/> |
| <instance addr="0x20022451" reg_inst="2"/> |
| <instance addr="0x20021451" reg_inst="3"/> |
| <instance addr="0x21028451" reg_inst="4"/> |
| <instance addr="0x21024451" reg_inst="5"/> |
| <instance addr="0x21022451" reg_inst="6"/> |
| <instance addr="0x21021451" reg_inst="7"/> |
| <instance addr="0x22028451" reg_inst="8"/> |
| <instance addr="0x22024451" reg_inst="9"/> |
| <instance addr="0x22022451" reg_inst="10"/> |
| <instance addr="0x22021451" reg_inst="11"/> |
| <instance addr="0x23028451" reg_inst="12"/> |
| <instance addr="0x23024451" reg_inst="13"/> |
| <instance addr="0x23022451" reg_inst="14"/> |
| <instance addr="0x23021451" reg_inst="15"/> |
| <instance addr="0x24028451" reg_inst="16"/> |
| <instance addr="0x24024451" reg_inst="17"/> |
| <instance addr="0x24022451" reg_inst="18"/> |
| <instance addr="0x24021451" reg_inst="19"/> |
| <instance addr="0x25028451" reg_inst="20"/> |
| <instance addr="0x25024451" reg_inst="21"/> |
| <instance addr="0x25022451" reg_inst="22"/> |
| <instance addr="0x25021451" reg_inst="23"/> |
| <instance addr="0x26028451" reg_inst="24"/> |
| <instance addr="0x26024451" reg_inst="25"/> |
| <instance addr="0x26022451" reg_inst="26"/> |
| <instance addr="0x26021451" reg_inst="27"/> |
| <instance addr="0x27028451" reg_inst="28"/> |
| <instance addr="0x27024451" reg_inst="29"/> |
| <instance addr="0x27022451" reg_inst="30"/> |
| <instance addr="0x27021451" reg_inst="31"/> |
| </register> |
| <register name="THRCTL_HOLD_OUT"> |
| <instance addr="0x20028455" reg_inst="0"/> |
| <instance addr="0x20024455" reg_inst="1"/> |
| <instance addr="0x20022455" reg_inst="2"/> |
| <instance addr="0x20021455" reg_inst="3"/> |
| <instance addr="0x21028455" reg_inst="4"/> |
| <instance addr="0x21024455" reg_inst="5"/> |
| <instance addr="0x21022455" reg_inst="6"/> |
| <instance addr="0x21021455" reg_inst="7"/> |
| <instance addr="0x22028455" reg_inst="8"/> |
| <instance addr="0x22024455" reg_inst="9"/> |
| <instance addr="0x22022455" reg_inst="10"/> |
| <instance addr="0x22021455" reg_inst="11"/> |
| <instance addr="0x23028455" reg_inst="12"/> |
| <instance addr="0x23024455" reg_inst="13"/> |
| <instance addr="0x23022455" reg_inst="14"/> |
| <instance addr="0x23021455" reg_inst="15"/> |
| <instance addr="0x24028455" reg_inst="16"/> |
| <instance addr="0x24024455" reg_inst="17"/> |
| <instance addr="0x24022455" reg_inst="18"/> |
| <instance addr="0x24021455" reg_inst="19"/> |
| <instance addr="0x25028455" reg_inst="20"/> |
| <instance addr="0x25024455" reg_inst="21"/> |
| <instance addr="0x25022455" reg_inst="22"/> |
| <instance addr="0x25021455" reg_inst="23"/> |
| <instance addr="0x26028455" reg_inst="24"/> |
| <instance addr="0x26024455" reg_inst="25"/> |
| <instance addr="0x26022455" reg_inst="26"/> |
| <instance addr="0x26021455" reg_inst="27"/> |
| <instance addr="0x27028455" reg_inst="28"/> |
| <instance addr="0x27024455" reg_inst="29"/> |
| <instance addr="0x27022455" reg_inst="30"/> |
| <instance addr="0x27021455" reg_inst="31"/> |
| </register> |
| <register name="VSU_HOLD_OUT"> |
| <instance addr="0x200284B6" reg_inst="0"/> |
| <instance addr="0x200244B6" reg_inst="1"/> |
| <instance addr="0x200224B6" reg_inst="2"/> |
| <instance addr="0x200214B6" reg_inst="3"/> |
| <instance addr="0x210284B6" reg_inst="4"/> |
| <instance addr="0x210244B6" reg_inst="5"/> |
| <instance addr="0x210224B6" reg_inst="6"/> |
| <instance addr="0x210214B6" reg_inst="7"/> |
| <instance addr="0x220284B6" reg_inst="8"/> |
| <instance addr="0x220244B6" reg_inst="9"/> |
| <instance addr="0x220224B6" reg_inst="10"/> |
| <instance addr="0x220214B6" reg_inst="11"/> |
| <instance addr="0x230284B6" reg_inst="12"/> |
| <instance addr="0x230244B6" reg_inst="13"/> |
| <instance addr="0x230224B6" reg_inst="14"/> |
| <instance addr="0x230214B6" reg_inst="15"/> |
| <instance addr="0x240284B6" reg_inst="16"/> |
| <instance addr="0x240244B6" reg_inst="17"/> |
| <instance addr="0x240224B6" reg_inst="18"/> |
| <instance addr="0x240214B6" reg_inst="19"/> |
| <instance addr="0x250284B6" reg_inst="20"/> |
| <instance addr="0x250244B6" reg_inst="21"/> |
| <instance addr="0x250224B6" reg_inst="22"/> |
| <instance addr="0x250214B6" reg_inst="23"/> |
| <instance addr="0x260284B6" reg_inst="24"/> |
| <instance addr="0x260244B6" reg_inst="25"/> |
| <instance addr="0x260224B6" reg_inst="26"/> |
| <instance addr="0x260214B6" reg_inst="27"/> |
| <instance addr="0x270284B6" reg_inst="28"/> |
| <instance addr="0x270244B6" reg_inst="29"/> |
| <instance addr="0x270224B6" reg_inst="30"/> |
| <instance addr="0x270214B6" reg_inst="31"/> |
| </register> |
| <register name="TFAC_HOLD_OUT"> |
| <instance addr="0x200284B7" reg_inst="0"/> |
| <instance addr="0x200244B7" reg_inst="1"/> |
| <instance addr="0x200224B7" reg_inst="2"/> |
| <instance addr="0x200214B7" reg_inst="3"/> |
| <instance addr="0x210284B7" reg_inst="4"/> |
| <instance addr="0x210244B7" reg_inst="5"/> |
| <instance addr="0x210224B7" reg_inst="6"/> |
| <instance addr="0x210214B7" reg_inst="7"/> |
| <instance addr="0x220284B7" reg_inst="8"/> |
| <instance addr="0x220244B7" reg_inst="9"/> |
| <instance addr="0x220224B7" reg_inst="10"/> |
| <instance addr="0x220214B7" reg_inst="11"/> |
| <instance addr="0x230284B7" reg_inst="12"/> |
| <instance addr="0x230244B7" reg_inst="13"/> |
| <instance addr="0x230224B7" reg_inst="14"/> |
| <instance addr="0x230214B7" reg_inst="15"/> |
| <instance addr="0x240284B7" reg_inst="16"/> |
| <instance addr="0x240244B7" reg_inst="17"/> |
| <instance addr="0x240224B7" reg_inst="18"/> |
| <instance addr="0x240214B7" reg_inst="19"/> |
| <instance addr="0x250284B7" reg_inst="20"/> |
| <instance addr="0x250244B7" reg_inst="21"/> |
| <instance addr="0x250224B7" reg_inst="22"/> |
| <instance addr="0x250214B7" reg_inst="23"/> |
| <instance addr="0x260284B7" reg_inst="24"/> |
| <instance addr="0x260244B7" reg_inst="25"/> |
| <instance addr="0x260224B7" reg_inst="26"/> |
| <instance addr="0x260214B7" reg_inst="27"/> |
| <instance addr="0x270284B7" reg_inst="28"/> |
| <instance addr="0x270244B7" reg_inst="29"/> |
| <instance addr="0x270224B7" reg_inst="30"/> |
| <instance addr="0x270214B7" reg_inst="31"/> |
| </register> |
| <register name="IFU_HOLD_OUT0"> |
| <instance addr="0x20028600" reg_inst="0"/> |
| <instance addr="0x20024600" reg_inst="1"/> |
| <instance addr="0x20022600" reg_inst="2"/> |
| <instance addr="0x20021600" reg_inst="3"/> |
| <instance addr="0x21028600" reg_inst="4"/> |
| <instance addr="0x21024600" reg_inst="5"/> |
| <instance addr="0x21022600" reg_inst="6"/> |
| <instance addr="0x21021600" reg_inst="7"/> |
| <instance addr="0x22028600" reg_inst="8"/> |
| <instance addr="0x22024600" reg_inst="9"/> |
| <instance addr="0x22022600" reg_inst="10"/> |
| <instance addr="0x22021600" reg_inst="11"/> |
| <instance addr="0x23028600" reg_inst="12"/> |
| <instance addr="0x23024600" reg_inst="13"/> |
| <instance addr="0x23022600" reg_inst="14"/> |
| <instance addr="0x23021600" reg_inst="15"/> |
| <instance addr="0x24028600" reg_inst="16"/> |
| <instance addr="0x24024600" reg_inst="17"/> |
| <instance addr="0x24022600" reg_inst="18"/> |
| <instance addr="0x24021600" reg_inst="19"/> |
| <instance addr="0x25028600" reg_inst="20"/> |
| <instance addr="0x25024600" reg_inst="21"/> |
| <instance addr="0x25022600" reg_inst="22"/> |
| <instance addr="0x25021600" reg_inst="23"/> |
| <instance addr="0x26028600" reg_inst="24"/> |
| <instance addr="0x26024600" reg_inst="25"/> |
| <instance addr="0x26022600" reg_inst="26"/> |
| <instance addr="0x26021600" reg_inst="27"/> |
| <instance addr="0x27028600" reg_inst="28"/> |
| <instance addr="0x27024600" reg_inst="29"/> |
| <instance addr="0x27022600" reg_inst="30"/> |
| <instance addr="0x27021600" reg_inst="31"/> |
| </register> |
| <register name="IFU_HOLD_OUT1"> |
| <instance addr="0x20028601" reg_inst="0"/> |
| <instance addr="0x20024601" reg_inst="1"/> |
| <instance addr="0x20022601" reg_inst="2"/> |
| <instance addr="0x20021601" reg_inst="3"/> |
| <instance addr="0x21028601" reg_inst="4"/> |
| <instance addr="0x21024601" reg_inst="5"/> |
| <instance addr="0x21022601" reg_inst="6"/> |
| <instance addr="0x21021601" reg_inst="7"/> |
| <instance addr="0x22028601" reg_inst="8"/> |
| <instance addr="0x22024601" reg_inst="9"/> |
| <instance addr="0x22022601" reg_inst="10"/> |
| <instance addr="0x22021601" reg_inst="11"/> |
| <instance addr="0x23028601" reg_inst="12"/> |
| <instance addr="0x23024601" reg_inst="13"/> |
| <instance addr="0x23022601" reg_inst="14"/> |
| <instance addr="0x23021601" reg_inst="15"/> |
| <instance addr="0x24028601" reg_inst="16"/> |
| <instance addr="0x24024601" reg_inst="17"/> |
| <instance addr="0x24022601" reg_inst="18"/> |
| <instance addr="0x24021601" reg_inst="19"/> |
| <instance addr="0x25028601" reg_inst="20"/> |
| <instance addr="0x25024601" reg_inst="21"/> |
| <instance addr="0x25022601" reg_inst="22"/> |
| <instance addr="0x25021601" reg_inst="23"/> |
| <instance addr="0x26028601" reg_inst="24"/> |
| <instance addr="0x26024601" reg_inst="25"/> |
| <instance addr="0x26022601" reg_inst="26"/> |
| <instance addr="0x26021601" reg_inst="27"/> |
| <instance addr="0x27028601" reg_inst="28"/> |
| <instance addr="0x27024601" reg_inst="29"/> |
| <instance addr="0x27022601" reg_inst="30"/> |
| <instance addr="0x27021601" reg_inst="31"/> |
| </register> |
| <register name="IFU_HOLD_OUT2"> |
| <instance addr="0x20028602" reg_inst="0"/> |
| <instance addr="0x20024602" reg_inst="1"/> |
| <instance addr="0x20022602" reg_inst="2"/> |
| <instance addr="0x20021602" reg_inst="3"/> |
| <instance addr="0x21028602" reg_inst="4"/> |
| <instance addr="0x21024602" reg_inst="5"/> |
| <instance addr="0x21022602" reg_inst="6"/> |
| <instance addr="0x21021602" reg_inst="7"/> |
| <instance addr="0x22028602" reg_inst="8"/> |
| <instance addr="0x22024602" reg_inst="9"/> |
| <instance addr="0x22022602" reg_inst="10"/> |
| <instance addr="0x22021602" reg_inst="11"/> |
| <instance addr="0x23028602" reg_inst="12"/> |
| <instance addr="0x23024602" reg_inst="13"/> |
| <instance addr="0x23022602" reg_inst="14"/> |
| <instance addr="0x23021602" reg_inst="15"/> |
| <instance addr="0x24028602" reg_inst="16"/> |
| <instance addr="0x24024602" reg_inst="17"/> |
| <instance addr="0x24022602" reg_inst="18"/> |
| <instance addr="0x24021602" reg_inst="19"/> |
| <instance addr="0x25028602" reg_inst="20"/> |
| <instance addr="0x25024602" reg_inst="21"/> |
| <instance addr="0x25022602" reg_inst="22"/> |
| <instance addr="0x25021602" reg_inst="23"/> |
| <instance addr="0x26028602" reg_inst="24"/> |
| <instance addr="0x26024602" reg_inst="25"/> |
| <instance addr="0x26022602" reg_inst="26"/> |
| <instance addr="0x26021602" reg_inst="27"/> |
| <instance addr="0x27028602" reg_inst="28"/> |
| <instance addr="0x27024602" reg_inst="29"/> |
| <instance addr="0x27022602" reg_inst="30"/> |
| <instance addr="0x27021602" reg_inst="31"/> |
| </register> |
| <register name="IFU_HOLD_OUT3"> |
| <instance addr="0x20028603" reg_inst="0"/> |
| <instance addr="0x20024603" reg_inst="1"/> |
| <instance addr="0x20022603" reg_inst="2"/> |
| <instance addr="0x20021603" reg_inst="3"/> |
| <instance addr="0x21028603" reg_inst="4"/> |
| <instance addr="0x21024603" reg_inst="5"/> |
| <instance addr="0x21022603" reg_inst="6"/> |
| <instance addr="0x21021603" reg_inst="7"/> |
| <instance addr="0x22028603" reg_inst="8"/> |
| <instance addr="0x22024603" reg_inst="9"/> |
| <instance addr="0x22022603" reg_inst="10"/> |
| <instance addr="0x22021603" reg_inst="11"/> |
| <instance addr="0x23028603" reg_inst="12"/> |
| <instance addr="0x23024603" reg_inst="13"/> |
| <instance addr="0x23022603" reg_inst="14"/> |
| <instance addr="0x23021603" reg_inst="15"/> |
| <instance addr="0x24028603" reg_inst="16"/> |
| <instance addr="0x24024603" reg_inst="17"/> |
| <instance addr="0x24022603" reg_inst="18"/> |
| <instance addr="0x24021603" reg_inst="19"/> |
| <instance addr="0x25028603" reg_inst="20"/> |
| <instance addr="0x25024603" reg_inst="21"/> |
| <instance addr="0x25022603" reg_inst="22"/> |
| <instance addr="0x25021603" reg_inst="23"/> |
| <instance addr="0x26028603" reg_inst="24"/> |
| <instance addr="0x26024603" reg_inst="25"/> |
| <instance addr="0x26022603" reg_inst="26"/> |
| <instance addr="0x26021603" reg_inst="27"/> |
| <instance addr="0x27028603" reg_inst="28"/> |
| <instance addr="0x27024603" reg_inst="29"/> |
| <instance addr="0x27022603" reg_inst="30"/> |
| <instance addr="0x27021603" reg_inst="31"/> |
| </register> |
| <register name="ISU_HOLD_OUT0"> |
| <instance addr="0x20028640" reg_inst="0"/> |
| <instance addr="0x20024640" reg_inst="1"/> |
| <instance addr="0x20022640" reg_inst="2"/> |
| <instance addr="0x20021640" reg_inst="3"/> |
| <instance addr="0x21028640" reg_inst="4"/> |
| <instance addr="0x21024640" reg_inst="5"/> |
| <instance addr="0x21022640" reg_inst="6"/> |
| <instance addr="0x21021640" reg_inst="7"/> |
| <instance addr="0x22028640" reg_inst="8"/> |
| <instance addr="0x22024640" reg_inst="9"/> |
| <instance addr="0x22022640" reg_inst="10"/> |
| <instance addr="0x22021640" reg_inst="11"/> |
| <instance addr="0x23028640" reg_inst="12"/> |
| <instance addr="0x23024640" reg_inst="13"/> |
| <instance addr="0x23022640" reg_inst="14"/> |
| <instance addr="0x23021640" reg_inst="15"/> |
| <instance addr="0x24028640" reg_inst="16"/> |
| <instance addr="0x24024640" reg_inst="17"/> |
| <instance addr="0x24022640" reg_inst="18"/> |
| <instance addr="0x24021640" reg_inst="19"/> |
| <instance addr="0x25028640" reg_inst="20"/> |
| <instance addr="0x25024640" reg_inst="21"/> |
| <instance addr="0x25022640" reg_inst="22"/> |
| <instance addr="0x25021640" reg_inst="23"/> |
| <instance addr="0x26028640" reg_inst="24"/> |
| <instance addr="0x26024640" reg_inst="25"/> |
| <instance addr="0x26022640" reg_inst="26"/> |
| <instance addr="0x26021640" reg_inst="27"/> |
| <instance addr="0x27028640" reg_inst="28"/> |
| <instance addr="0x27024640" reg_inst="29"/> |
| <instance addr="0x27022640" reg_inst="30"/> |
| <instance addr="0x27021640" reg_inst="31"/> |
| </register> |
| <register name="ISU_HOLD_OUT1"> |
| <instance addr="0x20028641" reg_inst="0"/> |
| <instance addr="0x20024641" reg_inst="1"/> |
| <instance addr="0x20022641" reg_inst="2"/> |
| <instance addr="0x20021641" reg_inst="3"/> |
| <instance addr="0x21028641" reg_inst="4"/> |
| <instance addr="0x21024641" reg_inst="5"/> |
| <instance addr="0x21022641" reg_inst="6"/> |
| <instance addr="0x21021641" reg_inst="7"/> |
| <instance addr="0x22028641" reg_inst="8"/> |
| <instance addr="0x22024641" reg_inst="9"/> |
| <instance addr="0x22022641" reg_inst="10"/> |
| <instance addr="0x22021641" reg_inst="11"/> |
| <instance addr="0x23028641" reg_inst="12"/> |
| <instance addr="0x23024641" reg_inst="13"/> |
| <instance addr="0x23022641" reg_inst="14"/> |
| <instance addr="0x23021641" reg_inst="15"/> |
| <instance addr="0x24028641" reg_inst="16"/> |
| <instance addr="0x24024641" reg_inst="17"/> |
| <instance addr="0x24022641" reg_inst="18"/> |
| <instance addr="0x24021641" reg_inst="19"/> |
| <instance addr="0x25028641" reg_inst="20"/> |
| <instance addr="0x25024641" reg_inst="21"/> |
| <instance addr="0x25022641" reg_inst="22"/> |
| <instance addr="0x25021641" reg_inst="23"/> |
| <instance addr="0x26028641" reg_inst="24"/> |
| <instance addr="0x26024641" reg_inst="25"/> |
| <instance addr="0x26022641" reg_inst="26"/> |
| <instance addr="0x26021641" reg_inst="27"/> |
| <instance addr="0x27028641" reg_inst="28"/> |
| <instance addr="0x27024641" reg_inst="29"/> |
| <instance addr="0x27022641" reg_inst="30"/> |
| <instance addr="0x27021641" reg_inst="31"/> |
| </register> |
| <register name="ISU_HOLD_OUT2"> |
| <instance addr="0x20028642" reg_inst="0"/> |
| <instance addr="0x20024642" reg_inst="1"/> |
| <instance addr="0x20022642" reg_inst="2"/> |
| <instance addr="0x20021642" reg_inst="3"/> |
| <instance addr="0x21028642" reg_inst="4"/> |
| <instance addr="0x21024642" reg_inst="5"/> |
| <instance addr="0x21022642" reg_inst="6"/> |
| <instance addr="0x21021642" reg_inst="7"/> |
| <instance addr="0x22028642" reg_inst="8"/> |
| <instance addr="0x22024642" reg_inst="9"/> |
| <instance addr="0x22022642" reg_inst="10"/> |
| <instance addr="0x22021642" reg_inst="11"/> |
| <instance addr="0x23028642" reg_inst="12"/> |
| <instance addr="0x23024642" reg_inst="13"/> |
| <instance addr="0x23022642" reg_inst="14"/> |
| <instance addr="0x23021642" reg_inst="15"/> |
| <instance addr="0x24028642" reg_inst="16"/> |
| <instance addr="0x24024642" reg_inst="17"/> |
| <instance addr="0x24022642" reg_inst="18"/> |
| <instance addr="0x24021642" reg_inst="19"/> |
| <instance addr="0x25028642" reg_inst="20"/> |
| <instance addr="0x25024642" reg_inst="21"/> |
| <instance addr="0x25022642" reg_inst="22"/> |
| <instance addr="0x25021642" reg_inst="23"/> |
| <instance addr="0x26028642" reg_inst="24"/> |
| <instance addr="0x26024642" reg_inst="25"/> |
| <instance addr="0x26022642" reg_inst="26"/> |
| <instance addr="0x26021642" reg_inst="27"/> |
| <instance addr="0x27028642" reg_inst="28"/> |
| <instance addr="0x27024642" reg_inst="29"/> |
| <instance addr="0x27022642" reg_inst="30"/> |
| <instance addr="0x27021642" reg_inst="31"/> |
| </register> |
| <register name="ISU_HOLD_OUT3"> |
| <instance addr="0x20028643" reg_inst="0"/> |
| <instance addr="0x20024643" reg_inst="1"/> |
| <instance addr="0x20022643" reg_inst="2"/> |
| <instance addr="0x20021643" reg_inst="3"/> |
| <instance addr="0x21028643" reg_inst="4"/> |
| <instance addr="0x21024643" reg_inst="5"/> |
| <instance addr="0x21022643" reg_inst="6"/> |
| <instance addr="0x21021643" reg_inst="7"/> |
| <instance addr="0x22028643" reg_inst="8"/> |
| <instance addr="0x22024643" reg_inst="9"/> |
| <instance addr="0x22022643" reg_inst="10"/> |
| <instance addr="0x22021643" reg_inst="11"/> |
| <instance addr="0x23028643" reg_inst="12"/> |
| <instance addr="0x23024643" reg_inst="13"/> |
| <instance addr="0x23022643" reg_inst="14"/> |
| <instance addr="0x23021643" reg_inst="15"/> |
| <instance addr="0x24028643" reg_inst="16"/> |
| <instance addr="0x24024643" reg_inst="17"/> |
| <instance addr="0x24022643" reg_inst="18"/> |
| <instance addr="0x24021643" reg_inst="19"/> |
| <instance addr="0x25028643" reg_inst="20"/> |
| <instance addr="0x25024643" reg_inst="21"/> |
| <instance addr="0x25022643" reg_inst="22"/> |
| <instance addr="0x25021643" reg_inst="23"/> |
| <instance addr="0x26028643" reg_inst="24"/> |
| <instance addr="0x26024643" reg_inst="25"/> |
| <instance addr="0x26022643" reg_inst="26"/> |
| <instance addr="0x26021643" reg_inst="27"/> |
| <instance addr="0x27028643" reg_inst="28"/> |
| <instance addr="0x27024643" reg_inst="29"/> |
| <instance addr="0x27022643" reg_inst="30"/> |
| <instance addr="0x27021643" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT0"> |
| <instance addr="0x20028680" reg_inst="0"/> |
| <instance addr="0x20024680" reg_inst="1"/> |
| <instance addr="0x20022680" reg_inst="2"/> |
| <instance addr="0x20021680" reg_inst="3"/> |
| <instance addr="0x21028680" reg_inst="4"/> |
| <instance addr="0x21024680" reg_inst="5"/> |
| <instance addr="0x21022680" reg_inst="6"/> |
| <instance addr="0x21021680" reg_inst="7"/> |
| <instance addr="0x22028680" reg_inst="8"/> |
| <instance addr="0x22024680" reg_inst="9"/> |
| <instance addr="0x22022680" reg_inst="10"/> |
| <instance addr="0x22021680" reg_inst="11"/> |
| <instance addr="0x23028680" reg_inst="12"/> |
| <instance addr="0x23024680" reg_inst="13"/> |
| <instance addr="0x23022680" reg_inst="14"/> |
| <instance addr="0x23021680" reg_inst="15"/> |
| <instance addr="0x24028680" reg_inst="16"/> |
| <instance addr="0x24024680" reg_inst="17"/> |
| <instance addr="0x24022680" reg_inst="18"/> |
| <instance addr="0x24021680" reg_inst="19"/> |
| <instance addr="0x25028680" reg_inst="20"/> |
| <instance addr="0x25024680" reg_inst="21"/> |
| <instance addr="0x25022680" reg_inst="22"/> |
| <instance addr="0x25021680" reg_inst="23"/> |
| <instance addr="0x26028680" reg_inst="24"/> |
| <instance addr="0x26024680" reg_inst="25"/> |
| <instance addr="0x26022680" reg_inst="26"/> |
| <instance addr="0x26021680" reg_inst="27"/> |
| <instance addr="0x27028680" reg_inst="28"/> |
| <instance addr="0x27024680" reg_inst="29"/> |
| <instance addr="0x27022680" reg_inst="30"/> |
| <instance addr="0x27021680" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT1"> |
| <instance addr="0x20028681" reg_inst="0"/> |
| <instance addr="0x20024681" reg_inst="1"/> |
| <instance addr="0x20022681" reg_inst="2"/> |
| <instance addr="0x20021681" reg_inst="3"/> |
| <instance addr="0x21028681" reg_inst="4"/> |
| <instance addr="0x21024681" reg_inst="5"/> |
| <instance addr="0x21022681" reg_inst="6"/> |
| <instance addr="0x21021681" reg_inst="7"/> |
| <instance addr="0x22028681" reg_inst="8"/> |
| <instance addr="0x22024681" reg_inst="9"/> |
| <instance addr="0x22022681" reg_inst="10"/> |
| <instance addr="0x22021681" reg_inst="11"/> |
| <instance addr="0x23028681" reg_inst="12"/> |
| <instance addr="0x23024681" reg_inst="13"/> |
| <instance addr="0x23022681" reg_inst="14"/> |
| <instance addr="0x23021681" reg_inst="15"/> |
| <instance addr="0x24028681" reg_inst="16"/> |
| <instance addr="0x24024681" reg_inst="17"/> |
| <instance addr="0x24022681" reg_inst="18"/> |
| <instance addr="0x24021681" reg_inst="19"/> |
| <instance addr="0x25028681" reg_inst="20"/> |
| <instance addr="0x25024681" reg_inst="21"/> |
| <instance addr="0x25022681" reg_inst="22"/> |
| <instance addr="0x25021681" reg_inst="23"/> |
| <instance addr="0x26028681" reg_inst="24"/> |
| <instance addr="0x26024681" reg_inst="25"/> |
| <instance addr="0x26022681" reg_inst="26"/> |
| <instance addr="0x26021681" reg_inst="27"/> |
| <instance addr="0x27028681" reg_inst="28"/> |
| <instance addr="0x27024681" reg_inst="29"/> |
| <instance addr="0x27022681" reg_inst="30"/> |
| <instance addr="0x27021681" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT2"> |
| <instance addr="0x20028682" reg_inst="0"/> |
| <instance addr="0x20024682" reg_inst="1"/> |
| <instance addr="0x20022682" reg_inst="2"/> |
| <instance addr="0x20021682" reg_inst="3"/> |
| <instance addr="0x21028682" reg_inst="4"/> |
| <instance addr="0x21024682" reg_inst="5"/> |
| <instance addr="0x21022682" reg_inst="6"/> |
| <instance addr="0x21021682" reg_inst="7"/> |
| <instance addr="0x22028682" reg_inst="8"/> |
| <instance addr="0x22024682" reg_inst="9"/> |
| <instance addr="0x22022682" reg_inst="10"/> |
| <instance addr="0x22021682" reg_inst="11"/> |
| <instance addr="0x23028682" reg_inst="12"/> |
| <instance addr="0x23024682" reg_inst="13"/> |
| <instance addr="0x23022682" reg_inst="14"/> |
| <instance addr="0x23021682" reg_inst="15"/> |
| <instance addr="0x24028682" reg_inst="16"/> |
| <instance addr="0x24024682" reg_inst="17"/> |
| <instance addr="0x24022682" reg_inst="18"/> |
| <instance addr="0x24021682" reg_inst="19"/> |
| <instance addr="0x25028682" reg_inst="20"/> |
| <instance addr="0x25024682" reg_inst="21"/> |
| <instance addr="0x25022682" reg_inst="22"/> |
| <instance addr="0x25021682" reg_inst="23"/> |
| <instance addr="0x26028682" reg_inst="24"/> |
| <instance addr="0x26024682" reg_inst="25"/> |
| <instance addr="0x26022682" reg_inst="26"/> |
| <instance addr="0x26021682" reg_inst="27"/> |
| <instance addr="0x27028682" reg_inst="28"/> |
| <instance addr="0x27024682" reg_inst="29"/> |
| <instance addr="0x27022682" reg_inst="30"/> |
| <instance addr="0x27021682" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT3"> |
| <instance addr="0x20028683" reg_inst="0"/> |
| <instance addr="0x20024683" reg_inst="1"/> |
| <instance addr="0x20022683" reg_inst="2"/> |
| <instance addr="0x20021683" reg_inst="3"/> |
| <instance addr="0x21028683" reg_inst="4"/> |
| <instance addr="0x21024683" reg_inst="5"/> |
| <instance addr="0x21022683" reg_inst="6"/> |
| <instance addr="0x21021683" reg_inst="7"/> |
| <instance addr="0x22028683" reg_inst="8"/> |
| <instance addr="0x22024683" reg_inst="9"/> |
| <instance addr="0x22022683" reg_inst="10"/> |
| <instance addr="0x22021683" reg_inst="11"/> |
| <instance addr="0x23028683" reg_inst="12"/> |
| <instance addr="0x23024683" reg_inst="13"/> |
| <instance addr="0x23022683" reg_inst="14"/> |
| <instance addr="0x23021683" reg_inst="15"/> |
| <instance addr="0x24028683" reg_inst="16"/> |
| <instance addr="0x24024683" reg_inst="17"/> |
| <instance addr="0x24022683" reg_inst="18"/> |
| <instance addr="0x24021683" reg_inst="19"/> |
| <instance addr="0x25028683" reg_inst="20"/> |
| <instance addr="0x25024683" reg_inst="21"/> |
| <instance addr="0x25022683" reg_inst="22"/> |
| <instance addr="0x25021683" reg_inst="23"/> |
| <instance addr="0x26028683" reg_inst="24"/> |
| <instance addr="0x26024683" reg_inst="25"/> |
| <instance addr="0x26022683" reg_inst="26"/> |
| <instance addr="0x26021683" reg_inst="27"/> |
| <instance addr="0x27028683" reg_inst="28"/> |
| <instance addr="0x27024683" reg_inst="29"/> |
| <instance addr="0x27022683" reg_inst="30"/> |
| <instance addr="0x27021683" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT4"> |
| <instance addr="0x20028684" reg_inst="0"/> |
| <instance addr="0x20024684" reg_inst="1"/> |
| <instance addr="0x20022684" reg_inst="2"/> |
| <instance addr="0x20021684" reg_inst="3"/> |
| <instance addr="0x21028684" reg_inst="4"/> |
| <instance addr="0x21024684" reg_inst="5"/> |
| <instance addr="0x21022684" reg_inst="6"/> |
| <instance addr="0x21021684" reg_inst="7"/> |
| <instance addr="0x22028684" reg_inst="8"/> |
| <instance addr="0x22024684" reg_inst="9"/> |
| <instance addr="0x22022684" reg_inst="10"/> |
| <instance addr="0x22021684" reg_inst="11"/> |
| <instance addr="0x23028684" reg_inst="12"/> |
| <instance addr="0x23024684" reg_inst="13"/> |
| <instance addr="0x23022684" reg_inst="14"/> |
| <instance addr="0x23021684" reg_inst="15"/> |
| <instance addr="0x24028684" reg_inst="16"/> |
| <instance addr="0x24024684" reg_inst="17"/> |
| <instance addr="0x24022684" reg_inst="18"/> |
| <instance addr="0x24021684" reg_inst="19"/> |
| <instance addr="0x25028684" reg_inst="20"/> |
| <instance addr="0x25024684" reg_inst="21"/> |
| <instance addr="0x25022684" reg_inst="22"/> |
| <instance addr="0x25021684" reg_inst="23"/> |
| <instance addr="0x26028684" reg_inst="24"/> |
| <instance addr="0x26024684" reg_inst="25"/> |
| <instance addr="0x26022684" reg_inst="26"/> |
| <instance addr="0x26021684" reg_inst="27"/> |
| <instance addr="0x27028684" reg_inst="28"/> |
| <instance addr="0x27024684" reg_inst="29"/> |
| <instance addr="0x27022684" reg_inst="30"/> |
| <instance addr="0x27021684" reg_inst="31"/> |
| </register> |
| <register name="MMU_HOLD_OUT5"> |
| <instance addr="0x20028685" reg_inst="0"/> |
| <instance addr="0x20024685" reg_inst="1"/> |
| <instance addr="0x20022685" reg_inst="2"/> |
| <instance addr="0x20021685" reg_inst="3"/> |
| <instance addr="0x21028685" reg_inst="4"/> |
| <instance addr="0x21024685" reg_inst="5"/> |
| <instance addr="0x21022685" reg_inst="6"/> |
| <instance addr="0x21021685" reg_inst="7"/> |
| <instance addr="0x22028685" reg_inst="8"/> |
| <instance addr="0x22024685" reg_inst="9"/> |
| <instance addr="0x22022685" reg_inst="10"/> |
| <instance addr="0x22021685" reg_inst="11"/> |
| <instance addr="0x23028685" reg_inst="12"/> |
| <instance addr="0x23024685" reg_inst="13"/> |
| <instance addr="0x23022685" reg_inst="14"/> |
| <instance addr="0x23021685" reg_inst="15"/> |
| <instance addr="0x24028685" reg_inst="16"/> |
| <instance addr="0x24024685" reg_inst="17"/> |
| <instance addr="0x24022685" reg_inst="18"/> |
| <instance addr="0x24021685" reg_inst="19"/> |
| <instance addr="0x25028685" reg_inst="20"/> |
| <instance addr="0x25024685" reg_inst="21"/> |
| <instance addr="0x25022685" reg_inst="22"/> |
| <instance addr="0x25021685" reg_inst="23"/> |
| <instance addr="0x26028685" reg_inst="24"/> |
| <instance addr="0x26024685" reg_inst="25"/> |
| <instance addr="0x26022685" reg_inst="26"/> |
| <instance addr="0x26021685" reg_inst="27"/> |
| <instance addr="0x27028685" reg_inst="28"/> |
| <instance addr="0x27024685" reg_inst="29"/> |
| <instance addr="0x27022685" reg_inst="30"/> |
| <instance addr="0x27021685" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG0"> |
| <instance addr="0x200286C0" reg_inst="0"/> |
| <instance addr="0x200246C0" reg_inst="1"/> |
| <instance addr="0x200226C0" reg_inst="2"/> |
| <instance addr="0x200216C0" reg_inst="3"/> |
| <instance addr="0x210286C0" reg_inst="4"/> |
| <instance addr="0x210246C0" reg_inst="5"/> |
| <instance addr="0x210226C0" reg_inst="6"/> |
| <instance addr="0x210216C0" reg_inst="7"/> |
| <instance addr="0x220286C0" reg_inst="8"/> |
| <instance addr="0x220246C0" reg_inst="9"/> |
| <instance addr="0x220226C0" reg_inst="10"/> |
| <instance addr="0x220216C0" reg_inst="11"/> |
| <instance addr="0x230286C0" reg_inst="12"/> |
| <instance addr="0x230246C0" reg_inst="13"/> |
| <instance addr="0x230226C0" reg_inst="14"/> |
| <instance addr="0x230216C0" reg_inst="15"/> |
| <instance addr="0x240286C0" reg_inst="16"/> |
| <instance addr="0x240246C0" reg_inst="17"/> |
| <instance addr="0x240226C0" reg_inst="18"/> |
| <instance addr="0x240216C0" reg_inst="19"/> |
| <instance addr="0x250286C0" reg_inst="20"/> |
| <instance addr="0x250246C0" reg_inst="21"/> |
| <instance addr="0x250226C0" reg_inst="22"/> |
| <instance addr="0x250216C0" reg_inst="23"/> |
| <instance addr="0x260286C0" reg_inst="24"/> |
| <instance addr="0x260246C0" reg_inst="25"/> |
| <instance addr="0x260226C0" reg_inst="26"/> |
| <instance addr="0x260216C0" reg_inst="27"/> |
| <instance addr="0x270286C0" reg_inst="28"/> |
| <instance addr="0x270246C0" reg_inst="29"/> |
| <instance addr="0x270226C0" reg_inst="30"/> |
| <instance addr="0x270216C0" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG1"> |
| <instance addr="0x200286C1" reg_inst="0"/> |
| <instance addr="0x200246C1" reg_inst="1"/> |
| <instance addr="0x200226C1" reg_inst="2"/> |
| <instance addr="0x200216C1" reg_inst="3"/> |
| <instance addr="0x210286C1" reg_inst="4"/> |
| <instance addr="0x210246C1" reg_inst="5"/> |
| <instance addr="0x210226C1" reg_inst="6"/> |
| <instance addr="0x210216C1" reg_inst="7"/> |
| <instance addr="0x220286C1" reg_inst="8"/> |
| <instance addr="0x220246C1" reg_inst="9"/> |
| <instance addr="0x220226C1" reg_inst="10"/> |
| <instance addr="0x220216C1" reg_inst="11"/> |
| <instance addr="0x230286C1" reg_inst="12"/> |
| <instance addr="0x230246C1" reg_inst="13"/> |
| <instance addr="0x230226C1" reg_inst="14"/> |
| <instance addr="0x230216C1" reg_inst="15"/> |
| <instance addr="0x240286C1" reg_inst="16"/> |
| <instance addr="0x240246C1" reg_inst="17"/> |
| <instance addr="0x240226C1" reg_inst="18"/> |
| <instance addr="0x240216C1" reg_inst="19"/> |
| <instance addr="0x250286C1" reg_inst="20"/> |
| <instance addr="0x250246C1" reg_inst="21"/> |
| <instance addr="0x250226C1" reg_inst="22"/> |
| <instance addr="0x250216C1" reg_inst="23"/> |
| <instance addr="0x260286C1" reg_inst="24"/> |
| <instance addr="0x260246C1" reg_inst="25"/> |
| <instance addr="0x260226C1" reg_inst="26"/> |
| <instance addr="0x260216C1" reg_inst="27"/> |
| <instance addr="0x270286C1" reg_inst="28"/> |
| <instance addr="0x270246C1" reg_inst="29"/> |
| <instance addr="0x270226C1" reg_inst="30"/> |
| <instance addr="0x270216C1" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG2"> |
| <instance addr="0x200286C2" reg_inst="0"/> |
| <instance addr="0x200246C2" reg_inst="1"/> |
| <instance addr="0x200226C2" reg_inst="2"/> |
| <instance addr="0x200216C2" reg_inst="3"/> |
| <instance addr="0x210286C2" reg_inst="4"/> |
| <instance addr="0x210246C2" reg_inst="5"/> |
| <instance addr="0x210226C2" reg_inst="6"/> |
| <instance addr="0x210216C2" reg_inst="7"/> |
| <instance addr="0x220286C2" reg_inst="8"/> |
| <instance addr="0x220246C2" reg_inst="9"/> |
| <instance addr="0x220226C2" reg_inst="10"/> |
| <instance addr="0x220216C2" reg_inst="11"/> |
| <instance addr="0x230286C2" reg_inst="12"/> |
| <instance addr="0x230246C2" reg_inst="13"/> |
| <instance addr="0x230226C2" reg_inst="14"/> |
| <instance addr="0x230216C2" reg_inst="15"/> |
| <instance addr="0x240286C2" reg_inst="16"/> |
| <instance addr="0x240246C2" reg_inst="17"/> |
| <instance addr="0x240226C2" reg_inst="18"/> |
| <instance addr="0x240216C2" reg_inst="19"/> |
| <instance addr="0x250286C2" reg_inst="20"/> |
| <instance addr="0x250246C2" reg_inst="21"/> |
| <instance addr="0x250226C2" reg_inst="22"/> |
| <instance addr="0x250216C2" reg_inst="23"/> |
| <instance addr="0x260286C2" reg_inst="24"/> |
| <instance addr="0x260246C2" reg_inst="25"/> |
| <instance addr="0x260226C2" reg_inst="26"/> |
| <instance addr="0x260216C2" reg_inst="27"/> |
| <instance addr="0x270286C2" reg_inst="28"/> |
| <instance addr="0x270246C2" reg_inst="29"/> |
| <instance addr="0x270226C2" reg_inst="30"/> |
| <instance addr="0x270216C2" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG3"> |
| <instance addr="0x200286C3" reg_inst="0"/> |
| <instance addr="0x200246C3" reg_inst="1"/> |
| <instance addr="0x200226C3" reg_inst="2"/> |
| <instance addr="0x200216C3" reg_inst="3"/> |
| <instance addr="0x210286C3" reg_inst="4"/> |
| <instance addr="0x210246C3" reg_inst="5"/> |
| <instance addr="0x210226C3" reg_inst="6"/> |
| <instance addr="0x210216C3" reg_inst="7"/> |
| <instance addr="0x220286C3" reg_inst="8"/> |
| <instance addr="0x220246C3" reg_inst="9"/> |
| <instance addr="0x220226C3" reg_inst="10"/> |
| <instance addr="0x220216C3" reg_inst="11"/> |
| <instance addr="0x230286C3" reg_inst="12"/> |
| <instance addr="0x230246C3" reg_inst="13"/> |
| <instance addr="0x230226C3" reg_inst="14"/> |
| <instance addr="0x230216C3" reg_inst="15"/> |
| <instance addr="0x240286C3" reg_inst="16"/> |
| <instance addr="0x240246C3" reg_inst="17"/> |
| <instance addr="0x240226C3" reg_inst="18"/> |
| <instance addr="0x240216C3" reg_inst="19"/> |
| <instance addr="0x250286C3" reg_inst="20"/> |
| <instance addr="0x250246C3" reg_inst="21"/> |
| <instance addr="0x250226C3" reg_inst="22"/> |
| <instance addr="0x250216C3" reg_inst="23"/> |
| <instance addr="0x260286C3" reg_inst="24"/> |
| <instance addr="0x260246C3" reg_inst="25"/> |
| <instance addr="0x260226C3" reg_inst="26"/> |
| <instance addr="0x260216C3" reg_inst="27"/> |
| <instance addr="0x270286C3" reg_inst="28"/> |
| <instance addr="0x270246C3" reg_inst="29"/> |
| <instance addr="0x270226C3" reg_inst="30"/> |
| <instance addr="0x270216C3" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG4"> |
| <instance addr="0x200286C4" reg_inst="0"/> |
| <instance addr="0x200246C4" reg_inst="1"/> |
| <instance addr="0x200226C4" reg_inst="2"/> |
| <instance addr="0x200216C4" reg_inst="3"/> |
| <instance addr="0x210286C4" reg_inst="4"/> |
| <instance addr="0x210246C4" reg_inst="5"/> |
| <instance addr="0x210226C4" reg_inst="6"/> |
| <instance addr="0x210216C4" reg_inst="7"/> |
| <instance addr="0x220286C4" reg_inst="8"/> |
| <instance addr="0x220246C4" reg_inst="9"/> |
| <instance addr="0x220226C4" reg_inst="10"/> |
| <instance addr="0x220216C4" reg_inst="11"/> |
| <instance addr="0x230286C4" reg_inst="12"/> |
| <instance addr="0x230246C4" reg_inst="13"/> |
| <instance addr="0x230226C4" reg_inst="14"/> |
| <instance addr="0x230216C4" reg_inst="15"/> |
| <instance addr="0x240286C4" reg_inst="16"/> |
| <instance addr="0x240246C4" reg_inst="17"/> |
| <instance addr="0x240226C4" reg_inst="18"/> |
| <instance addr="0x240216C4" reg_inst="19"/> |
| <instance addr="0x250286C4" reg_inst="20"/> |
| <instance addr="0x250246C4" reg_inst="21"/> |
| <instance addr="0x250226C4" reg_inst="22"/> |
| <instance addr="0x250216C4" reg_inst="23"/> |
| <instance addr="0x260286C4" reg_inst="24"/> |
| <instance addr="0x260246C4" reg_inst="25"/> |
| <instance addr="0x260226C4" reg_inst="26"/> |
| <instance addr="0x260216C4" reg_inst="27"/> |
| <instance addr="0x270286C4" reg_inst="28"/> |
| <instance addr="0x270246C4" reg_inst="29"/> |
| <instance addr="0x270226C4" reg_inst="30"/> |
| <instance addr="0x270216C4" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG5"> |
| <instance addr="0x200286C5" reg_inst="0"/> |
| <instance addr="0x200246C5" reg_inst="1"/> |
| <instance addr="0x200226C5" reg_inst="2"/> |
| <instance addr="0x200216C5" reg_inst="3"/> |
| <instance addr="0x210286C5" reg_inst="4"/> |
| <instance addr="0x210246C5" reg_inst="5"/> |
| <instance addr="0x210226C5" reg_inst="6"/> |
| <instance addr="0x210216C5" reg_inst="7"/> |
| <instance addr="0x220286C5" reg_inst="8"/> |
| <instance addr="0x220246C5" reg_inst="9"/> |
| <instance addr="0x220226C5" reg_inst="10"/> |
| <instance addr="0x220216C5" reg_inst="11"/> |
| <instance addr="0x230286C5" reg_inst="12"/> |
| <instance addr="0x230246C5" reg_inst="13"/> |
| <instance addr="0x230226C5" reg_inst="14"/> |
| <instance addr="0x230216C5" reg_inst="15"/> |
| <instance addr="0x240286C5" reg_inst="16"/> |
| <instance addr="0x240246C5" reg_inst="17"/> |
| <instance addr="0x240226C5" reg_inst="18"/> |
| <instance addr="0x240216C5" reg_inst="19"/> |
| <instance addr="0x250286C5" reg_inst="20"/> |
| <instance addr="0x250246C5" reg_inst="21"/> |
| <instance addr="0x250226C5" reg_inst="22"/> |
| <instance addr="0x250216C5" reg_inst="23"/> |
| <instance addr="0x260286C5" reg_inst="24"/> |
| <instance addr="0x260246C5" reg_inst="25"/> |
| <instance addr="0x260226C5" reg_inst="26"/> |
| <instance addr="0x260216C5" reg_inst="27"/> |
| <instance addr="0x270286C5" reg_inst="28"/> |
| <instance addr="0x270246C5" reg_inst="29"/> |
| <instance addr="0x270226C5" reg_inst="30"/> |
| <instance addr="0x270216C5" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG6"> |
| <instance addr="0x200286C6" reg_inst="0"/> |
| <instance addr="0x200246C6" reg_inst="1"/> |
| <instance addr="0x200226C6" reg_inst="2"/> |
| <instance addr="0x200216C6" reg_inst="3"/> |
| <instance addr="0x210286C6" reg_inst="4"/> |
| <instance addr="0x210246C6" reg_inst="5"/> |
| <instance addr="0x210226C6" reg_inst="6"/> |
| <instance addr="0x210216C6" reg_inst="7"/> |
| <instance addr="0x220286C6" reg_inst="8"/> |
| <instance addr="0x220246C6" reg_inst="9"/> |
| <instance addr="0x220226C6" reg_inst="10"/> |
| <instance addr="0x220216C6" reg_inst="11"/> |
| <instance addr="0x230286C6" reg_inst="12"/> |
| <instance addr="0x230246C6" reg_inst="13"/> |
| <instance addr="0x230226C6" reg_inst="14"/> |
| <instance addr="0x230216C6" reg_inst="15"/> |
| <instance addr="0x240286C6" reg_inst="16"/> |
| <instance addr="0x240246C6" reg_inst="17"/> |
| <instance addr="0x240226C6" reg_inst="18"/> |
| <instance addr="0x240216C6" reg_inst="19"/> |
| <instance addr="0x250286C6" reg_inst="20"/> |
| <instance addr="0x250246C6" reg_inst="21"/> |
| <instance addr="0x250226C6" reg_inst="22"/> |
| <instance addr="0x250216C6" reg_inst="23"/> |
| <instance addr="0x260286C6" reg_inst="24"/> |
| <instance addr="0x260246C6" reg_inst="25"/> |
| <instance addr="0x260226C6" reg_inst="26"/> |
| <instance addr="0x260216C6" reg_inst="27"/> |
| <instance addr="0x270286C6" reg_inst="28"/> |
| <instance addr="0x270246C6" reg_inst="29"/> |
| <instance addr="0x270226C6" reg_inst="30"/> |
| <instance addr="0x270216C6" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG7"> |
| <instance addr="0x200286C7" reg_inst="0"/> |
| <instance addr="0x200246C7" reg_inst="1"/> |
| <instance addr="0x200226C7" reg_inst="2"/> |
| <instance addr="0x200216C7" reg_inst="3"/> |
| <instance addr="0x210286C7" reg_inst="4"/> |
| <instance addr="0x210246C7" reg_inst="5"/> |
| <instance addr="0x210226C7" reg_inst="6"/> |
| <instance addr="0x210216C7" reg_inst="7"/> |
| <instance addr="0x220286C7" reg_inst="8"/> |
| <instance addr="0x220246C7" reg_inst="9"/> |
| <instance addr="0x220226C7" reg_inst="10"/> |
| <instance addr="0x220216C7" reg_inst="11"/> |
| <instance addr="0x230286C7" reg_inst="12"/> |
| <instance addr="0x230246C7" reg_inst="13"/> |
| <instance addr="0x230226C7" reg_inst="14"/> |
| <instance addr="0x230216C7" reg_inst="15"/> |
| <instance addr="0x240286C7" reg_inst="16"/> |
| <instance addr="0x240246C7" reg_inst="17"/> |
| <instance addr="0x240226C7" reg_inst="18"/> |
| <instance addr="0x240216C7" reg_inst="19"/> |
| <instance addr="0x250286C7" reg_inst="20"/> |
| <instance addr="0x250246C7" reg_inst="21"/> |
| <instance addr="0x250226C7" reg_inst="22"/> |
| <instance addr="0x250216C7" reg_inst="23"/> |
| <instance addr="0x260286C7" reg_inst="24"/> |
| <instance addr="0x260246C7" reg_inst="25"/> |
| <instance addr="0x260226C7" reg_inst="26"/> |
| <instance addr="0x260216C7" reg_inst="27"/> |
| <instance addr="0x270286C7" reg_inst="28"/> |
| <instance addr="0x270246C7" reg_inst="29"/> |
| <instance addr="0x270226C7" reg_inst="30"/> |
| <instance addr="0x270216C7" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG8"> |
| <instance addr="0x200286C8" reg_inst="0"/> |
| <instance addr="0x200246C8" reg_inst="1"/> |
| <instance addr="0x200226C8" reg_inst="2"/> |
| <instance addr="0x200216C8" reg_inst="3"/> |
| <instance addr="0x210286C8" reg_inst="4"/> |
| <instance addr="0x210246C8" reg_inst="5"/> |
| <instance addr="0x210226C8" reg_inst="6"/> |
| <instance addr="0x210216C8" reg_inst="7"/> |
| <instance addr="0x220286C8" reg_inst="8"/> |
| <instance addr="0x220246C8" reg_inst="9"/> |
| <instance addr="0x220226C8" reg_inst="10"/> |
| <instance addr="0x220216C8" reg_inst="11"/> |
| <instance addr="0x230286C8" reg_inst="12"/> |
| <instance addr="0x230246C8" reg_inst="13"/> |
| <instance addr="0x230226C8" reg_inst="14"/> |
| <instance addr="0x230216C8" reg_inst="15"/> |
| <instance addr="0x240286C8" reg_inst="16"/> |
| <instance addr="0x240246C8" reg_inst="17"/> |
| <instance addr="0x240226C8" reg_inst="18"/> |
| <instance addr="0x240216C8" reg_inst="19"/> |
| <instance addr="0x250286C8" reg_inst="20"/> |
| <instance addr="0x250246C8" reg_inst="21"/> |
| <instance addr="0x250226C8" reg_inst="22"/> |
| <instance addr="0x250216C8" reg_inst="23"/> |
| <instance addr="0x260286C8" reg_inst="24"/> |
| <instance addr="0x260246C8" reg_inst="25"/> |
| <instance addr="0x260226C8" reg_inst="26"/> |
| <instance addr="0x260216C8" reg_inst="27"/> |
| <instance addr="0x270286C8" reg_inst="28"/> |
| <instance addr="0x270246C8" reg_inst="29"/> |
| <instance addr="0x270226C8" reg_inst="30"/> |
| <instance addr="0x270216C8" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG9"> |
| <instance addr="0x200286C9" reg_inst="0"/> |
| <instance addr="0x200246C9" reg_inst="1"/> |
| <instance addr="0x200226C9" reg_inst="2"/> |
| <instance addr="0x200216C9" reg_inst="3"/> |
| <instance addr="0x210286C9" reg_inst="4"/> |
| <instance addr="0x210246C9" reg_inst="5"/> |
| <instance addr="0x210226C9" reg_inst="6"/> |
| <instance addr="0x210216C9" reg_inst="7"/> |
| <instance addr="0x220286C9" reg_inst="8"/> |
| <instance addr="0x220246C9" reg_inst="9"/> |
| <instance addr="0x220226C9" reg_inst="10"/> |
| <instance addr="0x220216C9" reg_inst="11"/> |
| <instance addr="0x230286C9" reg_inst="12"/> |
| <instance addr="0x230246C9" reg_inst="13"/> |
| <instance addr="0x230226C9" reg_inst="14"/> |
| <instance addr="0x230216C9" reg_inst="15"/> |
| <instance addr="0x240286C9" reg_inst="16"/> |
| <instance addr="0x240246C9" reg_inst="17"/> |
| <instance addr="0x240226C9" reg_inst="18"/> |
| <instance addr="0x240216C9" reg_inst="19"/> |
| <instance addr="0x250286C9" reg_inst="20"/> |
| <instance addr="0x250246C9" reg_inst="21"/> |
| <instance addr="0x250226C9" reg_inst="22"/> |
| <instance addr="0x250216C9" reg_inst="23"/> |
| <instance addr="0x260286C9" reg_inst="24"/> |
| <instance addr="0x260246C9" reg_inst="25"/> |
| <instance addr="0x260226C9" reg_inst="26"/> |
| <instance addr="0x260216C9" reg_inst="27"/> |
| <instance addr="0x270286C9" reg_inst="28"/> |
| <instance addr="0x270246C9" reg_inst="29"/> |
| <instance addr="0x270226C9" reg_inst="30"/> |
| <instance addr="0x270216C9" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG10"> |
| <instance addr="0x200286CA" reg_inst="0"/> |
| <instance addr="0x200246CA" reg_inst="1"/> |
| <instance addr="0x200226CA" reg_inst="2"/> |
| <instance addr="0x200216CA" reg_inst="3"/> |
| <instance addr="0x210286CA" reg_inst="4"/> |
| <instance addr="0x210246CA" reg_inst="5"/> |
| <instance addr="0x210226CA" reg_inst="6"/> |
| <instance addr="0x210216CA" reg_inst="7"/> |
| <instance addr="0x220286CA" reg_inst="8"/> |
| <instance addr="0x220246CA" reg_inst="9"/> |
| <instance addr="0x220226CA" reg_inst="10"/> |
| <instance addr="0x220216CA" reg_inst="11"/> |
| <instance addr="0x230286CA" reg_inst="12"/> |
| <instance addr="0x230246CA" reg_inst="13"/> |
| <instance addr="0x230226CA" reg_inst="14"/> |
| <instance addr="0x230216CA" reg_inst="15"/> |
| <instance addr="0x240286CA" reg_inst="16"/> |
| <instance addr="0x240246CA" reg_inst="17"/> |
| <instance addr="0x240226CA" reg_inst="18"/> |
| <instance addr="0x240216CA" reg_inst="19"/> |
| <instance addr="0x250286CA" reg_inst="20"/> |
| <instance addr="0x250246CA" reg_inst="21"/> |
| <instance addr="0x250226CA" reg_inst="22"/> |
| <instance addr="0x250216CA" reg_inst="23"/> |
| <instance addr="0x260286CA" reg_inst="24"/> |
| <instance addr="0x260246CA" reg_inst="25"/> |
| <instance addr="0x260226CA" reg_inst="26"/> |
| <instance addr="0x260216CA" reg_inst="27"/> |
| <instance addr="0x270286CA" reg_inst="28"/> |
| <instance addr="0x270246CA" reg_inst="29"/> |
| <instance addr="0x270226CA" reg_inst="30"/> |
| <instance addr="0x270216CA" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG11"> |
| <instance addr="0x200286CB" reg_inst="0"/> |
| <instance addr="0x200246CB" reg_inst="1"/> |
| <instance addr="0x200226CB" reg_inst="2"/> |
| <instance addr="0x200216CB" reg_inst="3"/> |
| <instance addr="0x210286CB" reg_inst="4"/> |
| <instance addr="0x210246CB" reg_inst="5"/> |
| <instance addr="0x210226CB" reg_inst="6"/> |
| <instance addr="0x210216CB" reg_inst="7"/> |
| <instance addr="0x220286CB" reg_inst="8"/> |
| <instance addr="0x220246CB" reg_inst="9"/> |
| <instance addr="0x220226CB" reg_inst="10"/> |
| <instance addr="0x220216CB" reg_inst="11"/> |
| <instance addr="0x230286CB" reg_inst="12"/> |
| <instance addr="0x230246CB" reg_inst="13"/> |
| <instance addr="0x230226CB" reg_inst="14"/> |
| <instance addr="0x230216CB" reg_inst="15"/> |
| <instance addr="0x240286CB" reg_inst="16"/> |
| <instance addr="0x240246CB" reg_inst="17"/> |
| <instance addr="0x240226CB" reg_inst="18"/> |
| <instance addr="0x240216CB" reg_inst="19"/> |
| <instance addr="0x250286CB" reg_inst="20"/> |
| <instance addr="0x250246CB" reg_inst="21"/> |
| <instance addr="0x250226CB" reg_inst="22"/> |
| <instance addr="0x250216CB" reg_inst="23"/> |
| <instance addr="0x260286CB" reg_inst="24"/> |
| <instance addr="0x260246CB" reg_inst="25"/> |
| <instance addr="0x260226CB" reg_inst="26"/> |
| <instance addr="0x260216CB" reg_inst="27"/> |
| <instance addr="0x270286CB" reg_inst="28"/> |
| <instance addr="0x270246CB" reg_inst="29"/> |
| <instance addr="0x270226CB" reg_inst="30"/> |
| <instance addr="0x270216CB" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG12"> |
| <instance addr="0x200286CC" reg_inst="0"/> |
| <instance addr="0x200246CC" reg_inst="1"/> |
| <instance addr="0x200226CC" reg_inst="2"/> |
| <instance addr="0x200216CC" reg_inst="3"/> |
| <instance addr="0x210286CC" reg_inst="4"/> |
| <instance addr="0x210246CC" reg_inst="5"/> |
| <instance addr="0x210226CC" reg_inst="6"/> |
| <instance addr="0x210216CC" reg_inst="7"/> |
| <instance addr="0x220286CC" reg_inst="8"/> |
| <instance addr="0x220246CC" reg_inst="9"/> |
| <instance addr="0x220226CC" reg_inst="10"/> |
| <instance addr="0x220216CC" reg_inst="11"/> |
| <instance addr="0x230286CC" reg_inst="12"/> |
| <instance addr="0x230246CC" reg_inst="13"/> |
| <instance addr="0x230226CC" reg_inst="14"/> |
| <instance addr="0x230216CC" reg_inst="15"/> |
| <instance addr="0x240286CC" reg_inst="16"/> |
| <instance addr="0x240246CC" reg_inst="17"/> |
| <instance addr="0x240226CC" reg_inst="18"/> |
| <instance addr="0x240216CC" reg_inst="19"/> |
| <instance addr="0x250286CC" reg_inst="20"/> |
| <instance addr="0x250246CC" reg_inst="21"/> |
| <instance addr="0x250226CC" reg_inst="22"/> |
| <instance addr="0x250216CC" reg_inst="23"/> |
| <instance addr="0x260286CC" reg_inst="24"/> |
| <instance addr="0x260246CC" reg_inst="25"/> |
| <instance addr="0x260226CC" reg_inst="26"/> |
| <instance addr="0x260216CC" reg_inst="27"/> |
| <instance addr="0x270286CC" reg_inst="28"/> |
| <instance addr="0x270246CC" reg_inst="29"/> |
| <instance addr="0x270226CC" reg_inst="30"/> |
| <instance addr="0x270216CC" reg_inst="31"/> |
| </register> |
| <register name="LSU_HOLD_OUT_REG13"> |
| <instance addr="0x200286CD" reg_inst="0"/> |
| <instance addr="0x200246CD" reg_inst="1"/> |
| <instance addr="0x200226CD" reg_inst="2"/> |
| <instance addr="0x200216CD" reg_inst="3"/> |
| <instance addr="0x210286CD" reg_inst="4"/> |
| <instance addr="0x210246CD" reg_inst="5"/> |
| <instance addr="0x210226CD" reg_inst="6"/> |
| <instance addr="0x210216CD" reg_inst="7"/> |
| <instance addr="0x220286CD" reg_inst="8"/> |
| <instance addr="0x220246CD" reg_inst="9"/> |
| <instance addr="0x220226CD" reg_inst="10"/> |
| <instance addr="0x220216CD" reg_inst="11"/> |
| <instance addr="0x230286CD" reg_inst="12"/> |
| <instance addr="0x230246CD" reg_inst="13"/> |
| <instance addr="0x230226CD" reg_inst="14"/> |
| <instance addr="0x230216CD" reg_inst="15"/> |
| <instance addr="0x240286CD" reg_inst="16"/> |
| <instance addr="0x240246CD" reg_inst="17"/> |
| <instance addr="0x240226CD" reg_inst="18"/> |
| <instance addr="0x240216CD" reg_inst="19"/> |
| <instance addr="0x250286CD" reg_inst="20"/> |
| <instance addr="0x250246CD" reg_inst="21"/> |
| <instance addr="0x250226CD" reg_inst="22"/> |
| <instance addr="0x250216CD" reg_inst="23"/> |
| <instance addr="0x260286CD" reg_inst="24"/> |
| <instance addr="0x260246CD" reg_inst="25"/> |
| <instance addr="0x260226CD" reg_inst="26"/> |
| <instance addr="0x260216CD" reg_inst="27"/> |
| <instance addr="0x270286CD" reg_inst="28"/> |
| <instance addr="0x270246CD" reg_inst="29"/> |
| <instance addr="0x270226CD" reg_inst="30"/> |
| <instance addr="0x270216CD" reg_inst="31"/> |
| </register> |
| <capture_group node_inst="0:31"> |
| <capture_register reg_name="HV_PR_STATE" reg_inst= "0:31" /> |
| <capture_register reg_name="PC_FIR_HOLD_OUT" reg_inst= "0:31" /> |
| <capture_register reg_name="THRCTL_HOLD_OUT" reg_inst= "0:31" /> |
| <capture_register reg_name="VSU_HOLD_OUT" reg_inst= "0:31" /> |
| <capture_register reg_name="TFAC_HOLD_OUT" reg_inst= "0:31" /> |
| <capture_register reg_name="IFU_HOLD_OUT0" reg_inst= "0:31" /> |
| <capture_register reg_name="IFU_HOLD_OUT1" reg_inst= "0:31" /> |
| <capture_register reg_name="IFU_HOLD_OUT2" reg_inst= "0:31" /> |
| <capture_register reg_name="IFU_HOLD_OUT3" reg_inst= "0:31" /> |
| <capture_register reg_name="ISU_HOLD_OUT0" reg_inst= "0:31" /> |
| <capture_register reg_name="ISU_HOLD_OUT1" reg_inst= "0:31" /> |
| <capture_register reg_name="ISU_HOLD_OUT2" reg_inst= "0:31" /> |
| <capture_register reg_name="ISU_HOLD_OUT3" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT0" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT1" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT2" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT3" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT4" reg_inst= "0:31" /> |
| <capture_register reg_name="MMU_HOLD_OUT5" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG0" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG1" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG2" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG3" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG4" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG5" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG6" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG7" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG8" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG9" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG10" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG11" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG12" reg_inst= "0:31" /> |
| <capture_register reg_name="LSU_HOLD_OUT_REG13" reg_inst= "0:31" /> |
| </capture_group> |
| <rule attn_type="CS" node_inst="0:31"> |
| <!-- FIR & ~MASK & ~ACT0 & ~ACT1 --> |
| <expr type="and"> |
| <expr type="reg" value1="EQ_CORE_FIR"/> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| </expr> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| </expr> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| </expr> |
| </expr> |
| </rule> |
| <rule attn_type="RE" node_inst="0:31"> |
| <!-- WOF & ~MASK & ~ACT0 & ACT1 --> |
| <expr type="and"> |
| <expr type="reg" value1="EQ_CORE_FIR_WOF"/> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| </expr> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| </expr> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| </expr> |
| </rule> |
| <rule attn_type="UCS" node_inst="0:31"> |
| <!-- (FIR | WOF) & ~MASK & ACT0 & ACT1 --> |
| <expr type="and"> |
| <expr type="or"> |
| <expr type="reg" value1="EQ_CORE_FIR"/> |
| <expr type="reg" value1="EQ_CORE_FIR_WOF"/> |
| </expr> |
| <expr type="not"> |
| <expr type="reg" value1="EQ_CORE_FIR_MASK"/> |
| </expr> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT0"/> |
| <expr type="reg" value1="EQ_CORE_FIR_ACT1"/> |
| </expr> |
| </rule> |
| <bit pos="0">IFU SRAM recoverable error (ICACHE parity error, etc)</bit> |
| <bit pos="1">TC checkstop</bit> |
| <bit pos="2">IFU RegFile recoverable error</bit> |
| <bit pos="3">IFU RegFile core checkstop</bit> |
| <bit pos="4">IFU logic recoverable error</bit> |
| <bit pos="5">IFU logic core checkstop</bit> |
| <bit pos="6">reserved</bit> |
| <bit pos="7">VSU Inference Accumulator recoverable error</bit> |
| <bit pos="8">Recovery core checkstop</bit> |
| <bit pos="9">VSU Slice Targeted File (STF) recoverable error</bit> |
| <bit pos="10">reserved</bit> |
| <bit pos="11">ISU logic recoverable error</bit> |
| <bit pos="12">ISU logic core checkstop</bit> |
| <bit pos="13">reserved</bit> |
| <bit pos="14">MCHK received while ME=0 - non recoverable</bit> |
| <bit pos="15">UE from L2</bit> |
| <bit pos="16">Number of UEs from L2 above threshold</bit> |
| <bit pos="17">UE on CI load</bit> |
| <bit pos="18">MMU TLB parity recoverable error</bit> |
| <bit pos="19">MMU SLB parity recoverable error</bit> |
| <bit pos="20">reserved</bit> |
| <bit pos="21">MMU CXT recoverable error</bit> |
| <bit pos="22">MMU logic core checkstop</bit> |
| <bit pos="23">MMU system checkstop</bit> |
| <bit pos="24">VSU logic recoverable error</bit> |
| <bit pos="25">VSU logic core checkstop</bit> |
| <bit pos="26">Thread in maintenance mode and receives recovery request</bit> |
| <bit pos="27">reserved</bit> |
| <bit pos="28">PC system checkstop - Recoverable error received when recovery disabled</bit> |
| <bit pos="29">LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)</bit> |
| <bit pos="30">LSU set deleted</bit> |
| <bit pos="31">LSU RegFile recoverable error</bit> |
| <bit pos="32">LSU RegFile core checkstop</bit> |
| <bit pos="33">MMU TLB multi hit error occurred</bit> |
| <bit pos="34">MMU SLB multi hit error occurred</bit> |
| <bit pos="35">LSU ERAT multi hit error occurred</bit> |
| <bit pos="36">PC forward progress error</bit> |
| <bit pos="37">LSU logic recoverable error</bit> |
| <bit pos="38">LSU logic core checkstop</bit> |
| <bit pos="39">reserved</bit> |
| <bit pos="40">reserved</bit> |
| <bit pos="41">LSU system checkstop</bit> |
| <bit pos="42">reserved</bit> |
| <bit pos="43">PC thread hang recoverable error</bit> |
| <bit pos="44">reserved</bit> |
| <bit pos="45">PC logic checkstop</bit> |
| <bit pos="46">PC TimeBase Facility checkstop</bit> |
| <bit pos="47">PC TimeBase Facility checkstop</bit> |
| <bit pos="48">reserved</bit> |
| <bit pos="49">reserved</bit> |
| <bit pos="50">reserved</bit> |
| <bit pos="51">reserved</bit> |
| <bit pos="52">Hang Recovery Failed</bit> |
| <bit pos="53">Core Hang detected</bit> |
| <bit pos="54">reserved</bit> |
| <bit pos="55">Nest Hang detected</bit> |
| <bit pos="56">Other Core Chiplet recoverable error</bit> |
| <bit pos="57">Other Core Chiplet core checkstop</bit> |
| <bit pos="58">Other Core Chiplet system checkstop</bit> |
| <bit pos="59">SCOM satellite error detected</bit> |
| <bit pos="60">Debug Trigger error inject</bit> |
| <bit pos="61">SCOM or Firmware recoverable error inject</bit> |
| <bit pos="62">Firmware checkstop error inject</bit> |
| <bit pos="63">PHYP checkstop via SPRC/SPRD</bit> |
| </attn_node> |