commit 93cd64ea88f53cf3826b2ffee8cb70f6b0dc4733
author Zane Shelley <zshelle@us.ibm.com> Thu Sep 23 09:37:12 2021 -0500
committer Zane Shelley <zshelle@us.ibm.com> Thu Sep 23 09:37:12 2021 -0500
tree 929076d42dc5950b03a63b6f0ed41888fbbddf98
parent 4aebf40d5efddb84840fce1d8419ec799e36cdd2

Add handling for bit 2 in all recoverable chiplet FIRs

Bit 2 in the recoverable chiplet FIRs is a special bit that indicates
there is a unit checkstop on that chiplet as well. If we ignore that bit
like we were and there was a unit checkstop attention with no
recoverable attentions, the isolator will return signatures from the
GFIR which will just confuse things.

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ic340c0e765f266b2980561913df8c64461febcba

xml/p10/node_cfir_iohs_cs.xml

diff --git a/xml/p10/node_cfir_iohs_cs.xml b/xml/p10/node_cfir_iohs_cs.xml
new file mode 100644
index 0000000..35f1980
--- /dev/null
+++ b/xml/p10/node_cfir_iohs_cs.xml
@@ -0,0 +1,34 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_CS" reg_type="SCOM">
+    <register name="CFIR_IOHS_CS">
+        <instance addr="0x18040000" reg_inst="0"/>
+        <instance addr="0x19040000" reg_inst="1"/>
+        <instance addr="0x1A040000" reg_inst="2"/>
+        <instance addr="0x1B040000" reg_inst="3"/>
+        <instance addr="0x1C040000" reg_inst="4"/>
+        <instance addr="0x1D040000" reg_inst="5"/>
+        <instance addr="0x1E040000" reg_inst="6"/>
+        <instance addr="0x1F040000" reg_inst="7"/>
+    </register>
+    <register name="CFIR_IOHS_CS_MASK">
+        <instance addr="0x18040040" reg_inst="0"/>
+        <instance addr="0x19040040" reg_inst="1"/>
+        <instance addr="0x1A040040" reg_inst="2"/>
+        <instance addr="0x1B040040" reg_inst="3"/>
+        <instance addr="0x1C040040" reg_inst="4"/>
+        <instance addr="0x1D040040" reg_inst="5"/>
+        <instance addr="0x1E040040" reg_inst="6"/>
+        <instance addr="0x1F040040" reg_inst="7"/>
+    </register>
+    <rule attn_type="CS" node_inst="0:7">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_IOHS_CS"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_IOHS_CS_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="IOHS_LOCAL_FIR" node_inst="0,1,2,3,4,5,6,7" pos="4">Attention from IOHS_LOCAL_FIR</bit>
+    <bit child_node="IOHS_DLP_FIR" node_inst="0,1,2,3,4,5,6,7" pos="5">Attention from IOHS_DLP_FIR</bit>
+</attn_node>