commit 94ea8ed1369e0b26be0aec2fe7dfdf87ccada581
author Caleb Palmer <cnpalmer@us.ibm.com> Thu Jul 25 14:26:46 2024 -0500
committer Caleb Palmer <cnpalmer@us.ibm.com> Mon Jul 29 12:39:30 2024 -0500
tree b6f91edbd66e7cf6bc52ddc876a5b8f141c675b0
parent f2a2932f736be2e51758e9ca4236cf714c5cbcf6

Update chip data files with new write operation rules

Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com>
Change-Id: Ide9bad598dbf8c766632c840f4c4c3f8a882bc3e

chip_data/explorer/node_tlxfir.json

diff --git a/chip_data/explorer/node_tlxfir.json b/chip_data/explorer/node_tlxfir.json
index a159694..f6306ac 100644
--- a/chip_data/explorer/node_tlxfir.json
+++ b/chip_data/explorer/node_tlxfir.json
@@ -7,11 +7,35 @@
                 "0": "0x08012400"
             }
         },
+        "TLXFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012401"
+            }
+        },
+        "TLXFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012402"
+            }
+        },
         "TLXFIR_MASK": {
             "instances": {
                 "0": "0x08012403"
             }
         },
+        "TLXFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012404"
+            }
+        },
+        "TLXFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012405"
+            }
+        },
         "TLXFIR_ACT0": {
             "instances": {
                 "0": "0x08012406"
@@ -159,6 +183,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "TLXFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "TLXFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "TLXFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "TLXFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "Info reg parity error"