diff --git a/chip_data/explorer/chip_explorer.json b/chip_data/explorer/chip_explorer.json
index 1d6f606..897218a 100644
--- a/chip_data/explorer/chip_explorer.json
+++ b/chip_data/explorer/chip_explorer.json
@@ -3,11 +3,11 @@
     "model_ec": ["EXPLORER_11", "EXPLORER_20"],
     "root_nodes": {
         "CHIP_CS": {
-            "name": "CHIPLET_OCMB_FIR",
+            "name": "CHIPLET_OCMB_FIR_CHIP_CS",
             "inst": 0
         },
         "RECOV": {
-            "name": "CHIPLET_OCMB_FIR",
+            "name": "CHIPLET_OCMB_FIR_RECOV",
             "inst": 0
         },
         "SP_ATTN": {
diff --git a/chip_data/explorer/node_chiplet_ocmb_fir.json b/chip_data/explorer/node_chiplet_ocmb_fir.json
index 9217105..1fa102f 100644
--- a/chip_data/explorer/node_chiplet_ocmb_fir.json
+++ b/chip_data/explorer/node_chiplet_ocmb_fir.json
@@ -19,7 +19,7 @@
         }
     },
     "isolation_nodes": {
-        "CHIPLET_OCMB_FIR": {
+        "CHIPLET_OCMB_FIR_CHIP_CS": {
             "instances": [0],
             "rules": [
                 {
@@ -45,7 +45,66 @@
                             }
                         ]
                     }
+                }
+            ],
+            "op_rules": {
+                "MASK_SET": {
+                    "op_rule": "read_set_write",
+                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
                 },
+                "MASK_CLEAR": {
+                    "op_rule": "read_clear_write",
+                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
+                }
+            },
+            "bits": {
+                "3": {
+                    "desc": "Attention from OCMB_LFIR",
+                    "child_node": {
+                        "name": "OCMB_LFIR"
+                    }
+                },
+                "4": {
+                    "desc": "Attention from MMIOFIR",
+                    "child_node": {
+                        "name": "MMIOFIR"
+                    }
+                },
+                "7": {
+                    "desc": "Attention from SRQFIR",
+                    "child_node": {
+                        "name": "SRQFIR"
+                    }
+                },
+                "8": {
+                    "desc": "Attention from MCBISTFIR",
+                    "child_node": {
+                        "name": "MCBISTFIR"
+                    }
+                },
+                "9": {
+                    "desc": "Attention from RDFFIR",
+                    "child_node": {
+                        "name": "RDFFIR"
+                    }
+                },
+                "11": {
+                    "desc": "Attention from TLXFIR",
+                    "child_node": {
+                        "name": "TLXFIR"
+                    }
+                },
+                "12": {
+                    "desc": "Attention from OMI_DL_FIR",
+                    "child_node": {
+                        "name": "OMI_DL_FIR"
+                    }
+                }
+            }
+        },
+        "CHIPLET_OCMB_FIR_RECOV": {
+            "instances": [0],
+            "rules": [
                 {
                     "attn_type": ["RECOV"],
                     "node_inst": [0],
@@ -75,6 +134,16 @@
                     }
                 }
             ],
+            "op_rules": {
+                "MASK_SET": {
+                    "op_rule": "read_set_write",
+                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "read_clear_write",
+                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
+                }
+            },
             "bits": {
                 "3": {
                     "desc": "Attention from OCMB_LFIR",
diff --git a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
index 4465e69..f8771f9 100644
--- a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
+++ b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
@@ -38,6 +38,16 @@
                     }
                 }
             ],
+            "op_rules": {
+                "MASK_SET": {
+                    "op_rule": "read_set_write",
+                    "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "read_clear_write",
+                    "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+                }
+            },
             "bits": {
                 "1": {
                     "desc": "Attention from MMIOFIR",
diff --git a/chip_data/explorer/node_mcbistfir.json b/chip_data/explorer/node_mcbistfir.json
index 666e57c..e70af77 100644
--- a/chip_data/explorer/node_mcbistfir.json
+++ b/chip_data/explorer/node_mcbistfir.json
@@ -7,11 +7,35 @@
                 "0": "0x08011800"
             }
         },
+        "MCBISTFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011801"
+            }
+        },
+        "MCBISTFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011802"
+            }
+        },
         "MCBISTFIR_MASK": {
             "instances": {
                 "0": "0x08011803"
             }
         },
+        "MCBISTFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011804"
+            }
+        },
+        "MCBISTFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011805"
+            }
+        },
         "MCBISTFIR_ACT0": {
             "instances": {
                 "0": "0x08011806"
@@ -139,6 +163,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "MCBISTFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "MCBISTFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "MCBISTFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "MCBISTFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "Invalid maint address"
diff --git a/chip_data/explorer/node_mmiofir.json b/chip_data/explorer/node_mmiofir.json
index d0a0824..7aa501d 100644
--- a/chip_data/explorer/node_mmiofir.json
+++ b/chip_data/explorer/node_mmiofir.json
@@ -7,11 +7,35 @@
                 "0": "0x08010870"
             }
         },
+        "MMIOFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08010871"
+            }
+        },
+        "MMIOFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08010872"
+            }
+        },
         "MMIOFIR_MASK": {
             "instances": {
                 "0": "0x08010873"
             }
         },
+        "MMIOFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08010874"
+            }
+        },
+        "MMIOFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08010875"
+            }
+        },
         "MMIOFIR_ACT0": {
             "instances": {
                 "0": "0x08010876"
@@ -139,6 +163,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "MMIOFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "MMIOFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "MMIOFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "MMIOFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "AFU desc unimp"
diff --git a/chip_data/explorer/node_ocmb_lfir.json b/chip_data/explorer/node_ocmb_lfir.json
index 4786883..2b7d896 100644
--- a/chip_data/explorer/node_ocmb_lfir.json
+++ b/chip_data/explorer/node_ocmb_lfir.json
@@ -7,11 +7,35 @@
                 "0": "0x0804000A"
             }
         },
+        "OCMB_LFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x0804000B"
+            }
+        },
+        "OCMB_LFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x0804000C"
+            }
+        },
         "OCMB_LFIR_MASK": {
             "instances": {
                 "0": "0x0804000D"
             }
         },
+        "OCMB_LFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x0804000E"
+            }
+        },
+        "OCMB_LFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x0804000F"
+            }
+        },
         "OCMB_LFIR_ACT0": {
             "instances": {
                 "0": "0x08040010"
@@ -117,6 +141,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "OCMB_LFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "OCMB_LFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "OCMB_LFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "OCMB_LFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "CFIR access PCB error"
diff --git a/chip_data/explorer/node_omi_dl_fir.json b/chip_data/explorer/node_omi_dl_fir.json
index 3b86cbb..0930ea0 100644
--- a/chip_data/explorer/node_omi_dl_fir.json
+++ b/chip_data/explorer/node_omi_dl_fir.json
@@ -7,11 +7,35 @@
                 "0": "0x08012800"
             }
         },
+        "OMI_DL_FIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012801"
+            }
+        },
+        "OMI_DL_FIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012802"
+            }
+        },
         "OMI_DL_FIR_MASK": {
             "instances": {
                 "0": "0x08012803"
             }
         },
+        "OMI_DL_FIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012804"
+            }
+        },
+        "OMI_DL_FIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012805"
+            }
+        },
         "OMI_DL_FIR_ACT0": {
             "instances": {
                 "0": "0x08012806"
@@ -204,6 +228,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "OMI_DL_FIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "OMI_DL_FIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "OMI_DL_FIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "OMI_DL_FIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "OMI-DL0 fatal error",
diff --git a/chip_data/explorer/node_rdffir.json b/chip_data/explorer/node_rdffir.json
index eafc663..1abc018 100644
--- a/chip_data/explorer/node_rdffir.json
+++ b/chip_data/explorer/node_rdffir.json
@@ -7,11 +7,35 @@
                 "0": "0x08011C00"
             }
         },
+        "RDFFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011C01"
+            }
+        },
+        "RDFFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011C02"
+            }
+        },
         "RDFFIR_MASK": {
             "instances": {
                 "0": "0x08011C03"
             }
         },
+        "RDFFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011C04"
+            }
+        },
+        "RDFFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011C05"
+            }
+        },
         "RDFFIR_ACT0": {
             "instances": {
                 "0": "0x08011C06"
@@ -276,6 +300,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "RDFFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "RDFFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "RDFFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "RDFFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "Mainline read MPE on rank 0"
diff --git a/chip_data/explorer/node_srqfir.json b/chip_data/explorer/node_srqfir.json
index c8aa095..64ff720 100644
--- a/chip_data/explorer/node_srqfir.json
+++ b/chip_data/explorer/node_srqfir.json
@@ -7,11 +7,35 @@
                 "0": "0x08011400"
             }
         },
+        "SRQFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011401"
+            }
+        },
+        "SRQFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011402"
+            }
+        },
         "SRQFIR_MASK": {
             "instances": {
                 "0": "0x08011403"
             }
         },
+        "SRQFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011404"
+            }
+        },
+        "SRQFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08011405"
+            }
+        },
         "SRQFIR_ACT0": {
             "instances": {
                 "0": "0x08011406"
@@ -134,6 +158,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "SRQFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "SRQFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "SRQFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "SRQFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "SRQ recoverable error"
diff --git a/chip_data/explorer/node_tlxfir.json b/chip_data/explorer/node_tlxfir.json
index a159694..f6306ac 100644
--- a/chip_data/explorer/node_tlxfir.json
+++ b/chip_data/explorer/node_tlxfir.json
@@ -7,11 +7,35 @@
                 "0": "0x08012400"
             }
         },
+        "TLXFIR_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012401"
+            }
+        },
+        "TLXFIR_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012402"
+            }
+        },
         "TLXFIR_MASK": {
             "instances": {
                 "0": "0x08012403"
             }
         },
+        "TLXFIR_MASK_AND": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012404"
+            }
+        },
+        "TLXFIR_MASK_OR": {
+            "access": "WO",
+            "instances": {
+                "0": "0x08012405"
+            }
+        },
         "TLXFIR_ACT0": {
             "instances": {
                 "0": "0x08012406"
@@ -159,6 +183,24 @@
                     }
                 }
             ],
+            "op_rules": {
+                "FIR_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "TLXFIR_OR"
+                },
+                "FIR_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "TLXFIR_AND"
+                },
+                "MASK_SET": {
+                    "op_rule": "atomic_or",
+                    "reg_name": "TLXFIR_MASK_OR"
+                },
+                "MASK_CLEAR": {
+                    "op_rule": "atomic_and",
+                    "reg_name": "TLXFIR_MASK_AND"
+                }
+            },
             "bits": {
                 "0": {
                     "desc": "Info reg parity error"