Update chip data files with new write operation rules
Signed-off-by: Caleb Palmer <cnpalmer@us.ibm.com>
Change-Id: Ide9bad598dbf8c766632c840f4c4c3f8a882bc3e
diff --git a/chip_data/odyssey/node_cfir_mem.json b/chip_data/odyssey/node_cfir_mem.json
index d87e6b7..fc3fa58 100644
--- a/chip_data/odyssey/node_cfir_mem.json
+++ b/chip_data/odyssey/node_cfir_mem.json
@@ -27,24 +27,72 @@
"0": "0x08040040"
}
},
+ "CFIR_MEM_CHIP_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040050"
+ }
+ },
+ "CFIR_MEM_CHIP_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040060"
+ }
+ },
"CFIR_MEM_RECOV_MASK": {
"instances": {
"0": "0x08040041"
}
},
+ "CFIR_MEM_RECOV_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040051"
+ }
+ },
+ "CFIR_MEM_RECOV_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040061"
+ }
+ },
"CFIR_MEM_SP_ATTN_MASK": {
"instances": {
"0": "0x08040042"
}
},
+ "CFIR_MEM_SP_ATTN_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040052"
+ }
+ },
+ "CFIR_MEM_SP_ATTN_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040062"
+ }
+ },
"CFIR_MEM_UNIT_CS_MASK": {
"instances": {
"0": "0x08040043"
}
+ },
+ "CFIR_MEM_UNIT_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040053"
+ }
+ },
+ "CFIR_MEM_UNIT_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040063"
+ }
}
},
"isolation_nodes": {
- "CFIR_MEM": {
+ "CFIR_MEM_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -70,7 +118,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_CHIP_CS_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_CHIP_CS_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -94,7 +237,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_RECOV_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_RECOV_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -118,7 +356,102 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_SP_ATTN_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_SP_ATTN_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_MEM_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -144,6 +477,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_UNIT_CS_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_MEM_UNIT_CS_MASK_CLEAR"
+ }
+ },
"bits": {
"4": {
"desc": "Attention from MEM_LOCAL_FIR",
diff --git a/chip_data/odyssey/node_cfir_tp.json b/chip_data/odyssey/node_cfir_tp.json
index aabdb6c..4b588e3 100644
--- a/chip_data/odyssey/node_cfir_tp.json
+++ b/chip_data/odyssey/node_cfir_tp.json
@@ -27,24 +27,72 @@
"0": "0x01040040"
}
},
+ "CFIR_TP_CHIP_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040050"
+ }
+ },
+ "CFIR_TP_CHIP_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040060"
+ }
+ },
"CFIR_TP_RECOV_MASK": {
"instances": {
"0": "0x01040041"
}
},
+ "CFIR_TP_RECOV_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040051"
+ }
+ },
+ "CFIR_TP_RECOV_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040061"
+ }
+ },
"CFIR_TP_SP_ATTN_MASK": {
"instances": {
"0": "0x01040042"
}
},
+ "CFIR_TP_SP_ATTN_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040052"
+ }
+ },
+ "CFIR_TP_SP_ATTN_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040062"
+ }
+ },
"CFIR_TP_UNIT_CS_MASK": {
"instances": {
"0": "0x01040043"
}
+ },
+ "CFIR_TP_UNIT_CS_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040053"
+ }
+ },
+ "CFIR_TP_UNIT_CS_MASK_CLEAR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040063"
+ }
}
},
"isolation_nodes": {
- "CFIR_TP": {
+ "CFIR_TP_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -70,7 +118,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_CHIP_CS_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_CHIP_CS_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -94,7 +165,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_RECOV_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_RECOV_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -118,7 +212,30 @@
}
]
}
+ }
+ ],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_SP_ATTN_MASK_OR"
},
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_SP_ATTN_MASK_CLEAR"
+ }
+ },
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ },
+ "CFIR_TP_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -144,6 +261,16 @@
}
}
],
+ "op_rules": {
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_UNIT_CS_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "CFIR_TP_UNIT_CS_MASK_CLEAR"
+ }
+ },
"bits": {
"4": {
"desc": "Attention from TP_LOCAL_FIR",
diff --git a/chip_data/odyssey/node_dlx_fir.json b/chip_data/odyssey/node_dlx_fir.json
index c42f877..e687b7f 100644
--- a/chip_data/odyssey/node_dlx_fir.json
+++ b/chip_data/odyssey/node_dlx_fir.json
@@ -7,11 +7,23 @@
"0": "0x08012400"
}
},
+ "DLX_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012401"
+ }
+ },
"DLX_FIR_MASK": {
"instances": {
"0": "0x08012402"
}
},
+ "DLX_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012403"
+ }
+ },
"DLX_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08012404"
@@ -224,6 +236,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error in SCOM component"
diff --git a/chip_data/odyssey/node_gfir.json b/chip_data/odyssey/node_gfir.json
index cead761..2312206 100644
--- a/chip_data/odyssey/node_gfir.json
+++ b/chip_data/odyssey/node_gfir.json
@@ -24,7 +24,7 @@
}
},
"isolation_nodes": {
- "GFIR": {
+ "GFIR_CHIP_CS": {
"instances": [0],
"rules": [
{
@@ -34,7 +34,32 @@
"expr_type": "reg",
"reg_name": "GFIR_CHIP_CS"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_CHIP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_CHIP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_RECOV": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["RECOV"],
"node_inst": [0],
@@ -42,7 +67,32 @@
"expr_type": "reg",
"reg_name": "GFIR_RECOV"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_RECOV",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_RECOV",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_SP_ATTN": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["SP_ATTN"],
"node_inst": [0],
@@ -50,7 +100,32 @@
"expr_type": "reg",
"reg_name": "GFIR_SP_ATTN"
}
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_SP_ATTN",
+ "inst": {
+ "0": 0
+ }
+ }
},
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM_SP_ATTN",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "GFIR_UNIT_CS": {
+ "instances": [0],
+ "rules": [
{
"attn_type": ["UNIT_CS"],
"node_inst": [0],
@@ -64,7 +139,7 @@
"1": {
"desc": "Attention from TP chiplet",
"child_node": {
- "name": "CFIR_TP",
+ "name": "CFIR_TP_UNIT_CS",
"inst": {
"0": 0
}
@@ -73,7 +148,7 @@
"8": {
"desc": "Attention from MEM chiplet",
"child_node": {
- "name": "CFIR_MEM",
+ "name": "CFIR_MEM_UNIT_CS",
"inst": {
"0": 0
}
diff --git a/chip_data/odyssey/node_mcbist_fir.json b/chip_data/odyssey/node_mcbist_fir.json
index cc2f457..f2d2aec 100644
--- a/chip_data/odyssey/node_mcbist_fir.json
+++ b/chip_data/odyssey/node_mcbist_fir.json
@@ -7,11 +7,23 @@
"0": "0x08011400"
}
},
+ "MCBIST_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011401"
+ }
+ },
"MCBIST_FIR_MASK": {
"instances": {
"0": "0x08011402"
}
},
+ "MCBIST_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011403"
+ }
+ },
"MCBIST_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011404"
@@ -274,6 +286,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error in scom component"
diff --git a/chip_data/odyssey/node_mem_local_fir.json b/chip_data/odyssey/node_mem_local_fir.json
index b7bc2f0..5f8136e 100644
--- a/chip_data/odyssey/node_mem_local_fir.json
+++ b/chip_data/odyssey/node_mem_local_fir.json
@@ -7,11 +7,23 @@
"0": "0x08040100"
}
},
+ "MEM_LOCAL_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040101"
+ }
+ },
"MEM_LOCAL_FIR_MASK": {
"instances": {
"0": "0x08040102"
}
},
+ "MEM_LOCAL_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08040103"
+ }
+ },
"MEM_LOCAL_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08040104"
@@ -154,6 +166,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "CFIR/LFIR parity error"
@@ -162,19 +192,59 @@
"desc": "CPLT_CTRL - PCB access error"
},
"2": {
- "desc": "CC - PCB access error"
+ "desc": "CC - PCB access error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"3": {
- "desc": "CC - clock control error"
+ "desc": "CC - clock control error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"4": {
- "desc": "PSC - PSCOM Access Error"
+ "desc": "PSC - PSCOM Access Error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"5": {
- "desc": "PSC - internal or ring interface error"
+ "desc": "PSC - internal or ring interface error",
+ "capture_groups": [
+ {
+ "group_name": "MEM_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"6": {
- "desc": "THERM - various errors"
+ "desc": "THERM - various errors",
+ "capture_groups": [
+ {
+ "group_name": "MEM_DTS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"7": {
"desc": "DBG - SCOM parity fail"
@@ -194,31 +264,27 @@
"63": {
"desc": "external local checkstop"
}
- },
- "capture_groups": [
- {
- "group_name": "MEM_LOCAL_FIR",
- "group_inst": {
- "0": 0
- }
- }
- ]
+ }
}
},
"capture_groups": {
- "MEM_LOCAL_FIR": [
- {
- "reg_name": "MEM_PSCOM_STATUS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
+ "MEM_ERR_STATUS_CG": [
{
"reg_name": "MEM_ERR_STATUS",
"reg_inst": {
"0": 0
}
- },
+ }
+ ],
+ "MEM_PSCOM_STATUS_ERR_CG": [
+ {
+ "reg_name": "MEM_PSCOM_STATUS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "MEM_DTS_ERR_CG": [
{
"reg_name": "MEM_DTS_ERR",
"reg_inst": {
diff --git a/chip_data/odyssey/node_mmio_fir.json b/chip_data/odyssey/node_mmio_fir.json
index b2a2de0..8504759 100644
--- a/chip_data/odyssey/node_mmio_fir.json
+++ b/chip_data/odyssey/node_mmio_fir.json
@@ -7,11 +7,23 @@
"0": "0x08010870"
}
},
+ "MMIO_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010871"
+ }
+ },
"MMIO_FIR_MASK": {
"instances": {
"0": "0x08010872"
}
},
+ "MMIO_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010873"
+ }
+ },
"MMIO_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08010874"
@@ -149,6 +161,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Interal SCOM logic parity error"
diff --git a/chip_data/odyssey/node_ocmb_phy_fir.json b/chip_data/odyssey/node_ocmb_phy_fir.json
index 7a17bdb..f0ef35f 100644
--- a/chip_data/odyssey/node_ocmb_phy_fir.json
+++ b/chip_data/odyssey/node_ocmb_phy_fir.json
@@ -7,11 +7,23 @@
"0": "0x08010C00"
}
},
+ "OCMB_PHY_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010C01"
+ }
+ },
"OCMB_PHY_FIR_MASK": {
"instances": {
"0": "0x08010C02"
}
},
+ "OCMB_PHY_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08010C03"
+ }
+ },
"OCMB_PHY_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08010C04"
@@ -139,6 +151,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "SCOM FSM or FIR register parity error"
diff --git a/chip_data/odyssey/node_odp_fir.json b/chip_data/odyssey/node_odp_fir.json
index efa697e..beb3317 100644
--- a/chip_data/odyssey/node_odp_fir.json
+++ b/chip_data/odyssey/node_odp_fir.json
@@ -8,12 +8,26 @@
"1": "0x08013400"
}
},
+ "ODP_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08013001",
+ "1": "0x08013401"
+ }
+ },
"ODP_FIR_MASK": {
"instances": {
"0": "0x08013002",
"1": "0x08013402"
}
},
+ "ODP_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08013003",
+ "1": "0x08013403"
+ }
+ },
"ODP_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08013004",
@@ -433,6 +447,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
diff --git a/chip_data/odyssey/node_rdf_fir.json b/chip_data/odyssey/node_rdf_fir.json
index 3c84186..a90f768 100644
--- a/chip_data/odyssey/node_rdf_fir.json
+++ b/chip_data/odyssey/node_rdf_fir.json
@@ -8,12 +8,26 @@
"1": "0x08012800"
}
},
+ "RDF_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011801",
+ "1": "0x08012801"
+ }
+ },
"RDF_FIR_MASK": {
"instances": {
"0": "0x08011802",
"1": "0x08012802"
}
},
+ "RDF_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011803",
+ "1": "0x08012803"
+ }
+ },
"RDF_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011804",
@@ -260,6 +274,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal SCOM error"
diff --git a/chip_data/odyssey/node_srq_fir.json b/chip_data/odyssey/node_srq_fir.json
index 8989871..24e6b31 100644
--- a/chip_data/odyssey/node_srq_fir.json
+++ b/chip_data/odyssey/node_srq_fir.json
@@ -7,11 +7,23 @@
"0": "0x08011000"
}
},
+ "SRQ_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011001"
+ }
+ },
"SRQ_FIR_MASK": {
"instances": {
"0": "0x08011002"
}
},
+ "SRQ_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08011003"
+ }
+ },
"SRQ_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08011004"
@@ -174,6 +186,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
@@ -313,7 +343,10 @@
"45": {
"desc": "DSM errors port1"
},
- "46:48": {
+ "46": {
+ "desc": "Firmware initiated channel fail"
+ },
+ "47:48": {
"desc": "reserved"
}
},
diff --git a/chip_data/odyssey/node_tlx_fir.json b/chip_data/odyssey/node_tlx_fir.json
index a9fde05..7ae6bc8 100644
--- a/chip_data/odyssey/node_tlx_fir.json
+++ b/chip_data/odyssey/node_tlx_fir.json
@@ -7,11 +7,23 @@
"0": "0x08012000"
}
},
+ "TLX_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012001"
+ }
+ },
"TLX_FIR_MASK": {
"instances": {
"0": "0x08012002"
}
},
+ "TLX_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x08012003"
+ }
+ },
"TLX_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x08012004"
@@ -179,6 +191,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "Internal parity error"
diff --git a/chip_data/odyssey/node_tp_local_fir.json b/chip_data/odyssey/node_tp_local_fir.json
index a0b98e2..be54371 100644
--- a/chip_data/odyssey/node_tp_local_fir.json
+++ b/chip_data/odyssey/node_tp_local_fir.json
@@ -7,11 +7,23 @@
"0": "0x01040100"
}
},
+ "TP_LOCAL_FIR_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040101"
+ }
+ },
"TP_LOCAL_FIR_MASK": {
"instances": {
"0": "0x01040102"
}
},
+ "TP_LOCAL_FIR_MASK_OR": {
+ "access": "WO",
+ "instances": {
+ "0": "0x01040103"
+ }
+ },
"TP_LOCAL_FIR_CFG_CHIP_CS": {
"instances": {
"0": "0x01040104"
@@ -121,6 +133,16 @@
"instances": {
"0": "0x000D001B"
}
+ },
+ "SPICTL0_ERROR_INJECT": {
+ "instances": {
+ "0": "0x00070000"
+ }
+ },
+ "SPICTL0_STATUS_REG": {
+ "instances": {
+ "0": "0x00070008"
+ }
}
},
"isolation_nodes": {
@@ -224,6 +246,24 @@
}
}
],
+ "op_rules": {
+ "FIR_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_OR"
+ },
+ "FIR_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ "MASK_SET": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_MASK_OR"
+ },
+ "MASK_CLEAR": {
+ "op_rule": "atomic_or",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
"bits": {
"0": {
"desc": "CFIR/LFIR parity error"
@@ -232,19 +272,59 @@
"desc": "CPLT_CTRL - PCB access error"
},
"2": {
- "desc": "CC - PCB access error"
+ "desc": "CC - PCB access error",
+ "capture_groups": [
+ {
+ "group_name": "TP_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"3": {
- "desc": "CC - clock control error"
+ "desc": "CC - clock control error",
+ "capture_groups": [
+ {
+ "group_name": "TP_ERR_STATUS_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"4": {
- "desc": "PSC - PSCOM Access Error"
+ "desc": "PSC - PSCOM Access Error",
+ "capture_groups": [
+ {
+ "group_name": "TP_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"5": {
- "desc": "PSC - internal or ring interface error"
+ "desc": "PSC - internal or ring interface error",
+ "capture_groups": [
+ {
+ "group_name": "TP_PSCOM_STATUS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"6": {
- "desc": "THERM - various errors"
+ "desc": "THERM - various errors",
+ "capture_groups": [
+ {
+ "group_name": "TP_DTS_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"7": {
"desc": "DBG - SCOM parity fail"
@@ -259,16 +339,40 @@
"desc": "Trace00 - SCOM parity error"
},
"11": {
- "desc": "ITR - FMU error"
+ "desc": "ITR - FMU error",
+ "capture_groups": [
+ {
+ "group_name": "TP_FMU_ERR_RPT_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"12": {
"desc": "ITR - PCB error"
},
"13": {
- "desc": "PCB master - timeout"
+ "desc": "PCB master - timeout",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"14": {
- "desc": "I2CM - parity errors"
+ "desc": "I2CM - parity errors",
+ "capture_groups": [
+ {
+ "group_name": "RESET_REG_B_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"15:17": {
"desc": "unused"
@@ -323,25 +427,65 @@
"desc": "unused"
},
"30": {
- "desc": "PCB controller - multicast group member count underrun"
+ "desc": "PCB controller - multicast group member count underrun",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"31": {
- "desc": "PCB controller - parity error"
+ "desc": "PCB controller - parity error",
+ "capture_groups": [
+ {
+ "group_name": "PCBCTL_ERR_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"32:35": {
"desc": "unused"
},
"36": {
- "desc": "PIB interface - RAM UE ECC error"
+ "desc": "PIB interface - RAM UE ECC error",
+ "capture_groups": [
+ {
+ "group_name": "PPE_PIBMEM_STATUS_REG_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"37": {
- "desc": "Direct interface to PIBMEM - RAM UE ECC error"
+ "desc": "Direct interface to PIBMEM - RAM UE ECC error",
+ "capture_groups": [
+ {
+ "group_name": "PPE_PIBMEM_STATUS_REG_CG",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"38:44": {
"desc": "unused"
},
"45": {
- "desc": "SPI controller 0 error"
+ "desc": "SPI controller 0 error",
+ "capture_groups": [
+ {
+ "group_name": "SPI_CONTROLLER",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
},
"46:62": {
"desc": "unused"
@@ -349,49 +493,51 @@
"63": {
"desc": "external local checkstop"
}
- },
- "capture_groups": [
- {
- "group_name": "TP_LOCAL_FIR",
- "group_inst": {
- "0": 0
- }
- }
- ]
+ }
}
},
"capture_groups": {
- "TP_LOCAL_FIR": [
- {
- "reg_name": "TP_ERR_STATUS",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_PSCOM_STATUS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_DTS_ERR",
- "reg_inst": {
- "0": 0
- }
- },
- {
- "reg_name": "TP_FMU_ERR_RPT",
- "reg_inst": {
- "0": 0
- }
- },
+ "PCBCTL_ERR_CG": [
{
"reg_name": "PCBCTL_ERR",
"reg_inst": {
"0": 0
}
- },
+ }
+ ],
+ "TP_FMU_ERR_RPT_CG": [
+ {
+ "reg_name": "TP_FMU_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_DTS_ERR_CG": [
+ {
+ "reg_name": "TP_DTS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_PSCOM_STATUS_ERR_CG": [
+ {
+ "reg_name": "TP_PSCOM_STATUS_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "TP_ERR_STATUS_CG": [
+ {
+ "reg_name": "TP_ERR_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "RESET_REG_B_CG": [
{
"reg_name": "RESET_REG_B",
"reg_inst": {
@@ -399,6 +545,28 @@
}
}
],
+ "SPI_CONTROLLER": [
+ {
+ "reg_name": "SPICTL0_ERROR_INJECT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SPICTL0_STATUS_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PPE_PIBMEM_STATUS_REG_CG": [
+ {
+ "reg_name": "PPE_PIBMEM_STATUS_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
"SPPE_HW_ERROR": [
{
"reg_name": "PPE_XIRAMDBG",