diff --git a/xml/p10/node_int_cq_fir.xml b/xml/p10/node_int_cq_fir.xml
index 1b2aa69..abba027 100644
--- a/xml/p10/node_int_cq_fir.xml
+++ b/xml/p10/node_int_cq_fir.xml
@@ -6,17 +6,135 @@
         <action attn_type="RE" config="01"/>
         <action attn_type="SPA" config="10"/>
     </local_fir>
-    <bit pos="0">Correctable ECC error detected while consuming data from the PowerBus Data ramp.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="1">Uncorrectable ECC error detected while consuming data from the PowerBus Data ramp.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="2">Special uncorrectable ECC error detected while consuming data on the PowerBus Data ramp for a Master DMA Read or Master CI Read.</bit>
-    <bit pos="3">Correctable ECC error detected while reading the PowerBus Data In Array. See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="4">Uncorrectable ECC error detected while reading the PowerBus Data In Array.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="5">Correctable ECC error detected while reading the PowerBus Data Out  Array. See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="6">Uncorrectable ECC error detected while reading the PowerBus Data Out Array.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="7">Correctable ECC error detected while consuming data on the AIB Data Bus.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="8">Uncorrectable ECC error detected while consuming data on the AIB Data Bus.  See INT_CQ_ERR_INFO2 for details.</bit>
-    <bit pos="9">Received an unsolicited master Combined Response - The master cResp tTag(0:11) matched my topology ID and unit ID, but tTag(12:19) pointed to TxIDs</bit>
-    <bit pos="10">Received unsolicited PowerBus data - The rTag(0:11) of incoming PB data matched my topology ID and unit ID, but rTag(12:19) pointed to TxIDs that</bit>
+    <register name="INT_CQ_ERR_RPT_HOLD">
+        <instance addr="0x02010839" reg_inst="0"/>
+    </register>
+    <register name="INT_CQ_ERR_INFO1">
+        <instance addr="0x0201083B" reg_inst="0"/>
+    </register>
+    <register name="INT_CQ_ERR_INFO2">
+        <instance addr="0x0201083C" reg_inst="0"/>
+    </register>
+    <register name="INT_CQ_ERR_INFO3">
+        <instance addr="0x0201083D" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR0_WOF">
+        <instance addr="0x02010AC2" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR0_WOF_DETAIL">
+        <instance addr="0x02010AC3" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR0_FATAL">
+        <instance addr="0x02010AC4" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR0_RECOV">
+        <instance addr="0x02010AC5" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR0_INFO">
+        <instance addr="0x02010AC6" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR1_WOF">
+        <instance addr="0x02010ACA" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR1_WOF_DETAIL">
+        <instance addr="0x02010ACB" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR1_FATAL">
+        <instance addr="0x02010ACC" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR1_RECOV">
+        <instance addr="0x02010ACD" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_ERR1_INFO">
+        <instance addr="0x02010ACE" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_NXC_WOF_ERR">
+        <instance addr="0x02010AD2" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_NXC_WOF_ERR_DETAIL">
+        <instance addr="0x02010AD3" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_NXC_FATAL_ERR">
+        <instance addr="0x02010AD4" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_NXC_RECOV_ERR">
+        <instance addr="0x02010AD5" reg_inst="0"/>
+    </register>
+    <register name="INT_PC_NXC_INFO_ERR">
+        <instance addr="0x02010AD6" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_WOF_ERR_G0">
+        <instance addr="0x020109C2" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_WOF_ERR_G0_DETAIL">
+        <instance addr="0x020109C3" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_FATAL_ERR_G0">
+        <instance addr="0x020109C4" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_RECOV_ERR_G0">
+        <instance addr="0x020109C5" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_INFO_ERR_G0">
+        <instance addr="0x020109C6" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_WOF_ERR_G1">
+        <instance addr="0x020109CA" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_WOF_ERR_G1_DETAIL">
+        <instance addr="0x020109CB" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_FATAL_ERR_G1">
+        <instance addr="0x020109CC" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_RECOV_ERR_G1">
+        <instance addr="0x020109CD" reg_inst="0"/>
+    </register>
+    <register name="INT_VC_INFO_ERR_G1">
+        <instance addr="0x020109CE" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="INT_CQ_ERR_RPT_HOLD" />
+        <capture_register reg_inst="0" reg_name="INT_CQ_ERR_INFO1" />
+        <capture_register reg_inst="0" reg_name="INT_CQ_ERR_INFO2" />
+        <capture_register reg_inst="0" reg_name="INT_CQ_ERR_INFO3" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR0_WOF" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR0_WOF_DETAIL" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR0_FATAL" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR0_RECOV" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR0_INFO" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR1_WOF" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR1_WOF_DETAIL" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR1_FATAL" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR1_RECOV" />
+        <capture_register reg_inst="0" reg_name="INT_PC_ERR1_INFO" />
+        <capture_register reg_inst="0" reg_name="INT_PC_NXC_WOF_ERR" />
+        <capture_register reg_inst="0" reg_name="INT_PC_NXC_WOF_ERR_DETAIL" />
+        <capture_register reg_inst="0" reg_name="INT_PC_NXC_FATAL_ERR" />
+        <capture_register reg_inst="0" reg_name="INT_PC_NXC_RECOV_ERR" />
+        <capture_register reg_inst="0" reg_name="INT_PC_NXC_INFO_ERR" />
+        <capture_register reg_inst="0" reg_name="INT_VC_WOF_ERR_G0" />
+        <capture_register reg_inst="0" reg_name="INT_VC_WOF_ERR_G0_DETAIL" />
+        <capture_register reg_inst="0" reg_name="INT_VC_FATAL_ERR_G0" />
+        <capture_register reg_inst="0" reg_name="INT_VC_RECOV_ERR_G0" />
+        <capture_register reg_inst="0" reg_name="INT_VC_INFO_ERR_G0" />
+        <capture_register reg_inst="0" reg_name="INT_VC_WOF_ERR_G1" />
+        <capture_register reg_inst="0" reg_name="INT_VC_WOF_ERR_G1_DETAIL" />
+        <capture_register reg_inst="0" reg_name="INT_VC_FATAL_ERR_G1" />
+        <capture_register reg_inst="0" reg_name="INT_VC_RECOV_ERR_G1" />
+        <capture_register reg_inst="0" reg_name="INT_VC_INFO_ERR_G1" />
+    </capture_group>
+    <bit pos="0">CE while consuming data from the PowerBus Data ramp</bit>
+    <bit pos="1">UE while consuming data from the PowerBus Data ramp</bit>
+    <bit pos="2">SUE while consuming data from the PowerBus Data ramp</bit>
+    <bit pos="3">CE while reading the PowerBus Data In Array</bit>
+    <bit pos="4">UE detected while reading the PowerBus Data In Array</bit>
+    <bit pos="5">CE while reading the PowerBus Data Out Array</bit>
+    <bit pos="6">UE while reading the PowerBus Data Out Array</bit>
+    <bit pos="7">CE while consuming data on the AIB Data Bus</bit>
+    <bit pos="8">UE while consuming data on the AIB Data Bus</bit>
+    <bit pos="9">Received an unsolicited master Combined Response</bit>
+    <bit pos="10">Received unsolicited PowerBus data</bit>
     <bit pos="11">Parity error detected on AIB credit signals from PC</bit>
     <bit pos="12">Parity error detected on AIB credit available signals from PC</bit>
     <bit pos="13">Parity error detected on AIB credit signals from VC</bit>
@@ -24,31 +142,31 @@
     <bit pos="15">Parity error detected on AIB Command Control</bit>
     <bit pos="16">Parity error detected on AIB Command Bus</bit>
     <bit pos="17">Parity error detected on AIB Data Control</bit>
-    <bit pos="18">Parity error detected on one of the following PowerBus interfaces (Rcmdx, cRespx, Data rtag).  See INT_CQ_ERR_INFO0 for details.</bit>
-    <bit pos="19">Slave CI Store or CI Load to an improper location.  This includes a Read targeting a WO space, a Write targeting a RO space, or targeting reserved</bit>
-    <bit pos="20">Slave CI Store or CI Load to an invalid Set Translation Table entry (that are associated with the NVPG, NVC, ESB and END BARs).</bit>
-    <bit pos="21">Slave CI Store or CI Load (that targets the IC_BAR) with a size violation, alignment problem, or comes from an unsupported source.</bit>
-    <bit pos="22">Slave CI Store or CI Load (that does not target the IC_BAR) with a size violation, alignment problem or comes from an unsupported source.</bit>
-    <bit pos="23">Migration Register Table (MRT) access - invalid entry selected.</bit>
-    <bit pos="24">Migration Register Table (MRT) access - The Table Size received in the AIB command is greater than the Target Page Size in the MRT entry.</bit>
+    <bit pos="18">Parity err detected in a PowerBus interface(Rcmdx, cRespx, Data rtag)</bit>
+    <bit pos="19">Slave CI Store or CI Load to an improper location</bit>
+    <bit pos="20">Slave CI Store or CI Load to an invalid Set Translation Table entry</bit>
+    <bit pos="21">Slave CI Store or CI Load error (targeting IC_BAR)</bit>
+    <bit pos="22">Slave CI Store or CI Load error (not targetting IC_BAR)</bit>
+    <bit pos="23">Migration Register Table (MRT) access - invalid entry selected</bit>
+    <bit pos="24">Migration Register Table (MRT) access - size error</bit>
     <bit pos="25">SCOM satellite error</bit>
-    <bit pos="26">Topology ID Index Translation Table Entry Invalid - When INT initiates a master op (Read or Write) on the PowerBus, in determining the initial</bit>
+    <bit pos="26">Topology ID Index Translation Table Entry Invalid</bit>
     <bit pos="27">Master Write Queue has flagged a PowerBus operational hang</bit>
     <bit pos="28">Master Read Queue has flagged a PowerBus operational hang</bit>
     <bit pos="29">Master Interrupt Queue has flagged a PowerBus operational hang</bit>
     <bit pos="30">Master Read Queue has flagged a PowerBus data hang</bit>
     <bit pos="31">CI Store Queue has flagged a PowerBus data hang</bit>
-    <bit pos="32">CI Load Queue has flagged an AIB data hang - Once a CI Load request has been sent on AIB, I use the PowerBus data hang timer mechanism (the</bit>
-    <bit pos="33">Bad cResp received during a Master Write command.</bit>
-    <bit pos="34">Bad cResp received during a Master Read command.</bit>
-    <bit pos="35">Bad cResp received during a Master Interrupt command.</bit>
-    <bit pos="36">A Master Read machine received cResp of abort_trm or abort_trm_ed. In addition to setting this error bit, the Read machine behaved as if the cResp was</bit>
-    <bit pos="37">Master Interrupt Protocol Error - The PowerBus cResp to a master interrupt command was a response that should never happen.  In the P10 INT Workbook,</bit>
-    <bit pos="38">Master Memory Op Targeted Secure Memory - VC or PC sent CQ a memory operation with the secure RA bit (bit 12) = 1 while SMF is enabled.</bit>
-    <bit pos="39">AIB Fence Raised - This bit is set whenever CQ, PC, or VC assert &quot;AIB Fence&quot;.  This bit is useful to know if AIB fence was raised before another FIR</bit>
-    <bit pos="40">Parity error detected on CQs configuration registers.</bit>
-    <bit pos="41">Reserved</bit>
-    <bit pos="42">Command Queue (FSM) severe error summary.  See INT_CQ_ERR_INFO3 for details.  This includes queue overflows and FSM parity errors.</bit>
+    <bit pos="32">CI Load Queue has flagged an AIB data hang</bit>
+    <bit pos="33">Bad cResp received during a Master Write command</bit>
+    <bit pos="34">Bad cResp received during a Master Read command</bit>
+    <bit pos="35">Bad cResp received during a Master Interrupt command</bit>
+    <bit pos="36">A Master Read machine received cResp of abort_trm or abort_trm_ed</bit>
+    <bit pos="37">Master Interrupt Protocol Error</bit>
+    <bit pos="38">Master Memory Op Targeted Secure Memory</bit>
+    <bit pos="39">AIB Fence Raised</bit>
+    <bit pos="40">Parity error detected on CQs configuration registers</bit>
+    <bit pos="41">reserved</bit>
+    <bit pos="42">Command Queue (FSM) severe error summary</bit>
     <bit pos="43">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
     <bit pos="44">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
     <bit pos="45">PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)</bit>
diff --git a/xml/p10/node_nx_cq_fir.xml b/xml/p10/node_nx_cq_fir.xml
index d6c70ef..f54716f 100644
--- a/xml/p10/node_nx_cq_fir.xml
+++ b/xml/p10/node_nx_cq_fir.xml
@@ -6,6 +6,16 @@
         <action attn_type="RE" config="01"/>
         <action attn_type="UCS" config="11"/>
     </local_fir>
+    <register name="NX_CQ_ERR_RPT_0">
+        <instance addr="0x020110A2" reg_inst="0"/>
+    </register>
+    <register name="NX_CQ_ERR_RPT_1">
+        <instance addr="0x020110A1" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="NX_CQ_ERR_RPT_0" />
+        <capture_register reg_inst="0" reg_name="NX_CQ_ERR_RPT_1" />
+    </capture_group>
     <bit pos="0">PBI internal parity error</bit>
     <bit pos="1">PowerBus CE error</bit>
     <bit pos="2">PowerBus UE error</bit>
diff --git a/xml/p10/node_nx_dma_eng_fir.xml b/xml/p10/node_nx_dma_eng_fir.xml
index 5733a80..2e6b10e 100644
--- a/xml/p10/node_nx_dma_eng_fir.xml
+++ b/xml/p10/node_nx_dma_eng_fir.xml
@@ -6,52 +6,62 @@
         <action attn_type="RE" config="01"/>
         <action attn_type="UCS" config="11"/>
     </local_fir>
-    <bit pos="0">DMA Hang Timer FIR bit</bit>
-    <bit pos="1">SHM invalid state error FIR bit</bit>
-    <bit pos="2">Reserved FIR bit 2</bit>
-    <bit pos="3">Reserved FIR bit 3</bit>
-    <bit pos="4">Channel 0 842 array corrected ECC error FIR bit</bit>
-    <bit pos="5">Channel 0 842 array uncorrectable ECC error FIR bit</bit>
-    <bit pos="6">Channel 1 842 array corrected ECC error FIR bit</bit>
-    <bit pos="7">Channel 1 842 array uncorrectable ECC error FIR bit</bit>
-    <bit pos="8">DMA non-zero CSB CC detected FIR bit. Lab use only. Masked.</bit>
-    <bit pos="9">DMA array correctable ECC error FIR bit</bit>
-    <bit pos="10">DMA outbound write/inbound read correctable ECC error FIR bit</bit>
-    <bit pos="11">Channel 4 Gzip array corrected ECC error FIR bit</bit>
-    <bit pos="12">Channel 4 Gzip array corrected ECC error FIR bit</bit>
-    <bit pos="13">Channel 4 Gzip array parity error FIR bit</bit>
-    <bit pos="14">Error from other SCOM satellites FIR bit</bit>
-    <bit pos="15">DMA invalid state error FIR bit</bit>
-    <bit pos="16">DMA invalid state error FIR bit. Unrecoverable despite name</bit>
-    <bit pos="17">DMA array uncorrectable ECC error FIR bit</bit>
-    <bit pos="18">DMA outbound write/inbound read uncorrectable ECC error FIR bit</bit>
-    <bit pos="19">DMA inbound read error FIR bit</bit>
-    <bit pos="20">Channel 0 842 invalid state error FIR bit</bit>
-    <bit pos="21">Channel 1 842 invalid state error FIR bit</bit>
-    <bit pos="22">Channel 2 SYM invalid state error FIR bit</bit>
-    <bit pos="23">Channel 3 SYMinvalid state error FIR bit</bit>
-    <bit pos="24">Channel 4 Gzip invalid state error FIR bit</bit>
-    <bit pos="25">Reserved FIR bit 25</bit>
-    <bit pos="26">Reserved FIR bit 26</bit>
-    <bit pos="27">Reserved FIR bit 27</bit>
-    <bit pos="28">Reserved FIR bit 28</bit>
-    <bit pos="29">Reserved FIR bit 29</bit>
-    <bit pos="30">Reserved FIR bit 30</bit>
-    <bit pos="31">UE error on CRB QW0 or QW4 FIR bit</bit>
-    <bit pos="32">SUE error on CRB QW0 or QW4 FIR bit</bit>
-    <bit pos="33">SUE error on something other than CRB QW0 or QW4 FIR bit</bit>
-    <bit pos="34">Channel 0 842 watchdog timer expired FIR bit</bit>
-    <bit pos="35">Channel 1 842 watchdog timer expired FIR bit</bit>
-    <bit pos="36">Channel 2 SYM watchdog timer expired FIR bit</bit>
-    <bit pos="37">Channel 3 SYM watchdog timer expired FIR bit</bit>
-    <bit pos="38">Reserved FIR bit 38. Hypervisor can use to signal local xstop to FSP.</bit>
-    <bit pos="39">Channel 4 Gzip watchdog timer expired FIR bit</bit>
-    <bit pos="40">Reserved FIR bit 40</bit>
-    <bit pos="41">Reserved FIR bit 41</bit>
-    <bit pos="42">Reserved FIR bit 42</bit>
-    <bit pos="43">Reserved FIR bit 43</bit>
-    <bit pos="44">Reserved FIR bit 44</bit>
-    <bit pos="45">Reserved FIR bit 45</bit>
-    <bit pos="46">Reserved FIR bit 46</bit>
-    <bit pos="47">Reserved FIR bit 47</bit>
+    <register name="SU_DMA_ERROR_REPORT_0">
+        <instance addr="0x02011057" reg_inst="0"/>
+    </register>
+    <register name="SU_DMA_ERROR_REPORT_1">
+        <instance addr="0x02011058" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="SU_DMA_ERROR_REPORT_0" />
+        <capture_register reg_inst="0" reg_name="SU_DMA_ERROR_REPORT_1" />
+    </capture_group>
+    <bit pos="0">DMA hang timer expired</bit>
+    <bit pos="1">SHM invalid state</bit>
+    <bit pos="2">reserved</bit>
+    <bit pos="3">reserved</bit>
+    <bit pos="4">Channel 0 842 engine ECC CE</bit>
+    <bit pos="5">Channel 0 842 engine ECC UE</bit>
+    <bit pos="6">Channel 1 842 engine ECC CE</bit>
+    <bit pos="7">Channel 1 842 engine ECC UE</bit>
+    <bit pos="8">DMA Non-zero CSB CC detected</bit>
+    <bit pos="9">DMA array ECC CE</bit>
+    <bit pos="10">DMA outbound write/inbound read ECC CE</bit>
+    <bit pos="11">Channel 4 GZIP ECC CE</bit>
+    <bit pos="12">Channel 4 GZIP ECC UE</bit>
+    <bit pos="13">Channel 4 GZIP ECC PE</bit>
+    <bit pos="14">Error from other SCOM satellites</bit>
+    <bit pos="15">DMA invalid state error (unrecoverable)</bit>
+    <bit pos="16">DMA invalid state error (unrecoverable)</bit>
+    <bit pos="17">DMA array ECC UE</bit>
+    <bit pos="18">DMA outbound write/inbound read ECC UE</bit>
+    <bit pos="19">DMA inbound read error</bit>
+    <bit pos="20">Channel 0 842 invalid state error</bit>
+    <bit pos="21">Channel 1 842 invalid state error</bit>
+    <bit pos="22">Channel 2 SYM invalid state error</bit>
+    <bit pos="23">Channel 3 SYM invalid state error</bit>
+    <bit pos="24">Channel 4 GZIP invalid state error</bit>
+    <bit pos="25">reserved</bit>
+    <bit pos="26">reserved</bit>
+    <bit pos="27">reserved</bit>
+    <bit pos="28">reserved</bit>
+    <bit pos="29">reserved</bit>
+    <bit pos="30">reserved</bit>
+    <bit pos="31">UE error on CRB QW0 or QW4</bit>
+    <bit pos="32">SUE error on CRB QW0 or QW4</bit>
+    <bit pos="33">SUE error on something other than CRB QW0 or QW4</bit>
+    <bit pos="34">Channel 0 842 watchdog timer expired</bit>
+    <bit pos="35">Channel 1 842 watchdog timer expired</bit>
+    <bit pos="36">Channel 2 SYM watchdog timer expired</bit>
+    <bit pos="37">Channel 3 SYM watchdog timer expired</bit>
+    <bit pos="38">Hypervisor local checkstop</bit>
+    <bit pos="39">Channel 4 Gzip watchdog timer expired</bit>
+    <bit pos="40">reserved</bit>
+    <bit pos="41">reserved</bit>
+    <bit pos="42">reserved</bit>
+    <bit pos="43">reserved</bit>
+    <bit pos="44">reserved</bit>
+    <bit pos="45">reserved</bit>
+    <bit pos="46">reserved</bit>
+    <bit pos="47">reserved</bit>
 </attn_node>
diff --git a/xml/p10/node_occ_fir.xml b/xml/p10/node_occ_fir.xml
index 769f09a..0e6df35 100644
--- a/xml/p10/node_occ_fir.xml
+++ b/xml/p10/node_occ_fir.xml
@@ -5,10 +5,20 @@
         <action attn_type="CS" config="00"/>
         <action attn_type="RE" config="01"/>
     </local_fir>
-    <bit pos="0">Input tied to 0.  Used by OCC Firmware to produce an attention to the FSP.</bit>
-    <bit pos="1">Input tied to 0.  Used by OCC Firmware to produce an attention tothe FSP.</bit>
-    <bit pos="2">Input tied to 0. Used by STOP GPE code to indicated to HYP that a QME has indicated a fault.</bit>
-    <bit pos="3">Input tied to 0.   Written by stop recovery firmware to indicate that the host side actions are complete and that FFDC information is available for</bit>
+    <register name="OCC_SCOM_ERR_RPT">
+        <instance addr="0x0101080A" reg_inst="0"/>
+    </register>
+    <register name="OCC_SCOM_ERR_RPT2">
+        <instance addr="0x0101080B" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="OCC_SCOM_ERR_RPT" />
+        <capture_register reg_inst="0" reg_name="OCC_SCOM_ERR_RPT2" />
+    </capture_group>
+    <bit pos="0">OCC_FW0</bit>
+    <bit pos="1">OCC_FW1</bit>
+    <bit pos="2">OCC_QME_ERROR_NOTIFY</bit>
+    <bit pos="3">reserved</bit>
     <bit pos="4">OCC Heartbeat Error</bit>
     <bit pos="5">GPE0 asserted a watchdog timeout condition</bit>
     <bit pos="6">GPE1 asserted a watchdog timeout condition</bit>
@@ -18,9 +28,9 @@
     <bit pos="10">GPE1 asserted an error condition that caused it to halt.</bit>
     <bit pos="11">GPE2 asserted an error condition that caused it to halt.</bit>
     <bit pos="12">GPE3 asserted an error condition that caused it to halt.</bit>
-    <bit pos="13">OCB Error (recoverable error)</bit>
-    <bit pos="14">SRAM Uncorrectable Error (recoverable error)</bit>
-    <bit pos="15">SRAM Correctable Error (masked (product); recoverable error (mfg)</bit>
+    <bit pos="13">OCB Error to PM Hcode for PM Complex Restart</bit>
+    <bit pos="14">SRAM UE to PM Hcode for PM Complex Restart</bit>
+    <bit pos="15">SRAM CE</bit>
     <bit pos="16">GPE0 asserted a halt condition</bit>
     <bit pos="17">GPE1 asserted a halt condition</bit>
     <bit pos="18">GPE2 asserted a halt condition</bit>
@@ -29,42 +39,42 @@
     <bit pos="21">GPE1 attempted to write outside the region defined in GPESWPR</bit>
     <bit pos="22">GPE2 attempted to write outside the region defined in GPESWPR</bit>
     <bit pos="23">GPE3 attempted to write outside the region defined in GPESWPR</bit>
-    <bit pos="24">Implemented but not used, inputs tied to 0</bit>
-    <bit pos="25">Implemented but not used, inputs tied to 0</bit>
-    <bit pos="26">External Trigger pin active (recoverable (product)</bit>
-    <bit pos="27">PPC405 Core Reset Output asserted (??? firmware)</bit>
-    <bit pos="28">PPC405 Chip Reset Output asserted (??? firmware)</bit>
-    <bit pos="29">PPC405 System Reset Output asserted (??? firmware)</bit>
-    <bit pos="30">PPC405 Wait State asserted (??? firmware)</bit>
-    <bit pos="31">PPC405 Stop Ack output asserted (recoverable -&gt; logging)</bit>
-    <bit pos="32">OCB Direct Bridge Error - See OCCERRRPT2[8:11] for error source</bit>
-    <bit pos="33">OCB PIB Address Parity Error - (PIB read or write operation).  Note:  may be set for either direct bridge or indirect channel operations.</bit>
+    <bit pos="24">Safe Mode for debug use</bit>
+    <bit pos="25">reserved</bit>
+    <bit pos="26">EXTERNAL_TRAP</bit>
+    <bit pos="27">PPC405 Core Reset Output asserted (OCC firmware)</bit>
+    <bit pos="28">PPC405 Chip Reset Output asserted (OCC firmware)</bit>
+    <bit pos="29">PPC405 System Reset Output asserted (OCC firmware)</bit>
+    <bit pos="30">PPC405 Wait State asserted (OCC firmware)</bit>
+    <bit pos="31">PPC405 Stop Ack output asserted</bit>
+    <bit pos="32">OCB Direct Bridge Error</bit>
+    <bit pos="33">OCB PIB Address Parity Error</bit>
     <bit pos="34">Indirect Channel Error</bit>
-    <bit pos="35">Parity error detected on OPIT interrupt bus. Interrupts are hung.</bit>
-    <bit pos="36">OPIT interrupt state machine error occurred.</bit>
-    <bit pos="37">Implemented but not used.  Input tied to 0</bit>
-    <bit pos="38">Implemented but not used.  Input tied to 0</bit>
-    <bit pos="39">Implemented but not used.  Input tied to 0</bit>
-    <bit pos="40">Implemented but not used.  Input tied to 0</bit>
-    <bit pos="41">Implemented but not used.  Input tied to 0</bit>
+    <bit pos="35">Parity error detected on OPIT interrupt bus</bit>
+    <bit pos="36">OPIT interrupt state machine error occurred</bit>
+    <bit pos="37">reserved</bit>
+    <bit pos="38">reserved</bit>
+    <bit pos="39">reserved</bit>
+    <bit pos="40">reserved</bit>
+    <bit pos="41">reserved</bit>
     <bit pos="42">JTAG accelerator error</bit>
     <bit pos="43">Any OCI Slave error occurreds</bit>
     <bit pos="44">PPC405 cache UE</bit>
     <bit pos="45">PPC405 cache CE</bit>
     <bit pos="46">PPC405 Machine Check</bit>
-    <bit pos="47">SRAM spare direct error Summary.  See OCCERRRPT2[0:3] for details</bit>
-    <bit pos="48">SRAM Controller Error - A read, write, or parity error occurred in the  SRAM tank controller.   See OCCERRRPT2[12:18] for more information</bit>
-    <bit pos="49">Implemented but notused.   Input tied to 0</bit>
-    <bit pos="50">Implemented but notused.   Input tied to 0</bit>
-    <bit pos="51">OCI slave error for GPE0 (see OCCERRPT for details)</bit>
-    <bit pos="52">OCI slave error for GPE1 (see OCCERRPT for details)</bit>
-    <bit pos="53">OCI slave error for GPE2 (see OCCERRPT for details)</bit>
-    <bit pos="54">OCI slave error for GPE3 (see OCCERRPT for details)</bit>
-    <bit pos="55">PPC405 ICU timeout on OCI  request</bit>
-    <bit pos="56">PPC405 DCU timeout on OCI  request</bit>
-    <bit pos="57">Used by OCC to indicate that a fault occurred (to achieve safe mode).  Connected to OCCMISC[firmware_fault].</bit>
-    <bit pos="58">Used by OCC to notify another firmware entity that an event occurred.  Connected to OCCMISC[firmware_notify].</bit>
-    <bit pos="59">Implemented but not used.  Inputs tied to 0.</bit>
-    <bit pos="60">Implemented but not used.  Inputs tied to 0.</bit>
-    <bit pos="61">Implemented but not used.  Inputs tied to 0.</bit>
+    <bit pos="47">SRAM spare direct error Summary</bit>
+    <bit pos="48">Read, write, or parity error in the SRAM tank controller</bit>
+    <bit pos="49">reserved</bit>
+    <bit pos="50">reserved</bit>
+    <bit pos="51">OCI slave error for GPE0</bit>
+    <bit pos="52">OCI slave error for GPE1</bit>
+    <bit pos="53">OCI slave error for GPE2</bit>
+    <bit pos="54">OCI slave error for GPE3</bit>
+    <bit pos="55">PPC405 ICU timeout on OCI request</bit>
+    <bit pos="56">PPC405 DCU timeout on OCI request</bit>
+    <bit pos="57">OCC fault occurred (to achieve safe mode)</bit>
+    <bit pos="58">Read by HYP as part of the communication of a Power Management fault</bit>
+    <bit pos="59">reserved</bit>
+    <bit pos="60">reserved</bit>
+    <bit pos="61">reserved</bit>
 </attn_node>
diff --git a/xml/p10/node_pbao_fir.xml b/xml/p10/node_pbao_fir.xml
index 3753302..e2468e5 100644
--- a/xml/p10/node_pbao_fir.xml
+++ b/xml/p10/node_pbao_fir.xml
@@ -5,24 +5,34 @@
         <action attn_type="CS" config="00"/>
         <action attn_type="RE" config="01"/>
     </local_fir>
+    <register name="PBAO_ERR_RPT_1">
+        <instance addr="0x01010CCD" reg_inst="0"/>
+    </register>
+    <register name="PBAO_ERR_RPT_2">
+        <instance addr="0x01010CCE" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="PBAO_ERR_RPT_1" />
+        <capture_register reg_inst="0" reg_name="PBAO_ERR_RPT_2" />
+    </capture_group>
     <bit pos="0">OCI Address Parity Error Det</bit>
     <bit pos="1">PBA OCI Slave Initialization Error</bit>
     <bit pos="2">OCI Write Data Parity Error Detected</bit>
-    <bit pos="3">Spare -was OCI Re-Request Timeout</bit>
+    <bit pos="3">spare</bit>
     <bit pos="4">BCUE Setup Error</bit>
     <bit pos="5">BCUE Read Data Parity Error OR MRDERR Asserted</bit>
     <bit pos="6">BCDE Setup Error</bit>
     <bit pos="7">BCDE Write Data error indicated by OCI Slave</bit>
-    <bit pos="8">Internal Logic Error.  See PBAERRRPT2 for more detailed information.</bit>
-    <bit pos="9">Illegal access to OCI Register. Invalid address, read to write-only, write to read-only.</bit>
-    <bit pos="10">Push Write Error. Push queue did not get OCI ADDRACK for push write request.  Either the address is invalid or the targeted detected and address</bit>
-    <bit pos="11">Push Write Error. Push queue did not get OCI ADDRACK for push write request.  Either the address is invalid or the targeted detected and address</bit>
-    <bit pos="12">Illegal PBAX Flow.  See PBAERRRPT2 for more info.</bit>
-    <bit pos="13">Illegal PBAX Flow.  See PBAERRRPT2 for more info.</bit>
-    <bit pos="14">PBAXSND Reservation Error.  Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.</bit>
-    <bit pos="15">PBAXISND Reservation Error.  Reservation request and Reservations not enabled, push queue not enabled, or push queue is full.</bit>
-    <bit pos="16">The htm fifo interface was not able to keep up with the frequency variation between PBAO and PBAF and has overflowed and lost htm trace records.</bit>
-    <bit pos="17">The PBA has been configured to use the PowerBus Topology Translate tables, and the request did not hit a valid entry.</bit>
-    <bit pos="18">Spare</bit>
-    <bit pos="19">Spare</bit>
+    <bit pos="8">Internal Logic Error</bit>
+    <bit pos="9">Illegal access to OCI Register</bit>
+    <bit pos="10">Push Write Error</bit>
+    <bit pos="11">Push Write Error</bit>
+    <bit pos="12">Illegal PBAX Flow</bit>
+    <bit pos="13">Illegal PBAX Flow</bit>
+    <bit pos="14">PBAXSND Reservation Error</bit>
+    <bit pos="15">PBAXISND Reservation Error</bit>
+    <bit pos="16">htm fifo interface fequency variation error</bit>
+    <bit pos="17">Invalide PB topology translate table entry</bit>
+    <bit pos="18">spare</bit>
+    <bit pos="19">spare</bit>
 </attn_node>
diff --git a/xml/p10/node_vas_fir.xml b/xml/p10/node_vas_fir.xml
index d64212d..ce1311e 100644
--- a/xml/p10/node_vas_fir.xml
+++ b/xml/p10/node_vas_fir.xml
@@ -20,7 +20,7 @@
     <bit pos="11">Correctable ECC error detected in WC logic</bit>
     <bit pos="12">Correctable ECC error detected in RG logic</bit>
     <bit pos="13">ECC Correctable Error detected on CQ outbound PowerBus interface</bit>
-    <bit pos="14">ECC UNCorrectable Error detected on CQ outbound PowerBus interface</bit>
+    <bit pos="14">ECC Uncorrectable Error detected on CQ outbound PowerBus interface</bit>
     <bit pos="15">PowerBus state machine hang detected in CQ logic</bit>
     <bit pos="16">Uncorrectable ECC error detected in Egress logic</bit>
     <bit pos="17">Uncorrectable ECC error detected in Ingress logic</bit>
@@ -29,7 +29,7 @@
     <bit pos="20">Uncorrectable ECC error detected in RG logic</bit>
     <bit pos="21">Parity error detected in Ingress logic</bit>
     <bit pos="22">Software cast error detected in Ingress logic</bit>
-    <bit pos="23">VAS attempted to access a memory address which has the secure memory bit set</bit>
+    <bit pos="23">reserved</bit>
     <bit pos="24">ECC sue error detected in Egress logic</bit>
     <bit pos="25">ECC sue error detected in Ingress logic</bit>
     <bit pos="26">ECC sue error detected in CQ logic</bit>
@@ -44,18 +44,18 @@
     <bit pos="35">Address error detected on OS MMIO write</bit>
     <bit pos="36">non-8-Byte MMIO detected by hypervisor</bit>
     <bit pos="37">non-8-Byte MMIO detected by user or OS</bit>
-    <bit pos="38">Unused - Was Write monitor operation attempted on a window that is not open</bit>
-    <bit pos="39">Unused - Was Multiple write monotor registers match the same snooped PB operation</bit>
-    <bit pos="40">Unused - Was Page Migration Register is not valid</bit>
-    <bit pos="41">Unused - Was Page Migration Register size does not match corresponding FIFO</bit>
+    <bit pos="38">reserved</bit>
+    <bit pos="39">reserved</bit>
+    <bit pos="40">reserved</bit>
+    <bit pos="41">reserved</bit>
     <bit pos="42">ASB_Notify sent but not claimed and interrupts were disabled in window context</bit>
-    <bit pos="43">Unused - Was Write monitor operation hit a window which has notification disabled</bit>
-    <bit pos="44">VAS rejected a PB paste command.  See window status register for details</bit>
+    <bit pos="43">reserved</bit>
+    <bit pos="44">VAS rejected a PB paste command</bit>
     <bit pos="45">VAS hung waiting for data from PowerBus</bit>
     <bit pos="46">Incoming PowerBus parity error</bit>
     <bit pos="47">HW error from SCOM Satellite 1</bit>
     <bit pos="48">NX Local Checkstop</bit>
-    <bit pos="49">SCOM MMIO address offset error.  SCOM-initiated MMIO address did not decode to valid address.</bit>
+    <bit pos="49">SCOM MMIO address offset error</bit>
     <bit pos="50">TopoID Error Bit</bit>
-    <bit pos="51">Unused bit</bit>
+    <bit pos="51">spare</bit>
 </attn_node>