diff --git a/test/simulator/testcases/eq_core_fir.cpp b/test/simulator/testcases/eq_core_fir.cpp
new file mode 100644
index 0000000..242d818
--- /dev/null
+++ b/test/simulator/testcases/eq_core_fir.cpp
@@ -0,0 +1,38 @@
+#include "simulator.hpp"
+
+START_TEST_CASE(eq_core_fir)
+
+CHIP(proc0, P10_20)
+
+START_ITERATION
+
+REG_SCOM(proc0, 0x570F001C, 0x0000000001000000) // GFIR_CS
+REG_SCOM(proc0, 0x27040000, 0x8600000000000000) // CFIR_EQ_CS
+REG_SCOM(proc0, 0x27040040, 0x2000000000000000) // CFIR_EQ_CS_MASK
+
+REG_SCOM(proc0, 0x570F001B, 0x0000000001000000) // GFIR_RE
+REG_SCOM(proc0, 0x27040001, 0x8600000000000000) // CFIR_EQ_RE
+
+// Core 28
+REG_SCOM(proc0, 0x27028440, 0x4000002000000008) // EQ_CORE_FIR
+REG_SCOM(proc0, 0x27028443, 0x0221D81A71A8F63A) // EQ_CORE_FIR_MASK
+REG_SCOM(proc0, 0x27028446, 0x14C802408A030048) // EQ_CORE_FIR_ACT0
+REG_SCOM(proc0, 0x27028447, 0xBDDC26C5FE1300CC) // EQ_CORE_FIR_ACT1
+REG_SCOM(proc0, 0x27028448, 0x0000000000000080) // EQ_CORE_FIR_WOF
+
+// Core 29
+REG_SCOM(proc0, 0x27024440, 0x0000000000000009) // EQ_CORE_FIR
+REG_SCOM(proc0, 0x27024443, 0x0221D81A71A8F63A) // EQ_CORE_FIR_MASK
+REG_SCOM(proc0, 0x27024446, 0x14C802408A030048) // EQ_CORE_FIR_ACT0
+REG_SCOM(proc0, 0x27024447, 0xBDDC26C5FE1300CC) // EQ_CORE_FIR_ACT1
+REG_SCOM(proc0, 0x27024448, 0x0000000000000080) // EQ_CORE_FIR_WOF
+
+EXP_SIG(proc0, 0x682c, 28, 1, CHECKSTOP)
+EXP_SIG(proc0, 0x682c, 28, 26, CHECKSTOP)
+EXP_SIG(proc0, 0x682c, 29, 63, CHECKSTOP)
+EXP_SIG(proc0, 0x682c, 28, 56, RECOVERABLE)
+EXP_SIG(proc0, 0x682c, 29, 56, RECOVERABLE)
+
+END_ITERATION
+
+END_TEST_CASE
diff --git a/test/simulator/testcases/meson.build b/test/simulator/testcases/meson.build
index 6aabb36..5d9e306 100644
--- a/test/simulator/testcases/meson.build
+++ b/test/simulator/testcases/meson.build
@@ -1,6 +1,7 @@
 # Test cases
 test_src = files(
     'sample_test_case.cpp',
+    'eq_core_fir.cpp',
     'exp20_foxhound7.cpp',
     'exp20_tlx_err_rpt_1.cpp',
     'omi_dl_fatal.cpp',