diff --git a/test/simulator/chip_data/sample.cdb b/test/simulator/chip_data/sample.cdb
deleted file mode 100644
index 2e36af5..0000000
--- a/test/simulator/chip_data/sample.cdb
+++ /dev/null
Binary files differ
diff --git a/test/simulator/sample_data/chip_sample.xml b/test/simulator/sample_data/chip_sample.xml
new file mode 100644
index 0000000..8b0ca6e
--- /dev/null
+++ b/test/simulator/sample_data/chip_sample.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<chip model_ec="SAMPLE_10" name="Sample">
+    <attn_tree attn_type="CS" node_inst="0" root_node="GFIR"/>
+    <attn_tree attn_type="RE" node_inst="0" root_node="GFIR"/>
+</chip>
diff --git a/test/simulator/sample_data/node_cfir0.xml b/test/simulator/sample_data/node_cfir0.xml
new file mode 100644
index 0000000..67e5707
--- /dev/null
+++ b/test/simulator/sample_data/node_cfir0.xml
@@ -0,0 +1,41 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="CFIR0" reg_type="SCOM">
+    <register name="CFIR0_CS">
+        <instance addr="0x00f00000" reg_inst="0"/>
+        <instance addr="0x00f00010" reg_inst="1"/>
+    </register>
+    <register name="CFIR0_RE">
+        <instance addr="0x00f00001" reg_inst="0"/>
+        <instance addr="0x00f00011" reg_inst="1"/>
+    </register>
+    <register name="CFIR0_MASK">
+        <instance addr="0x00f00002" reg_inst="0"/>
+        <instance addr="0x00f00012" reg_inst="1"/>
+    </register>
+    <capture_group node_inst="0:1">
+        <capture_register reg_inst="0:1" reg_name="CFIR0_CS"/>
+        <capture_register reg_inst="0:1" reg_name="CFIR0_RE"/>
+        <capture_register reg_inst="0:1" reg_name="CFIR0_MASK"/>
+    </capture_group>
+    <rule attn_type="CS" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR0_CS"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR0_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR0_RE"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR0_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="LFIR0" node_inst="0:1" pos="4">Attention on LFIR0</bit>
+    <bit child_node="LFIR1" node_inst="0,2" pos="5">Attention on LFIR1</bit>
+    <bit child_node="LFIR1" node_inst="3,5" pos="6">Attention on LFIR1</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/node_cfir1.xml b/test/simulator/sample_data/node_cfir1.xml
new file mode 100644
index 0000000..9a9cb0e
--- /dev/null
+++ b/test/simulator/sample_data/node_cfir1.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="CFIR1" reg_type="SCOM">
+    <register name="CFIR1_CS">
+        <instance addr="0x00f10000" reg_inst="0"/>
+    </register>
+    <register name="CFIR1_RE">
+        <instance addr="0x00f10001" reg_inst="0"/>
+    </register>
+    <register name="CFIR1_MASK">
+        <instance addr="0x00f10002" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="CFIR1_CS"/>
+        <capture_register reg_inst="0" reg_name="CFIR1_RE"/>
+        <capture_register reg_inst="0" reg_name="CFIR1_MASK"/>
+    </capture_group>
+    <rule attn_type="CS" node_inst="0">
+        <expr type="and">
+            <expr type="reg" value1="CFIR1_CS"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR1_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0">
+        <expr type="and">
+            <expr type="reg" value1="CFIR1_RE"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR1_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="LFIR1" node_inst="1" pos="4">Attention on LFIR1</bit>
+    <bit child_node="LFIR1" node_inst="4" pos="5">Attention on LFIR1</bit>
+    <bit child_node="LFIR2" node_inst="0" pos="6">Attention on LFIR2</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/node_gfir.xml b/test/simulator/sample_data/node_gfir.xml
new file mode 100644
index 0000000..362d903
--- /dev/null
+++ b/test/simulator/sample_data/node_gfir.xml
@@ -0,0 +1,22 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="GFIR" reg_type="SCOM">
+    <register name="GFIR_CS">
+        <instance addr="0xf0000000" reg_inst="0"/>
+    </register>
+    <register name="GFIR_RE">
+        <instance addr="0xf0000001" reg_inst="0"/>
+    </register>
+    <capture_group node_inst="0">
+        <capture_register reg_inst="0" reg_name="GFIR_CS"/>
+        <capture_register reg_inst="0" reg_name="GFIR_RE"/>
+    </capture_group>
+    <rule attn_type="CS" node_inst="0">
+        <expr type="reg" value1="GFIR_CS"/>
+    </rule>
+    <rule attn_type="RE" node_inst="0">
+        <expr type="reg" value1="GFIR_RE"/>
+    </rule>
+    <bit child_node="CFIR0" node_inst="0" pos="0">Attention on CFIR0</bit>
+    <bit child_node="CFIR0" node_inst="1" pos="1">Attention on CFIR1</bit>
+    <bit child_node="CFIR1" node_inst="0" pos="2">Attention on CFIR1</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/node_lfir0.xml b/test/simulator/sample_data/node_lfir0.xml
new file mode 100644
index 0000000..47e00ca
--- /dev/null
+++ b/test/simulator/sample_data/node_lfir0.xml
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="LFIR0" reg_type="SCOM">
+    <local_fir config="" name="LFIR0">
+        <instance addr="0x0000f000" reg_inst="0"/>
+        <instance addr="0x0000f010" reg_inst="1"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+    </local_fir>
+    <bit pos="0">Attention A</bit>
+    <bit pos="1">Attention B</bit>
+    <bit pos="2">Attention C</bit>
+    <bit pos="3">Attention D</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/node_lfir1.xml b/test/simulator/sample_data/node_lfir1.xml
new file mode 100644
index 0000000..ec3db0e
--- /dev/null
+++ b/test/simulator/sample_data/node_lfir1.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="LFIR1" reg_type="SCOM">
+    <local_fir config="W" name="LFIR1">
+        <instance addr="0x0000f100" reg_inst="0"/>
+        <instance addr="0x0000f110" reg_inst="1"/>
+        <instance addr="0x0000f120" reg_inst="2"/>
+        <instance addr="0x0000f130" reg_inst="3"/>
+        <instance addr="0x0000f140" reg_inst="4"/>
+        <instance addr="0x0000f150" reg_inst="5"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+    </local_fir>
+    <bit pos="0">Attention A</bit>
+    <bit pos="1">Attention B</bit>
+    <bit pos="2">Attention C</bit>
+    <bit pos="3">Attention D</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/node_lfir2.xml b/test/simulator/sample_data/node_lfir2.xml
new file mode 100644
index 0000000..ccaa3e0
--- /dev/null
+++ b/test/simulator/sample_data/node_lfir2.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="SAMPLE_10" name="LFIR2" reg_type="SCOM">
+    <local_fir config="W2" name="LFIR2">
+        <instance addr="0x0000f200" reg_inst="0"/>
+        <action attn_type="CS" config="000"/>
+        <action attn_type="RE" config="010"/>
+    </local_fir>
+    <bit pos="0">Attention A</bit>
+    <bit pos="1">Attention B</bit>
+    <bit pos="2">Attention C</bit>
+    <bit pos="3">Attention D</bit>
+</attn_node>
diff --git a/test/simulator/sample_data/sample.cdb b/test/simulator/sample_data/sample.cdb
new file mode 100644
index 0000000..7d2717e
--- /dev/null
+++ b/test/simulator/sample_data/sample.cdb
Binary files differ
diff --git a/test/simulator/sample_test_case.cpp b/test/simulator/sample_test_case.cpp
index af78ce0..7cf0c26 100644
--- a/test/simulator/sample_test_case.cpp
+++ b/test/simulator/sample_test_case.cpp
@@ -6,12 +6,74 @@
 
 START_ITERATION
 
+REG_SCOM(proc0, 0xf0000000, 0x0000000000000000) // GFIR_CS
+REG_SCOM(proc0, 0xf0000001, 0x0000000000000000) // GFIR_RE
+
+REG_SCOM(proc0, 0x00f00000, 0x0000000000000000) // CFIR0_CS   inst 0
+REG_SCOM(proc0, 0x00f00001, 0x0000000000000000) // CFIR0_RE   inst 0
+REG_SCOM(proc0, 0x00f00002, 0x0000000000000000) // CFIR0_MASK inst 0
+
+REG_SCOM(proc0, 0x00f00010, 0x0000000000000000) // CFIR0_CS   inst 1
+REG_SCOM(proc0, 0x00f00011, 0x0000000000000000) // CFIR0_RE   inst 1
+REG_SCOM(proc0, 0x00f00012, 0x0000000000000000) // CFIR0_MASK inst 1
+
+REG_SCOM(proc0, 0x00f10000, 0x0000000000000000) // CFIR1_CS   inst 0
+REG_SCOM(proc0, 0x00f10001, 0x0000000000000000) // CFIR1_RE   inst 0
+REG_SCOM(proc0, 0x00f10002, 0x0000000000000000) // CFIR1_MASK inst 0
+
+REG_SCOM(proc0, 0x0000f000, 0x0000000000000000) // LFIR0      inst 0
+REG_SCOM(proc0, 0x0000f003, 0x0000000000000000) // LFIR0_MASK inst 0
+REG_SCOM(proc0, 0x0000f006, 0x0000000000000000) // LFIR0_ACT0 inst 0
+REG_SCOM(proc0, 0x0000f007, 0x0000000000000000) // LFIR0_ACT1 inst 0
+
+REG_SCOM(proc0, 0x0000f010, 0x0000000000000000) // LFIR0      inst 1
+REG_SCOM(proc0, 0x0000f013, 0x0000000000000000) // LFIR0_MASK inst 1
+REG_SCOM(proc0, 0x0000f016, 0x0000000000000000) // LFIR0_ACT0 inst 1
+REG_SCOM(proc0, 0x0000f017, 0x0000000000000000) // LFIR0_ACT1 inst 1
+
+REG_SCOM(proc0, 0x0000f100, 0x0000000000000000) // LFIR1      inst 0
+REG_SCOM(proc0, 0x0000f103, 0x0000000000000000) // LFIR1_MASK inst 0
+REG_SCOM(proc0, 0x0000f106, 0x0000000000000000) // LFIR1_ACT0 inst 0
+REG_SCOM(proc0, 0x0000f107, 0x0000000000000000) // LFIR1_ACT1 inst 0
+
+REG_SCOM(proc0, 0x0000f110, 0x0000000000000000) // LFIR1      inst 1
+REG_SCOM(proc0, 0x0000f113, 0x0000000000000000) // LFIR1_MASK inst 1
+REG_SCOM(proc0, 0x0000f116, 0x0000000000000000) // LFIR1_ACT0 inst 1
+REG_SCOM(proc0, 0x0000f117, 0x0000000000000000) // LFIR1_ACT1 inst 1
+
+REG_SCOM(proc0, 0x0000f120, 0x0000000000000000) // LFIR1      inst 2
+REG_SCOM(proc0, 0x0000f123, 0x0000000000000000) // LFIR1_MASK inst 2
+REG_SCOM(proc0, 0x0000f126, 0x0000000000000000) // LFIR1_ACT0 inst 2
+REG_SCOM(proc0, 0x0000f127, 0x0000000000000000) // LFIR1_ACT1 inst 2
+
+REG_SCOM(proc0, 0x0000f130, 0x0000000000000000) // LFIR1      inst 3
+REG_SCOM(proc0, 0x0000f133, 0x0000000000000000) // LFIR1_MASK inst 3
+REG_SCOM(proc0, 0x0000f136, 0x0000000000000000) // LFIR1_ACT0 inst 3
+REG_SCOM(proc0, 0x0000f137, 0x0000000000000000) // LFIR1_ACT1 inst 3
+
+REG_SCOM(proc0, 0x0000f140, 0x0000000000000000) // LFIR1      inst 4
+REG_SCOM(proc0, 0x0000f143, 0x0000000000000000) // LFIR1_MASK inst 4
+REG_SCOM(proc0, 0x0000f146, 0x0000000000000000) // LFIR1_ACT0 inst 4
+REG_SCOM(proc0, 0x0000f147, 0x0000000000000000) // LFIR1_ACT1 inst 4
+
+REG_SCOM(proc0, 0x0000f150, 0x0000000000000000) // LFIR1      inst 5
+REG_SCOM(proc0, 0x0000f153, 0x0000000000000000) // LFIR1_MASK inst 5
+REG_SCOM(proc0, 0x0000f156, 0x0000000000000000) // LFIR1_ACT0 inst 5
+REG_SCOM(proc0, 0x0000f157, 0x0000000000000000) // LFIR1_ACT1 inst 5
+
+REG_SCOM(proc0, 0x0000f200, 0x0000000000000000) // LFIR2      inst 0
+REG_SCOM(proc0, 0x0000f203, 0x0000000000000000) // LFIR2_MASK inst 0
+REG_SCOM(proc0, 0x0000f206, 0x0000000000000000) // LFIR2_ACT0 inst 0
+REG_SCOM(proc0, 0x0000f207, 0x0000000000000000) // LFIR2_ACT1 inst 0
+
+// start temp test case
 REG_IDSCOM(proc0, 0x80000000FF000000, 0x8000) // parent FIR bit 48
 
 REG_SCOM(proc0, 0x00FF0000, 0x8800000000000000) // child FIR bits 0 and 4
 
 EXP_SIG(proc0, 0x2222, 0, 0, CHECKSTOP)
 EXP_SIG(proc0, 0x2222, 0, 4, CHECKSTOP)
+// end temp test case
 
 END_ITERATION
 
diff --git a/test/simulator/simulator.cpp b/test/simulator/simulator.cpp
index 2e480ac..dfedb61 100644
--- a/test/simulator/simulator.cpp
+++ b/test/simulator/simulator.cpp
@@ -10,7 +10,7 @@
 // Paths are relative from the build/ directory
 const std::map<SimulatorData::ChipType, const char*>
     SimulatorData::cv_chipPath = {
-        {SAMPLE, "../test/simulator/chip_data/sample.cdb"},
+        {SAMPLE, "../test/simulator/sample_data/sample.cdb"},
 };
 
 //------------------------------------------------------------------------------