Copied P10, Explorer, and Odyssey chip data from PRD project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I7d0b1571242fb2da9378bcbfa7c2f0541b8ac915
diff --git a/chip_data/chip_data_json.md b/chip_data/chip_data_json.md
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+# Chip Data File JSON Format
+
+## General Requirements/Guidelines
+
+- All file names must contain the `.json` extension. Otherwise, there are no
+ additional file name requirements.
+
+- The file format is flexible so that a chip can be described by one file or
+ many files. It is up to the data owner to determine how the data is split into
+ multiple files, if desired. The only requirement is that all data contained in
+ a file must be the same for all chip model/EC levels described by the file
+ (see the `model_ec` property). Otherwise, the necessary data must be split
+ into multiple files.
+
+- All files for a chip model/EC level must be contained within the same
+ directory (no sub-directories). A directory could contain files for more than
+ one chip model/EC level. A directory can contain non-JSON files, but all JSON
+ files in the directory must be Chip Data JSON.
+
+---
+
+## 1) Base JSON Object
+
+All files will have the same format, which is a JSON object containing the
+properties defined below.
+
+### 1.1) Property: `version` (required, integer)
+
+A positive integer representing the Chip Data file format version. This will be
+useful later if the file format needs to change. The initial version is `1` and
+is currently the only supported version.
+
+### 1.2) Property: `model_ec` (required, array of strings)
+
+An array of strings representing the chip models and EC levels represented by
+this file. See appendix for supported values.
+
+**Important:** This property allows us to reuse the same data definition for
+multiple chip models and/or EC levels. It is intentionally limited to the file
+scope for simplicity, maintainability, and readability. Separate files will be
+required if any data differs between chip models and/or EC levels.
+
+### 1.3) Property: `registers` (optional, object)
+
+A JSON object where the keys are register names and the values are Register JSON
+objects.
+
+A register name must be alphanumeric and/or underscores. No spaces or other
+symbols allowed. The register names will be displayed in log files.
+
+This property will be combined with all other definitions of this property in
+all other Chip Data files for the target chip models and EC levels defined in
+the `model_ec` property.
+
+Not all Chip Data files will need to define this property, which is why the
+field is optional. However, after combining all the files, at minimum, an entry
+should exist for every register referenced in the Isolation Node JSON objects.
+
+### 1.4) Property: `isolation_nodes` (optional, object)
+
+A JSON object where the keys are isolation node names and the values are
+Isolation Node JSON objects.
+
+An isolation node name must be alphanumeric and/or underscores. No spaces or
+other symbols allowed. The isolation node names will be displayed in log files.
+Note that these typically matches the name of the register(s) targeted for
+isolation, but it is not required.
+
+This property will be combined with all other definitions of this property in
+all other Chip Data files for the target chip models and EC levels defined in
+the `model_ec` property.
+
+Not all Chip Data files will need to define this property, which is why the
+field is optional. However, after combining all the files there should be at
+least one Isolation Node JSON object defined per attention type.
+
+### 1.5) Property: `root_nodes` (optional, object)
+
+A JSON object where the keys are attention types and the values are Root Node
+JSON objects. See appendix for supported attention types.
+
+This property will be combined with all other definitions of this property in
+all other Chip Data files for the target chip models and EC levels defined in
+the `model_ec` property.
+
+Not all Chip Data files will need to define this property, which is why the
+field is optional. However, after combining all the files there should be a Root
+Node JSON object defined for all attentions types supported on the target chip
+models and EC levels.
+
+### 1.6) Property: `capture_groups` (optional, object)
+
+A JSON object where the keys are capture group names and the values are an array
+of Capture Register JSON objects. The array is used to maintain the order in
+which registers are captured and stored in the FFDC.
+
+This property will be combined with all other definitions of this property in
+all other Chip Data files for the target chip models and EC levels defined in
+the `model_ec` property.
+
+Not all Chip Data files will need to define this property, which is why the
+field is optional.
+
+**Important:** All registers referenced by the Isolation Node Rules should be
+automatically captured for FFDC. Therefore, the capture groups should only be
+defined if additional registers are needed.
+
+---
+
+## 2) Register JSON object
+
+This describes a hardware register that may be used for isolation or simply
+captured for FFDC. At a minimum, a Register JSON object must exist for each
+register referenced by the Isolation Node JSON objects.
+
+### 2.2) Property: `reg_type` (optional, string)
+
+A string representing the register type, which specifies the register size, bit
+order, etc. Most registers are standard SCOM registers. So the default value of
+`SCOM` will be used when this property is not specified. See appendix for
+supported types.
+
+### 2.3) Property: `access` (optional, string)
+
+The hardware operation accessibility. Most registers have read and write access.
+So the default value of `RW` will be used when this property is not specified.
+See appendix for supported types.
+
+### 2.4) Property: `instances` (required, object)
+
+It is possible that a register could have multiple instances within a chip. For
+example, the same register could exist for each core on a processor chip.
+Generally, the isolation rules and bit definition for registers like these are
+the same for each instance. The only difference would be the register addresses
+associated with each instance. So, instead of repeating the same information
+multiple times, this object will contain the addresses for each unique instance
+of the register.
+
+The key is a register instance, which a unique integer value for the logical
+instance of the register. Note that the default value of `0` should be used for
+any single-instance registers.
+
+The value is a string representation of the address for this register instance.
+The length of this hexadecimal integer is dependent on the `reg_type` property.
+Note that value is intentionally a string for readability of the file. See
+appendix for number format requirements.
+
+---
+
+## 3) Isolation Node JSON object
+
+This object is a node in an attention isolation tree. It will contain:
+
+- A set of rules describing the registers and bit operations required to
+ determine if there are active attentions for supported attention types.
+
+- A bit definition of the rule results indicating whether an active attention
+ has been found or if it originated from another node in the isolation tree.
+
+- A list of registers associated with this isolation node to store in logs for
+ additional debug, if necessary.
+
+**Important:** A node typically represents a FIR. However, other hardware
+registers, or a combination of registers, could be used as well.
+
+### 3.1) Property: `reg_type` (optional, string)
+
+All registers used by this node must be of the same type. This dispels any
+ambiguity that may occur with the bitwise operations defined by the `rules`
+property. It also defines the maximum number of entries that can be defined in
+the `bits` property and the order of the bit positions (left to right vs. right
+to left).
+
+Most registers are standard SCOM registers. So the default value of `SCOM` will
+be used when this property is not specified. See appendix for supported types.
+
+### 3.2) Property: `instances` (required, array of integers)
+
+An array of integers representing the instances defined for this isolation node.
+
+### 3.3) Property: `rules` (required, array of objects)
+
+An array of Isolation Rule JSON objects.
+
+### 3.4) Property: `bits` (required, object)
+
+The keys are bit positions of the resulting rule output, which can be integers
+or integer ranges. See appendix for the number range format.
+
+The values are Isolation Bit JSON objects.
+
+### 3.5) Property: `capture_groups` (optional, array of objects)
+
+An array of Capture Group JSON objects. When isolating to this node, these
+objects provide a list of registers that should be captured and stored in log
+files for additional debug, if necessary. The array is used to maintain the
+order in which registers are captured and stored in the FFDC.
+
+---
+
+## 4) Isolation Rule JSON Object
+
+A rule specifies how an attention is raised from a register. A rule is
+constructed by a series of expressions (see `expr` below) which are bitwise
+operations on a register or set of registers. Any active bits (i.e. bit is set
+to 1) in the result of the expressions will indicate the active attentions for
+the rule.
+
+### 4.1) Property: `attn_type` (required, array of strings)
+
+An array of strings representing the attention types targeted for this rule.
+Some rules can be defined for more than one attention type, which is why this is
+an array. See appendix for supported values.
+
+### 4.2) Property: `node_inst` (required, array of integers)
+
+An array of integers representing the isolation node instances targeted for this
+rule. Some rules can be defined for more than one isolation node instance, which
+is why this is an array.
+
+### 4.3) Property: `expr` (required, object)
+
+An Isolation Rule Expression JSON object.
+
+---
+
+## 5) Isolation Rule Expression JSON object
+
+Expressions are used to characterize bitwise operations carried out against
+registers and/or integer constants. For example, `~some_register & 0xffff` will
+take the contents of `some_register`, apply a bitwise NOT operation, and then
+AND that value with the integer `0xffff`. This example will generate the
+following Isolation Rule JSON object:
+
+```json
+{
+ "attn_type": ["CS", "RE", "SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "some_register",
+ "reg_inst": { "0": 2, "1": 4 }
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0xffff"
+ }
+ ]
+ }
+}
+```
+
+For simplicity, the register and integer sizes will be defined by the `reg_type`
+property of the Isolation Node JSON object. This ensures all values are the same
+length, eliminating the ambiguity caused by variable register and integer sizes.
+
+### 5.1) Property: `expr_type` (required, string)
+
+This property is required for Isolation Rule Expression JSON objects. All other
+properties depend on this property's value.
+
+#### 5.1.1) Expression Type Value: `reg`
+
+This is a special expression that indicates the value of the target register
+should be used in this expression. Generally, this means reading the register
+value from hardware.
+
+##### 5.1.1.1) Additional Property: `reg_name` (required, string)
+
+The name of the target register. This would be the same value as the keys used
+in the `registers` property of the Base JSON object.
+
+##### 5.1.1.2) Additional Property: `reg_inst` (optional, object)
+
+An instance map from node instance (key) to register instance (value). See
+appendix for details on instance maps. If this property is not specified, the
+register instance value will always match the node instance value.
+
+**Important:** All nodes instances in the `node_inst` property of the containing
+Isolation Rule JSON object must exist as keys in this instance map.
+
+#### 5.1.2) Expression Type Value: `int`
+
+This simply represents an integer constant.
+
+##### 5.1.2.1) Additional Property: `int_value` (required, string)
+
+A right-justified, unsigned integer constant value. This number will be
+represented as a string for readability of hexadecimal numbers. See appendix for
+the number format rules.
+
+**Important:** The size of the constant is determined by the register type
+specified in the `reg_type` property of the containing Isolation Node JSON
+object. So if the register type is `SCOM`, which is 64-bit, and the value is
+`0xff`, the actual number will be `0x00000000000000ff`.
+
+#### 5.1.3) Expression Type Values: `and` and `or`
+
+Bitwise AND and OR operations (i.e. `EXPR_1 & EXPR_2 | EXPR_3`).
+
+##### 5.1.3.1) Additional Property: `exprs` (required, array of objects)
+
+An array of Isolation Rule Expression JSON objects. There must be at least two
+entries in the array, but more can be specified. Regardless of the array size,
+the same operation will be applied to all entries of the array after each
+sub-expression has been resolved.
+
+#### 5.1.4) Expression Type Value: `not`
+
+A bitwise NOT operation (i.e. `~EXPR`).
+
+##### 5.1.4.1) Additional Property: `expr` (required, object)
+
+An Isolation Rule Expression JSON object. The NOT operation will be applied
+after the sub-expression has been resolved.
+
+#### 5.1.5) Expression Type Values: `lshift` and `rshift`
+
+Left and right shift operations (i.e. `(EXPR << 8) >> 16`).
+
+##### 5.1.5.1) Additional Property: `expr` (required, object)
+
+An Isolation Rule Expression JSON object. The shift operation will be applied
+after the sub-expression has been resolved.
+
+##### 5.1.5.2) Additional Property: `shift_value` (required, integer)
+
+The shift value. Must be a positive integer.
+
+**Important:** Any values shifted beyond the defined register length will be
+lost. For example, given the register length of 2 bytes, the expression
+`(0xffff << 8) >> 8` will resolve to `0x00ff`.
+
+---
+
+## 6) Isolation Bit JSON Object
+
+These objects provide the metadata for each bit defined by the isolation rules.
+
+### 6.1) Property: `desc` (required, string)
+
+A human-readable description of this bit, which will be displayed in log files.
+It is highly recommended to keep this description short and concise (~50
+characters) because longer descriptions will likely be truncated depending on
+the application.
+
+### 6.2) Property: `child_node` (optional, object)
+
+When specified, this property indicates the attention originated from another
+isolation node. This property is a simple JSON object with the following
+properties:
+
+#### 6.2.1) Subproperty: `name` (required, string)
+
+The name of the target isolation node. This would be the same value as the keys
+used in the `isolation_nodes` property of the Base JSON object.
+
+#### 6.2.2) Subproperty: `inst` (optional, object)
+
+An instance map from parent node instance (key) to child node instance (value).
+See appendix for details on instance maps. If this property is not specified,
+the child node instance value will always match the parent node instance value.
+
+**Important:** All nodes instances in the `instances` property of the containing
+Isolation Node JSON object must exist as keys in this instance map.
+
+### 6.3) Property: `capture_groups` (optional, array of objects)
+
+An array of Capture Group JSON objects. When isolating to this bit, these
+objects provide a list of registers that should be captured and stored in log
+files for additional debug, if necessary. The array is used to maintain the
+order in which registers are captured and stored in the FFDC.
+
+---
+
+## 7) Capture Group JSON Object
+
+This describes a capture group and which instances needs to be captured for
+FFDC.
+
+### 7.1) Property: `group_name` (required, string)
+
+A capture group name. This value is found in the keys of the `capture_groups`
+property of the Base JSON object.
+
+### 7.2) Property: `group_inst` (required, object)
+
+This is an instance map from node instance (key) to group instance (value). See
+appendix for details on instance maps.
+
+**Important:** If a node instance is not defined in this map, the group simply
+will not be captured.
+
+---
+
+## 8) Root Node JSON object
+
+The attention isolation tree can be traversed via the Isolation Node JSON
+objects. A Root Node JSON object is simply the root of the isolation tree for a
+specific attention type. As a reminder, the attention types are the keys of the
+`root_nodes` property of the Base JSON object.
+
+### 8.1) Property: `name` (required, string)
+
+The string name of the isolation node that will be the root of this isolation
+tree. This value is found in the keys of the `isolation_nodes` property of the
+Base JSON object.
+
+### 8.2) Property: `inst` (required, integer)
+
+The logical instance of the root node. This value is found in the `node_inst`
+property of an Isolation Node Rule object associated with the target isolation
+node.
+
+---
+
+## 9) Capture Register JSON Object
+
+This describes a register and which instances needs to be captured for FFDC.
+
+### 9.1) Property: `reg_name` (required, string)
+
+A register name. This value is found in the keys of the `registers` property of
+the Base JSON object.
+
+### 9.2) Property: `reg_inst` (required, object)
+
+This is an instance map from group instance (key) to register instance (value).
+See appendix for details on instance maps.
+
+**Important:** If a group instance is not defined in this map, the register
+simply will not be captured.
+
+---
+
+## 10) Appendix
+
+### 10.1) Number Formats
+
+All numbers in the Chip Data files are unsigned integers. When possible, the
+JSON integer data type should be used for performance and file size.
+Unfortunately, the JSON integer data type only allows base 10 numbers. For
+readability, some properties allow a string representation of the number
+specifically for numbers that are better served to be in the hexadecimal format.
+In which case, the string value must start with '0x'.
+
+### 10.2) Number Ranges
+
+A number range represents consecutive ascending or descending numbers (including
+both endpoints) and are expressed using a colon (e.g. "8:15" or "15:8").
+
+### 10.3) Instance Maps
+
+Instance Maps are a simple JSON object mapping one type of instance to another.
+Say for example you are targeting a specific capture group instance and you want
+to capture all of the associated registers for FFDC. The Capture Register JSON
+object instance maps define how group instances map to register instances.
+
+### 10.4) Supported Chip Models and EC Levels
+
+| Value | Description |
+| ------------- | ---------------------- |
+| `EXPLORER_11` | Explorer chip EC 1.1 |
+| `EXPLORER_20` | Explorer chip EC 2.0 |
+| `ODYSSEY_10` | Odyssey chip EC 1.0 |
+| `P11S_10` | P11 Spinal chip EC 1.0 |
+| `P11T_10` | P11 Tap chip EC 1.0 |
+
+### 10.5) Supported Attention Types
+
+**Important:** A chip checkstop is often associated with a system checkstop,
+which is certainly true for processor chips. However, systems may, but not
+always, recover from a chip checkstop on a memory buffer or other peripheral
+chips.
+
+| Value | Description |
+| ----- | ------------------------------------------------------------------ |
+| `CS` | Chip checkstop hardware attention. |
+| `UCS` | Local checkstop hardware attention within a chip unit. |
+| `RE` | Recoverable hardware attention. |
+| `SPA` | SW or HW event requiring action by the service processor firmware. |
+
+### 10.6) Supported Register Types
+
+- POWER Systems SCOM register (default)
+
+ - Property value: `SCOM`
+ - Address length: 4 bytes
+ - Register length: 8 bytes
+ - Bit order: ascending (0-63, left to right)
+
+- POWER Systems Indirect SCOM register
+ - Property value: `IDSCOM`
+ - Address length: 8 bytes
+ - Register length: 8 bytes
+ - Bit order: ascending (0-63, left to right)
+
+### 10.7) Supported Register Access Types
+
+| Value | Description |
+| ----- | ------------------------------- |
+| `RO` | read-only access |
+| `WO` | write-only access |
+| `RW` | read and write access (default) |
diff --git a/chip_data/explorer/chip_explorer.json b/chip_data/explorer/chip_explorer.json
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+++ b/chip_data/explorer/chip_explorer.json
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+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "root_nodes": {
+ "CS": {
+ "name": "CHIPLET_OCMB_FIR",
+ "inst": 0
+ },
+ "RE": {
+ "name": "CHIPLET_OCMB_FIR",
+ "inst": 0
+ },
+ "SPA": {
+ "name": "CHIPLET_OCMB_SPA_FIR",
+ "inst": 0
+ }
+ }
+}
diff --git a/chip_data/explorer/node_chiplet_ocmb_fir.json b/chip_data/explorer/node_chiplet_ocmb_fir.json
new file mode 100644
index 0000000..1bd1910
--- /dev/null
+++ b/chip_data/explorer/node_chiplet_ocmb_fir.json
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+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "CHIPLET_OCMB_CS_FIR": {
+ "instances": {
+ "0": "0x08040000"
+ }
+ },
+ "CHIPLET_OCMB_RE_FIR": {
+ "instances": {
+ "0": "0x08040001"
+ }
+ },
+ "CHIPLET_OCMB_FIR_MASK": {
+ "instances": {
+ "0": "0x08040002"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CHIPLET_OCMB_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_CS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x1FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_RE_FIR"
+ },
+ "shift_value": 2
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x1FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "3": {
+ "desc": "Attention from OCMB_LFIR",
+ "child_node": {
+ "name": "OCMB_LFIR"
+ }
+ },
+ "4": {
+ "desc": "Attention from MMIOFIR",
+ "child_node": {
+ "name": "MMIOFIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from SRQFIR",
+ "child_node": {
+ "name": "SRQFIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from MCBISTFIR",
+ "child_node": {
+ "name": "MCBISTFIR"
+ }
+ },
+ "9": {
+ "desc": "Attention from RDFFIR",
+ "child_node": {
+ "name": "RDFFIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLXFIR",
+ "child_node": {
+ "name": "TLXFIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from OMI_DL_FIR",
+ "child_node": {
+ "name": "OMI_DL_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
new file mode 100644
index 0000000..0865a6e
--- /dev/null
+++ b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
@@ -0,0 +1,81 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "CHIPLET_OCMB_SPA_FIR": {
+ "instances": {
+ "0": "0x08040004"
+ }
+ },
+ "CHIPLET_OCMB_SPA_FIR_MASK": {
+ "instances": {
+ "0": "0x08040007"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CHIPLET_OCMB_SPA_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_SPA_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from MMIOFIR",
+ "child_node": {
+ "name": "MMIOFIR"
+ }
+ },
+ "4": {
+ "desc": "Attention from SRQFIR",
+ "child_node": {
+ "name": "SRQFIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from MCBISTFIR",
+ "child_node": {
+ "name": "MCBISTFIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from RDFFIR",
+ "child_node": {
+ "name": "RDFFIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from TLXFIR",
+ "child_node": {
+ "name": "TLXFIR"
+ }
+ },
+ "9": {
+ "desc": "Attention from OMI_DL_FIR",
+ "child_node": {
+ "name": "OMI_DL_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/explorer/node_mcbistfir.json b/chip_data/explorer/node_mcbistfir.json
new file mode 100644
index 0000000..80dde58
--- /dev/null
+++ b/chip_data/explorer/node_mcbistfir.json
@@ -0,0 +1,227 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "MCBISTFIR": {
+ "instances": {
+ "0": "0x08011800"
+ }
+ },
+ "MCBISTFIR_MASK": {
+ "instances": {
+ "0": "0x08011803"
+ }
+ },
+ "MCBISTFIR_ACT0": {
+ "instances": {
+ "0": "0x08011806"
+ }
+ },
+ "MCBISTFIR_ACT1": {
+ "instances": {
+ "0": "0x08011807"
+ }
+ },
+ "MCBISTFIR_WOF": {
+ "instances": {
+ "0": "0x08011808"
+ }
+ },
+ "MCB_ERR_RPT_0": {
+ "instances": {
+ "0": "0x080118E7"
+ }
+ },
+ "MCB_ERR_RPT_1": {
+ "instances": {
+ "0": "0x080118EC"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MCBISTFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBISTFIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Invalid maint address"
+ },
+ "1": {
+ "desc": "Command address timeout"
+ },
+ "2": {
+ "desc": "Internal FSM error"
+ },
+ "3": {
+ "desc": "MCBIST broadcast out of sync"
+ },
+ "4": {
+ "desc": "MCBIST data error"
+ },
+ "5": {
+ "desc": "Hard NCE ETE attn"
+ },
+ "6": {
+ "desc": "Soft NCE ETE attn"
+ },
+ "7": {
+ "desc": "Int NCE ETE attn"
+ },
+ "8": {
+ "desc": "RCE ETE attn"
+ },
+ "9": {
+ "desc": "ICE (IMPE) ETE attn"
+ },
+ "10": {
+ "desc": "MCBIST program complete"
+ },
+ "11": {
+ "desc": "MCBIST CCS subtest done"
+ },
+ "12": {
+ "desc": "WAT debug bus attn"
+ },
+ "13": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "14": {
+ "desc": "SCOM fatal reg parity error"
+ },
+ "15": {
+ "desc": "SCOM WAT and debug reg parity error"
+ },
+ "16:17": {
+ "desc": "Reserved"
+ },
+ "18": {
+ "desc": "Internal SCOM error"
+ },
+ "19": {
+ "desc": "Internal SCOM error clone"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MCBISTFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MCBISTFIR": [
+ {
+ "reg_name": "MCB_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_mmiofir.json b/chip_data/explorer/node_mmiofir.json
new file mode 100644
index 0000000..300d1e2
--- /dev/null
+++ b/chip_data/explorer/node_mmiofir.json
@@ -0,0 +1,206 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "MMIOFIR": {
+ "instances": {
+ "0": "0x08010870"
+ }
+ },
+ "MMIOFIR_MASK": {
+ "instances": {
+ "0": "0x08010873"
+ }
+ },
+ "MMIOFIR_ACT0": {
+ "instances": {
+ "0": "0x08010876"
+ }
+ },
+ "MMIOFIR_ACT1": {
+ "instances": {
+ "0": "0x08010877"
+ }
+ },
+ "MMIOFIR_WOF": {
+ "instances": {
+ "0": "0x08010878"
+ }
+ },
+ "MMIO_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801087C"
+ }
+ },
+ "MMIO_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801087E"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MMIOFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIOFIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "AFU desc unimp"
+ },
+ "1": {
+ "desc": "MMIO err"
+ },
+ "2": {
+ "desc": "SCOM err"
+ },
+ "3": {
+ "desc": "FSM perr"
+ },
+ "4": {
+ "desc": "FIFO overflow"
+ },
+ "5": {
+ "desc": "Ctl reg parity err"
+ },
+ "6": {
+ "desc": "Info reg parity error"
+ },
+ "7": {
+ "desc": "SNSC both starts err"
+ },
+ "8": {
+ "desc": "SNSC mult seq parity err"
+ },
+ "9": {
+ "desc": "SNSC FSM parity err"
+ },
+ "10": {
+ "desc": "SNSC reg parity err"
+ },
+ "11": {
+ "desc": "acTAG PASID cfg err"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MMIOFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MMIOFIR": [
+ {
+ "reg_name": "MMIO_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MMIO_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_ocmb_lfir.json b/chip_data/explorer/node_ocmb_lfir.json
new file mode 100644
index 0000000..fa784af
--- /dev/null
+++ b/chip_data/explorer/node_ocmb_lfir.json
@@ -0,0 +1,349 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "OCMB_LFIR": {
+ "instances": {
+ "0": "0x0804000A"
+ }
+ },
+ "OCMB_LFIR_MASK": {
+ "instances": {
+ "0": "0x0804000D"
+ }
+ },
+ "OCMB_LFIR_ACT0": {
+ "instances": {
+ "0": "0x08040010"
+ }
+ },
+ "OCMB_LFIR_ACT1": {
+ "instances": {
+ "0": "0x08040011"
+ }
+ },
+ "ADSP_PCBI": {
+ "instances": {
+ "0": "0x00200860",
+ "1": "0x00201860",
+ "2": "0x00202860",
+ "3": "0x00203860",
+ "4": "0x00204860",
+ "5": "0x00205860",
+ "6": "0x00206860",
+ "7": "0x00207860"
+ }
+ },
+ "CSU_PCBI": {
+ "instances": {
+ "0": "0x002000B0",
+ "1": "0x002010B0",
+ "2": "0x002020B0",
+ "3": "0x002030B0",
+ "4": "0x002040B0",
+ "5": "0x002050B0",
+ "6": "0x002060B0",
+ "7": "0x002070B0"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OCMB_LFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_LFIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR access PCB error"
+ },
+ "1": {
+ "desc": "CFIR internal parity error"
+ },
+ "2": {
+ "desc": "LFIR internal parity error"
+ },
+ "3": {
+ "desc": "Debug scom satellite error"
+ },
+ "4": {
+ "desc": "PSCOM Logic: PCB Access Error"
+ },
+ "5": {
+ "desc": "PSCOM Logic: Summarized internal errors"
+ },
+ "6": {
+ "desc": "Trace Logic : Scom Satellite Error - Trace0"
+ },
+ "7": {
+ "desc": "Trace Logic : Scom Satellite Error - Trace1"
+ },
+ "8": {
+ "desc": "PIB2GIF parity error on FSM or Registers"
+ },
+ "9": {
+ "desc": "MSG access PCB error"
+ },
+ "10:18": {
+ "desc": "unused"
+ },
+ "19": {
+ "desc": "DLL IRQ"
+ },
+ "20": {
+ "desc": "Watchdog timer interrupt"
+ },
+ "21": {
+ "desc": "internal temp sensor tripped a threshold"
+ },
+ "22": {
+ "desc": "GPBC_FATAL_ERROR"
+ },
+ "23": {
+ "desc": "GPBC_NON_FATAL_ERROR"
+ },
+ "24": {
+ "desc": "early power off warning"
+ },
+ "25": {
+ "desc": "TOP fatal interrupts"
+ },
+ "26": {
+ "desc": "TOP non fatal interrupts"
+ },
+ "27:30": {
+ "desc": "Interrupt from OPSe to OCMB"
+ },
+ "31": {
+ "desc": "SerDes continuous calibration failure"
+ },
+ "32": {
+ "desc": "Firmware Assert or CPU Exception"
+ },
+ "33": {
+ "desc": "Extended error information ready"
+ },
+ "34": {
+ "desc": "Interrupt from OPSe to OCMB"
+ },
+ "35": {
+ "desc": "DDR thermal event"
+ },
+ "36": {
+ "desc": "DDR4 PHY fatal"
+ },
+ "37": {
+ "desc": "DDR4 PHY non fatal"
+ },
+ "38": {
+ "desc": "DDR4 PHY interrupt"
+ },
+ "39": {
+ "desc": "foxhound fatal lane 7"
+ },
+ "40": {
+ "desc": "foxhound fatal lane 6"
+ },
+ "41": {
+ "desc": "foxhound fatal lane 5"
+ },
+ "42": {
+ "desc": "foxhound fatal lane 4"
+ },
+ "43": {
+ "desc": "foxhound fatal lane 3"
+ },
+ "44": {
+ "desc": "foxhound fatal lane 2"
+ },
+ "45": {
+ "desc": "foxhound fatal lane 1"
+ },
+ "46": {
+ "desc": "foxhound fatal lane 0"
+ },
+ "47:54": {
+ "desc": "foxhound non fatal"
+ },
+ "55:62": {
+ "desc": "foxhound serdes interrupt"
+ },
+ "63": {
+ "desc": "GIF2PCB parity error on FSM or Registers"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "OCMB_LFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "OCMB_LFIR": [
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 4
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 5
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 6
+ }
+ },
+ {
+ "reg_name": "ADSP_PCBI",
+ "reg_inst": {
+ "0": 7
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 4
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 5
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 6
+ }
+ },
+ {
+ "reg_name": "CSU_PCBI",
+ "reg_inst": {
+ "0": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_omi_dl_err_rpt.json b/chip_data/explorer/node_omi_dl_err_rpt.json
new file mode 100644
index 0000000..c2e38bf
--- /dev/null
+++ b/chip_data/explorer/node_omi_dl_err_rpt.json
@@ -0,0 +1,100 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "isolation_nodes": {
+ "OMI_DL_ERR_RPT": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "52": {
+ "desc": "spare"
+ },
+ "53": {
+ "desc": "spare"
+ },
+ "54": {
+ "desc": "spare"
+ },
+ "55": {
+ "desc": "RX receiving slow A"
+ },
+ "56": {
+ "desc": "RX receiving illegal run length"
+ },
+ "57": {
+ "desc": "control parity error"
+ },
+ "58": {
+ "desc": "data parity error"
+ },
+ "59": {
+ "desc": "truncated flit from TL"
+ },
+ "60": {
+ "desc": "illegal run length from TL"
+ },
+ "61": {
+ "desc": "Ack pointer overflow"
+ },
+ "62": {
+ "desc": "UE on control flit replay buffer"
+ },
+ "63": {
+ "desc": "UE on control flit frame buffer"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/explorer/node_omi_dl_fir.json b/chip_data/explorer/node_omi_dl_fir.json
new file mode 100644
index 0000000..989a636
--- /dev/null
+++ b/chip_data/explorer/node_omi_dl_fir.json
@@ -0,0 +1,397 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "OMI_DL_FIR": {
+ "instances": {
+ "0": "0x08012800"
+ }
+ },
+ "OMI_DL_FIR_MASK": {
+ "instances": {
+ "0": "0x08012803"
+ }
+ },
+ "OMI_DL_FIR_ACT0": {
+ "instances": {
+ "0": "0x08012806"
+ }
+ },
+ "OMI_DL_FIR_ACT1": {
+ "instances": {
+ "0": "0x08012807"
+ }
+ },
+ "OMI_DL_FIR_WOF": {
+ "instances": {
+ "0": "0x08012808"
+ }
+ },
+ "CMN_CONFIG": {
+ "instances": {
+ "0": "0x0801280E"
+ }
+ },
+ "PMU_CNTR": {
+ "instances": {
+ "0": "0x0801280F"
+ }
+ },
+ "OMI_DL_CONFIG0": {
+ "instances": {
+ "0": "0x08012810"
+ }
+ },
+ "OMI_DL_CONFIG1": {
+ "instances": {
+ "0": "0x08012811"
+ }
+ },
+ "OMI_DL_ERR_MASK": {
+ "instances": {
+ "0": "0x08012812"
+ }
+ },
+ "OMI_DL_ERR_RPT": {
+ "instances": {
+ "0": "0x08012813"
+ }
+ },
+ "OMI_DL_ERR_CAPTURE": {
+ "instances": {
+ "0": "0x08012814"
+ }
+ },
+ "OMI_DL_EDPL_MAX_COUNT": {
+ "instances": {
+ "0": "0x08012815"
+ }
+ },
+ "OMI_DL_STATUS": {
+ "instances": {
+ "0": "0x08012816"
+ }
+ },
+ "OMI_DL_TRAINING_STATUS": {
+ "instances": {
+ "0": "0x08012817"
+ }
+ },
+ "OMI_DL_DLX_CONFIG": {
+ "instances": {
+ "0": "0x08012818"
+ }
+ },
+ "OMI_DL_DLX_INFO": {
+ "instances": {
+ "0": "0x08012819"
+ }
+ },
+ "OMI_DL_ERR_ACTION": {
+ "instances": {
+ "0": "0x0801281D"
+ }
+ },
+ "OMI_DL_DEBUG_AID": {
+ "instances": {
+ "0": "0x0801281E"
+ }
+ },
+ "OMI_DL_CYA_BITS": {
+ "instances": {
+ "0": "0x0801281F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OMI_DL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OMI-DL0 fatal error",
+ "child_node": {
+ "name": "OMI_DL_ERR_RPT",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "1": {
+ "desc": "OMI-DL0 UE on data flit"
+ },
+ "2": {
+ "desc": "OMI-DL0 CE on TL flit"
+ },
+ "3": {
+ "desc": "OMI-DL0 detected a CRC error"
+ },
+ "4": {
+ "desc": "OMI-DL0 received a nack"
+ },
+ "5": {
+ "desc": "OMI-DL0 running in degraded mode"
+ },
+ "6": {
+ "desc": "OMI-DL0 parity error detection on a lane"
+ },
+ "7": {
+ "desc": "OMI-DL0 retrained due to no forward progress"
+ },
+ "8": {
+ "desc": "OMI-DL0 remote side initiated a retrain"
+ },
+ "9": {
+ "desc": "OMI-DL0 retrain due to internal error or software"
+ },
+ "10": {
+ "desc": "OMI-DL0 threshold reached"
+ },
+ "11": {
+ "desc": "OMI-DL0 trained"
+ },
+ "12": {
+ "desc": "OMI-DL0 endpoint error bit 0"
+ },
+ "13": {
+ "desc": "OMI-DL0 endpoint error bit 1"
+ },
+ "14": {
+ "desc": "OMI-DL0 endpoint error bit 2"
+ },
+ "15": {
+ "desc": "OMI-DL0 endpoint error bit 3"
+ },
+ "16": {
+ "desc": "OMI-DL0 endpoint error bit 4"
+ },
+ "17": {
+ "desc": "OMI-DL0 endpoint error bit 5"
+ },
+ "18": {
+ "desc": "OMI-DL0 endpoint error bit 6"
+ },
+ "19": {
+ "desc": "OMI-DL0 endpoint error bit 7"
+ },
+ "20:39": {
+ "desc": "OMI-DL1"
+ },
+ "40:59": {
+ "desc": "OMI-DL2"
+ },
+ "60": {
+ "desc": "Performance monitor wrapped"
+ },
+ "61": {
+ "desc": "reserved"
+ },
+ "62": {
+ "desc": "LFIR internal parity error"
+ },
+ "63": {
+ "desc": "SCOM Satellite Error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "OMI_DL_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "OMI_DL_FIR": [
+ {
+ "reg_name": "CMN_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PMU_CNTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_CONFIG0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_CONFIG1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_ERR_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_ERR_CAPTURE",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_DLX_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_DLX_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_ERR_ACTION",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_DEBUG_AID",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OMI_DL_CYA_BITS",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_rdffir.json b/chip_data/explorer/node_rdffir.json
new file mode 100644
index 0000000..a597425
--- /dev/null
+++ b/chip_data/explorer/node_rdffir.json
@@ -0,0 +1,739 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "RDFFIR": {
+ "instances": {
+ "0": "0x08011C00"
+ }
+ },
+ "RDFFIR_MASK": {
+ "instances": {
+ "0": "0x08011C03"
+ }
+ },
+ "RDFFIR_ACT0": {
+ "instances": {
+ "0": "0x08011C06"
+ }
+ },
+ "RDFFIR_ACT1": {
+ "instances": {
+ "0": "0x08011C07"
+ }
+ },
+ "RDFFIR_WOF": {
+ "instances": {
+ "0": "0x08011C08"
+ }
+ },
+ "FARB0": {
+ "instances": {
+ "0": "0x08011415"
+ }
+ },
+ "MBSEC0": {
+ "instances": {
+ "0": "0x08011855"
+ }
+ },
+ "MBSEC1": {
+ "instances": {
+ "0": "0x08011856"
+ }
+ },
+ "MBSTR": {
+ "instances": {
+ "0": "0x08011857"
+ }
+ },
+ "MBSSYMEC": {
+ "instances": {
+ "0": "0x08011858",
+ "1": "0x08011859",
+ "2": "0x0801185A",
+ "3": "0x0801185B",
+ "4": "0x0801185C",
+ "5": "0x0801185D",
+ "6": "0x0801185E",
+ "7": "0x0801185F",
+ "8": "0x08011860"
+ }
+ },
+ "MBSMSEC": {
+ "instances": {
+ "0": "0x08011869"
+ }
+ },
+ "MBNCER": {
+ "instances": {
+ "0": "0x0801186A"
+ }
+ },
+ "MBRCER": {
+ "instances": {
+ "0": "0x0801186B"
+ }
+ },
+ "MBMPER": {
+ "instances": {
+ "0": "0x0801186C"
+ }
+ },
+ "MBUER": {
+ "instances": {
+ "0": "0x0801186D"
+ }
+ },
+ "MBAUER": {
+ "instances": {
+ "0": "0x0801186E"
+ }
+ },
+ "MC_ADDR_TRANS0": {
+ "instances": {
+ "0": "0x0801186F"
+ }
+ },
+ "MC_ADDR_TRANS1": {
+ "instances": {
+ "0": "0x08011870"
+ }
+ },
+ "MC_ADDR_TRANS2": {
+ "instances": {
+ "0": "0x08011871"
+ }
+ },
+ "MBSEVR0": {
+ "instances": {
+ "0": "0x0801187E"
+ }
+ },
+ "MCBAGRA": {
+ "instances": {
+ "0": "0x080118D6"
+ }
+ },
+ "MCBMCAT": {
+ "instances": {
+ "0": "0x080118D7"
+ }
+ },
+ "MCB_CNTL": {
+ "instances": {
+ "0": "0x080118DB"
+ }
+ },
+ "MCB_CNTLSTAT": {
+ "instances": {
+ "0": "0x080118DC"
+ }
+ },
+ "MCBCFG": {
+ "instances": {
+ "0": "0x080118E0"
+ }
+ },
+ "EXP_MSR": {
+ "instances": {
+ "0": "0x08011C0C"
+ }
+ },
+ "RDF_ERR_RPT_0": {
+ "instances": {
+ "0": "0x08011C0E"
+ }
+ },
+ "RDF_ERR_RPT_1": {
+ "instances": {
+ "0": "0x08011C0F"
+ }
+ },
+ "HW_MS": {
+ "instances": {
+ "0": "0x08011C10",
+ "1": "0x08011C11",
+ "2": "0x08011C12",
+ "3": "0x08011C13",
+ "4": "0x08011C14",
+ "5": "0x08011C15",
+ "6": "0x08011C16",
+ "7": "0x08011C17"
+ }
+ },
+ "FW_MS": {
+ "instances": {
+ "0": "0x08011C18",
+ "1": "0x08011C19",
+ "2": "0x08011C1A",
+ "3": "0x08011C1B",
+ "4": "0x08011C1C",
+ "5": "0x08011C1D",
+ "6": "0x08011C1E",
+ "7": "0x08011C1F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "RDFFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDFFIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Mainline read MPE on rank 0"
+ },
+ "1": {
+ "desc": "Mainline read MPE on rank 1"
+ },
+ "2": {
+ "desc": "Mainline read MPE on rank 2"
+ },
+ "3": {
+ "desc": "Mainline read MPE on rank 3"
+ },
+ "4": {
+ "desc": "Mainline read MPE on rank 4"
+ },
+ "5": {
+ "desc": "Mainline read MPE on rank 5"
+ },
+ "6": {
+ "desc": "Mainline read MPE on rank 6"
+ },
+ "7": {
+ "desc": "Mainline read MPE on rank 7"
+ },
+ "8": {
+ "desc": "Mainline read NCE"
+ },
+ "9": {
+ "desc": "Mainline read TCE"
+ },
+ "10": {
+ "desc": "Mainline read SCE"
+ },
+ "11": {
+ "desc": "Mainline read MCE"
+ },
+ "12": {
+ "desc": "Mainline read SUE"
+ },
+ "13": {
+ "desc": "Mainline read AUE"
+ },
+ "14": {
+ "desc": "Mainline read UE"
+ },
+ "15": {
+ "desc": "Mainline read RCD"
+ },
+ "16": {
+ "desc": "Mainline read IAUE"
+ },
+ "17": {
+ "desc": "Mainline read IUE"
+ },
+ "18": {
+ "desc": "Mainline read IRCD"
+ },
+ "19": {
+ "desc": "Mainline read IMPE"
+ },
+ "20": {
+ "desc": "Maintenance MPE on rank 0"
+ },
+ "21": {
+ "desc": "Maintenance MPE on rank 1"
+ },
+ "22": {
+ "desc": "Maintenance MPE on rank 2"
+ },
+ "23": {
+ "desc": "Maintenance MPE on rank 3"
+ },
+ "24": {
+ "desc": "Maintenance MPE on rank 4"
+ },
+ "25": {
+ "desc": "Maintenance MPE on rank 5"
+ },
+ "26": {
+ "desc": "Maintenance MPE on rank 6"
+ },
+ "27": {
+ "desc": "Maintenance MPE on rank 7"
+ },
+ "28": {
+ "desc": "Maintenance NCE"
+ },
+ "29": {
+ "desc": "Maintenance TCE"
+ },
+ "30": {
+ "desc": "Maintenance SCE"
+ },
+ "31": {
+ "desc": "Maintenance MCE"
+ },
+ "32": {
+ "desc": "Maintenance SUE"
+ },
+ "33": {
+ "desc": "Maintenance AUE"
+ },
+ "34": {
+ "desc": "Maintenance UE"
+ },
+ "35": {
+ "desc": "Maintenance RCD"
+ },
+ "36": {
+ "desc": "Maintenance IAUE"
+ },
+ "37": {
+ "desc": "Maintenance IUE"
+ },
+ "38": {
+ "desc": "Maintenance IRCD"
+ },
+ "39": {
+ "desc": "Maintenance IMPE"
+ },
+ "40": {
+ "desc": "RDDATA valid error"
+ },
+ "41": {
+ "desc": "SCOM status register parity error"
+ },
+ "42": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "43": {
+ "desc": "SCOM unrecoverable register parity error"
+ },
+ "44": {
+ "desc": "ECC corrector internal parity error"
+ },
+ "45": {
+ "desc": "Rd Buff ECC CHK Cor CE DW0 Detected"
+ },
+ "46": {
+ "desc": "Rd Buff ECC CHK Cor CE DW1 Detected"
+ },
+ "47": {
+ "desc": "Rd Buff ECC CHK Cor UE DW0 Detected"
+ },
+ "48": {
+ "desc": "Rd Buff ECC CHK Cor UE DW1 Detected"
+ },
+ "49:59": {
+ "desc": "Reserved"
+ },
+ "60": {
+ "desc": "SCOM register parity error for debug/wat control"
+ },
+ "61": {
+ "desc": "Reserved"
+ },
+ "62": {
+ "desc": "Internal SCOM error"
+ },
+ "63": {
+ "desc": "Internal SCOM error copy"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "RDFFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "RDFFIR": [
+ {
+ "reg_name": "FARB0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEC0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEC1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 4
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 5
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 6
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 7
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC",
+ "reg_inst": {
+ "0": 8
+ }
+ },
+ {
+ "reg_name": "MBSMSEC",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBNCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBRCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBMPER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBAUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MC_ADDR_TRANS0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MC_ADDR_TRANS1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MC_ADDR_TRANS2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEVR0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBAGRA",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBMCAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTLSTAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBCFG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "EXP_MSR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RDF_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RDF_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 4
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 5
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 6
+ }
+ },
+ {
+ "reg_name": "HW_MS",
+ "reg_inst": {
+ "0": 7
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 4
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 5
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 6
+ }
+ },
+ {
+ "reg_name": "FW_MS",
+ "reg_inst": {
+ "0": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_srqfir.json b/chip_data/explorer/node_srqfir.json
new file mode 100644
index 0000000..c3a3cc6
--- /dev/null
+++ b/chip_data/explorer/node_srqfir.json
@@ -0,0 +1,252 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "SRQFIR": {
+ "instances": {
+ "0": "0x08011400"
+ }
+ },
+ "SRQFIR_MASK": {
+ "instances": {
+ "0": "0x08011403"
+ }
+ },
+ "SRQFIR_ACT0": {
+ "instances": {
+ "0": "0x08011406"
+ }
+ },
+ "SRQFIR_ACT1": {
+ "instances": {
+ "0": "0x08011407"
+ }
+ },
+ "SRQFIR_WOF": {
+ "instances": {
+ "0": "0x08011408"
+ }
+ },
+ "SRQ_ERR_RPT": {
+ "instances": {
+ "0": "0x0801141C"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "SRQFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQFIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "SRQ recoverable error"
+ },
+ "1": {
+ "desc": "SRQ nonrecoverable error"
+ },
+ "2": {
+ "desc": "Refresh overrun"
+ },
+ "3": {
+ "desc": "WAT error"
+ },
+ "4": {
+ "desc": "RCD parity error"
+ },
+ "5": {
+ "desc": "MCB logic error"
+ },
+ "6": {
+ "desc": "Emergency throttle"
+ },
+ "7": {
+ "desc": "NCF MCB parity error"
+ },
+ "8": {
+ "desc": "DDR MBA event n"
+ },
+ "9": {
+ "desc": "WRQ RRQ hang err"
+ },
+ "10": {
+ "desc": "SM one hot error"
+ },
+ "11": {
+ "desc": "Reg parity error"
+ },
+ "12": {
+ "desc": "Cmd parity error"
+ },
+ "13": {
+ "desc": "Port fail"
+ },
+ "14": {
+ "desc": "informational register parity error bit"
+ },
+ "15": {
+ "desc": "Debug parity error"
+ },
+ "16": {
+ "desc": "WDF unrecoverable mainline error"
+ },
+ "17": {
+ "desc": "WDF mmio error"
+ },
+ "18": {
+ "desc": "WDF array UE on mainline operations (SUE put in mem)"
+ },
+ "19": {
+ "desc": "WDF mainline dataflow error (SUE not reliably put in mem)"
+ },
+ "20": {
+ "desc": "WDF scom register parity err, affecting mainline config"
+ },
+ "21": {
+ "desc": "WDF scom register parity err, affecting scom ops only"
+ },
+ "22": {
+ "desc": "WDF SCOM fsm parity error"
+ },
+ "23": {
+ "desc": "WDF write buffer array CE"
+ },
+ "24": {
+ "desc": "NCF UE"
+ },
+ "25": {
+ "desc": "Firmware initiated channel fail"
+ },
+ "26": {
+ "desc": "NCF logic error"
+ },
+ "27": {
+ "desc": "NCF parity error"
+ },
+ "28": {
+ "desc": "NCF correctable error"
+ },
+ "29": {
+ "desc": "Internal scom error"
+ },
+ "30": {
+ "desc": "Internal scom error copy"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "SRQFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "SRQFIR": [
+ {
+ "reg_name": "SRQ_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/explorer/node_tlx_err_rpt_1.json b/chip_data/explorer/node_tlx_err_rpt_1.json
new file mode 100644
index 0000000..423071e
--- /dev/null
+++ b/chip_data/explorer/node_tlx_err_rpt_1.json
@@ -0,0 +1,97 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "isolation_nodes": {
+ "TLX_ERR_RPT_1": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000005C00000"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000005C00000"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_ERR_RPT_1_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000005C00000"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "37": {
+ "desc": "TLXT FIFO CE"
+ },
+ "39": {
+ "desc": "Unexpected Interrupt Response"
+ },
+ "40": {
+ "desc": "BDI Poisoned"
+ },
+ "41": {
+ "desc": "TLXT Metadata UE"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/explorer/node_tlxfir.json b/chip_data/explorer/node_tlxfir.json
new file mode 100644
index 0000000..56fb114
--- /dev/null
+++ b/chip_data/explorer/node_tlxfir.json
@@ -0,0 +1,301 @@
+{
+ "version": 1,
+ "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+ "registers": {
+ "TLXFIR": {
+ "instances": {
+ "0": "0x08012400"
+ }
+ },
+ "TLXFIR_MASK": {
+ "instances": {
+ "0": "0x08012403"
+ }
+ },
+ "TLXFIR_ACT0": {
+ "instances": {
+ "0": "0x08012406"
+ }
+ },
+ "TLXFIR_ACT1": {
+ "instances": {
+ "0": "0x08012407"
+ }
+ },
+ "TLXFIR_WOF": {
+ "instances": {
+ "0": "0x08012408"
+ }
+ },
+ "TLX_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801241C"
+ }
+ },
+ "TLX_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801241D"
+ }
+ },
+ "TLX_ERR_RPT_2": {
+ "instances": {
+ "0": "0x0801241E"
+ }
+ },
+ "TLX_ERR_RPT_0_MASK": {
+ "instances": {
+ "0": "0x08012414"
+ }
+ },
+ "TLX_ERR_RPT_1_MASK": {
+ "instances": {
+ "0": "0x08012415"
+ }
+ },
+ "TLX_ERR_RPT_2_MASK": {
+ "instances": {
+ "0": "0x08012416"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TLXFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLXFIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Info reg parity error"
+ },
+ "1": {
+ "desc": "Ctrl reg parity error"
+ },
+ "2": {
+ "desc": "TLX VC0 return credit counter overflow"
+ },
+ "3": {
+ "desc": "TLX VC1 return credit counter overflow"
+ },
+ "4": {
+ "desc": "TLX dcp0 return credit counter overflow"
+ },
+ "5": {
+ "desc": "TLX dcp1 return credit counter overflow"
+ },
+ "6": {
+ "desc": "TLX credit management block error"
+ },
+ "7": {
+ "desc": "TLX credit management block parity error"
+ },
+ "8": {
+ "desc": "TLXT fatal parity error"
+ },
+ "9": {
+ "desc": "TLXT recoverable error",
+ "child_node": {
+ "name": "TLX_ERR_RPT_1"
+ }
+ },
+ "10": {
+ "desc": "TLXT configuration error"
+ },
+ "11": {
+ "desc": "TLXT informational parity error"
+ },
+ "12": {
+ "desc": "TLXT hard error"
+ },
+ "13:15": {
+ "desc": "Reserved"
+ },
+ "16": {
+ "desc": "Corrupted pad mem pattern"
+ },
+ "17": {
+ "desc": "Downstream OC parity error"
+ },
+ "18": {
+ "desc": "OC malformed"
+ },
+ "19": {
+ "desc": "OC protocol error"
+ },
+ "20": {
+ "desc": "Address translate error"
+ },
+ "21": {
+ "desc": "Metadata unc or data parity error"
+ },
+ "22": {
+ "desc": "OC unsupported group 2"
+ },
+ "23": {
+ "desc": "OC unsupported group 1"
+ },
+ "24": {
+ "desc": "Bit flip control error"
+ },
+ "25": {
+ "desc": "Control HW error"
+ },
+ "26": {
+ "desc": "ECC corrected and others"
+ },
+ "27": {
+ "desc": "Trace stop"
+ },
+ "28": {
+ "desc": "Internal SCOM error"
+ },
+ "29": {
+ "desc": "Internal SCOM error clone"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "TLXFIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "TLXFIR": [
+ {
+ "reg_name": "TLX_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_0_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_1_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_2_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/chip_odyssey.json b/chip_data/odyssey/chip_odyssey.json
new file mode 100644
index 0000000..4e8f3c0
--- /dev/null
+++ b/chip_data/odyssey/chip_odyssey.json
@@ -0,0 +1,22 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "root_nodes": {
+ "CS": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "RE": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "SPA": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "UCS": {
+ "name": "GFIR",
+ "inst": 0
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_cfir_mem.json b/chip_data/odyssey/node_cfir_mem.json
new file mode 100644
index 0000000..d8c38ca
--- /dev/null
+++ b/chip_data/odyssey/node_cfir_mem.json
@@ -0,0 +1,229 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "CFIR_MEM_CS": {
+ "instances": {
+ "0": "0x08040000"
+ }
+ },
+ "CFIR_MEM_RE": {
+ "instances": {
+ "0": "0x08040001"
+ }
+ },
+ "CFIR_MEM_SPA": {
+ "instances": {
+ "0": "0x08040002"
+ }
+ },
+ "CFIR_MEM_UCS": {
+ "instances": {
+ "0": "0x08040003"
+ }
+ },
+ "CFIR_MEM_CS_MASK": {
+ "instances": {
+ "0": "0x08040040"
+ }
+ },
+ "CFIR_MEM_RE_MASK": {
+ "instances": {
+ "0": "0x08040041"
+ }
+ },
+ "CFIR_MEM_SPA_MASK": {
+ "instances": {
+ "0": "0x08040042"
+ }
+ },
+ "CFIR_MEM_UCS_MASK": {
+ "instances": {
+ "0": "0x08040043"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_MEM": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_cfir_tp.json b/chip_data/odyssey/node_cfir_tp.json
new file mode 100644
index 0000000..eca635b
--- /dev/null
+++ b/chip_data/odyssey/node_cfir_tp.json
@@ -0,0 +1,157 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "CFIR_TP_CS": {
+ "instances": {
+ "0": "0x01040000"
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": {
+ "0": "0x01040001"
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": {
+ "0": "0x01040002"
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": {
+ "0": "0x01040003"
+ }
+ },
+ "CFIR_TP_CS_MASK": {
+ "instances": {
+ "0": "0x01040040"
+ }
+ },
+ "CFIR_TP_RE_MASK": {
+ "instances": {
+ "0": "0x01040041"
+ }
+ },
+ "CFIR_TP_SPA_MASK": {
+ "instances": {
+ "0": "0x01040042"
+ }
+ },
+ "CFIR_TP_UCS_MASK": {
+ "instances": {
+ "0": "0x01040043"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_TP": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_dlx_err_rpt.json b/chip_data/odyssey/node_dlx_err_rpt.json
new file mode 100644
index 0000000..4554c54
--- /dev/null
+++ b/chip_data/odyssey/node_dlx_err_rpt.json
@@ -0,0 +1,123 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "isolation_nodes": {
+ "DLX_ERR_RPT": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "50": {
+ "desc": "buffer UE"
+ },
+ "51": {
+ "desc": "insufficient working lanes"
+ },
+ "52": {
+ "desc": "bad CRC from TLXT"
+ },
+ "53": {
+ "desc": "flit hammer"
+ },
+ "54": {
+ "desc": "TX lane reversal"
+ },
+ "55": {
+ "desc": "RX receiving slow A"
+ },
+ "56": {
+ "desc": "RX receiving illegal run length"
+ },
+ "57": {
+ "desc": "control parity error"
+ },
+ "58": {
+ "desc": "scom register parity error"
+ },
+ "59": {
+ "desc": "truncated flit from TL"
+ },
+ "60": {
+ "desc": "illegal run length from TL"
+ },
+ "61": {
+ "desc": "ack pointer overflow"
+ },
+ "62": {
+ "desc": "UE on bus from TLXT"
+ },
+ "63": {
+ "desc": "ECC UE on dword containing run length"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_dlx_fir.json b/chip_data/odyssey/node_dlx_fir.json
new file mode 100644
index 0000000..eaa5cbc
--- /dev/null
+++ b/chip_data/odyssey/node_dlx_fir.json
@@ -0,0 +1,429 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "DLX_FIR": {
+ "instances": {
+ "0": "0x08012400"
+ }
+ },
+ "DLX_FIR_MASK": {
+ "instances": {
+ "0": "0x08012402"
+ }
+ },
+ "DLX_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08012404"
+ }
+ },
+ "DLX_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08012405"
+ }
+ },
+ "DLX_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08012406"
+ }
+ },
+ "DLX_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08012407"
+ }
+ },
+ "DLX_FIR_WOF": {
+ "instances": {
+ "0": "0x08012408"
+ }
+ },
+ "CMN_CONFIG": {
+ "instances": {
+ "0": "0x0801240E"
+ }
+ },
+ "PMU_CNTR": {
+ "instances": {
+ "0": "0x0801240F"
+ }
+ },
+ "DLX_CONFIG0": {
+ "instances": {
+ "0": "0x08012410"
+ }
+ },
+ "DLX_CONFIG1": {
+ "instances": {
+ "0": "0x08012411"
+ }
+ },
+ "DLX_ERR_MASK": {
+ "instances": {
+ "0": "0x08012412"
+ }
+ },
+ "DLX_ERR_RPT": {
+ "instances": {
+ "0": "0x08012413"
+ }
+ },
+ "DLX_EDPL_MAX_COUNT": {
+ "instances": {
+ "0": "0x08012415"
+ }
+ },
+ "DLX_STATUS": {
+ "instances": {
+ "0": "0x08012416"
+ }
+ },
+ "DLX_TRAINING_STATUS": {
+ "instances": {
+ "0": "0x08012417"
+ }
+ },
+ "DLX_RMT_CONFIG": {
+ "instances": {
+ "0": "0x08012418"
+ }
+ },
+ "DLX_RMT_INFO": {
+ "instances": {
+ "0": "0x08012419"
+ }
+ },
+ "DLX_SKIT_CTL": {
+ "instances": {
+ "0": "0x0801241A"
+ }
+ },
+ "DLX_SKIT_STATUS": {
+ "instances": {
+ "0": "0x0801241B"
+ }
+ },
+ "DLX_CYA2": {
+ "instances": {
+ "0": "0x0801241C"
+ }
+ },
+ "DLX_ERR_ACTION": {
+ "instances": {
+ "0": "0x0801241D"
+ }
+ },
+ "DLX_DEBUG_AID": {
+ "instances": {
+ "0": "0x0801241E"
+ }
+ },
+ "DLX_CYA_BITS": {
+ "instances": {
+ "0": "0x0801241F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "DLX_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error in SCOM component"
+ },
+ "1": {
+ "desc": "DL0 fatal error",
+ "child_node": {
+ "name": "DLX_ERR_RPT",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "DL0 buffer UE / insufficient working lanes",
+ "child_node": {
+ "name": "DLX_ERR_RPT",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "DL0 CE on TL flit"
+ },
+ "4": {
+ "desc": "DL0 detected a CRC error"
+ },
+ "5": {
+ "desc": "DL0 received a nack"
+ },
+ "6": {
+ "desc": "DL0 running in degraded mode"
+ },
+ "7": {
+ "desc": "DL0 parity error detection on a lane"
+ },
+ "8": {
+ "desc": "DL0 retrained due to no forward progress"
+ },
+ "9": {
+ "desc": "DL0 remote side initiated a retrain"
+ },
+ "10": {
+ "desc": "DL0 retrain due to internal error or software"
+ },
+ "11": {
+ "desc": "DL0 threshold reached"
+ },
+ "12": {
+ "desc": "DL0 trained"
+ },
+ "13": {
+ "desc": "DL0 received replay flit with link_errors bit 0"
+ },
+ "14": {
+ "desc": "DL0 received replay flit with link_errors bit 1"
+ },
+ "15": {
+ "desc": "DL0 received replay flit with link_errors bit 2"
+ },
+ "16": {
+ "desc": "DL0 received replay flit with link_errors bit 3"
+ },
+ "17": {
+ "desc": "DL0 received replay flit with link_errors bit 4"
+ },
+ "18": {
+ "desc": "DL0 received replay flit with link_errors bit 5"
+ },
+ "19": {
+ "desc": "DL0 received replay flit with link_errors bit 6"
+ },
+ "20": {
+ "desc": "DL0 received replay flit with link_errors bit 7"
+ },
+ "21": {
+ "desc": "DL0 skitter error"
+ },
+ "22": {
+ "desc": "DL0 skitter drift detected"
+ },
+ "23:63": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "DLX_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "DLX_FIR": [
+ {
+ "reg_name": "CMN_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PMU_CNTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CONFIG0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CONFIG1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_RMT_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_RMT_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_SKIT_CTL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_SKIT_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CYA2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_ACTION",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_DEBUG_AID",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CYA_BITS",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_gfir.json b/chip_data/odyssey/node_gfir.json
new file mode 100644
index 0000000..86e36ca
--- /dev/null
+++ b/chip_data/odyssey/node_gfir.json
@@ -0,0 +1,85 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "GFIR_CS": {
+ "instances": {
+ "0": "0x570F001C"
+ }
+ },
+ "GFIR_RE": {
+ "instances": {
+ "0": "0x570F001B"
+ }
+ },
+ "GFIR_SPA": {
+ "instances": {
+ "0": "0x570F001A"
+ }
+ },
+ "GFIR_UCS": {
+ "instances": {
+ "0": "0x570F002A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "GFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_CS"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_RE"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_SPA"
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_UCS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_mcbist_fir.json b/chip_data/odyssey/node_mcbist_fir.json
new file mode 100644
index 0000000..0b50099
--- /dev/null
+++ b/chip_data/odyssey/node_mcbist_fir.json
@@ -0,0 +1,512 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MCBIST_FIR": {
+ "instances": {
+ "0": "0x08011400"
+ }
+ },
+ "MCBIST_FIR_MASK": {
+ "instances": {
+ "0": "0x08011402"
+ }
+ },
+ "MCBIST_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011404"
+ }
+ },
+ "MCBIST_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011405"
+ }
+ },
+ "MCBIST_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011406"
+ }
+ },
+ "MCBIST_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011407"
+ }
+ },
+ "MCBIST_FIR_WOF": {
+ "instances": {
+ "0": "0x08011408"
+ }
+ },
+ "MBSEC0": {
+ "instances": {
+ "0": "0x08011455"
+ }
+ },
+ "MBSEC1": {
+ "instances": {
+ "0": "0x08011456"
+ }
+ },
+ "MBSTR": {
+ "instances": {
+ "0": "0x08011457"
+ }
+ },
+ "MBSSYMEC0": {
+ "instances": {
+ "0": "0x08011458"
+ }
+ },
+ "MBSSYMEC1": {
+ "instances": {
+ "0": "0x08011459"
+ }
+ },
+ "MBSSYMEC2": {
+ "instances": {
+ "0": "0x0801145A"
+ }
+ },
+ "MBSSYMEC3": {
+ "instances": {
+ "0": "0x0801145B"
+ }
+ },
+ "MBSSYMEC4": {
+ "instances": {
+ "0": "0x0801145C"
+ }
+ },
+ "MBSSYMEC5": {
+ "instances": {
+ "0": "0x0801145D"
+ }
+ },
+ "MBSSYMEC6": {
+ "instances": {
+ "0": "0x0801145E"
+ }
+ },
+ "MBSSYMEC7": {
+ "instances": {
+ "0": "0x0801145F"
+ }
+ },
+ "MBSSYMEC8": {
+ "instances": {
+ "0": "0x08011460"
+ }
+ },
+ "MBSSYMEC9": {
+ "instances": {
+ "0": "0x08011461"
+ }
+ },
+ "MBSMSEC": {
+ "instances": {
+ "0": "0x08011469"
+ }
+ },
+ "MBNCER": {
+ "instances": {
+ "0": "0x0801146A"
+ }
+ },
+ "MBRCER": {
+ "instances": {
+ "0": "0x0801146B"
+ }
+ },
+ "MBMPER": {
+ "instances": {
+ "0": "0x0801146C"
+ }
+ },
+ "MBUER": {
+ "instances": {
+ "0": "0x0801146D"
+ }
+ },
+ "MBAUER": {
+ "instances": {
+ "0": "0x0801146E"
+ }
+ },
+ "MBA_ERR_MASK_0": {
+ "instances": {
+ "0": "0x08011473"
+ }
+ },
+ "MBA_ERR_MASK_1": {
+ "instances": {
+ "0": "0x08011474"
+ }
+ },
+ "MBSEVR0": {
+ "instances": {
+ "0": "0x0801147E"
+ }
+ },
+ "MCBAGRA": {
+ "instances": {
+ "0": "0x080114D6"
+ }
+ },
+ "MCBMCAT": {
+ "instances": {
+ "0": "0x080114D7"
+ }
+ },
+ "MCB_CNTL": {
+ "instances": {
+ "0": "0x080114DB"
+ }
+ },
+ "MCB_CNTLSTAT": {
+ "instances": {
+ "0": "0x080114DC"
+ }
+ },
+ "MCBCFG": {
+ "instances": {
+ "0": "0x080114E0"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MCBIST_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error in scom component"
+ },
+ "1": {
+ "desc": "Invalid maint address"
+ },
+ "2": {
+ "desc": "Command address timeout"
+ },
+ "3": {
+ "desc": "Internal FSM error"
+ },
+ "4": {
+ "desc": "CSS Array uncorrected CE or UE"
+ },
+ "5": {
+ "desc": "MCBIST data error"
+ },
+ "6": {
+ "desc": "Hard NCE ETE attn"
+ },
+ "7": {
+ "desc": "Soft NCE ETE attn"
+ },
+ "8": {
+ "desc": "Int NCE ETE attn"
+ },
+ "9": {
+ "desc": "IUE ETE attn"
+ },
+ "10": {
+ "desc": "ICE (IMPE) ETE attn"
+ },
+ "11": {
+ "desc": "MCBIST program complete"
+ },
+ "12": {
+ "desc": "MCBIST CCS subtest done"
+ },
+ "13": {
+ "desc": "WAT debug bus attn"
+ },
+ "14": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "15": {
+ "desc": "SCOM fatal reg parity error"
+ },
+ "16": {
+ "desc": "SCOM WAT and debug reg parity error"
+ },
+ "17": {
+ "desc": "IAUE ETE attn"
+ },
+ "18": {
+ "desc": "IRCD ETE attn"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MCBIST_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MCBIST_FIR": [
+ {
+ "reg_name": "MBSEC0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEC1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC4",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC5",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC6",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC7",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC8",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC9",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSMSEC",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBNCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBRCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBMPER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBA_ERR_MASK_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBA_ERR_MASK_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBAUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEVR0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBAGRA",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBMCAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTLSTAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBCFG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_mem_local_fir.json b/chip_data/odyssey/node_mem_local_fir.json
new file mode 100644
index 0000000..78fba62
--- /dev/null
+++ b/chip_data/odyssey/node_mem_local_fir.json
@@ -0,0 +1,185 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MEM_LOCAL_FIR": {
+ "instances": {
+ "0": "0x08040100"
+ }
+ },
+ "MEM_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x08040102"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08040104"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08040105"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08040106"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08040107"
+ }
+ },
+ "MEM_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x08040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MEM_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR/LFIR parity error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - clock control error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM Access Error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - various errors"
+ },
+ "7": {
+ "desc": "DBG - SCOM parity fail"
+ },
+ "8": {
+ "desc": "unused"
+ },
+ "9": {
+ "desc": "unused"
+ },
+ "10": {
+ "desc": "Trace00 - SCOM parity error"
+ },
+ "11:62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "external local checkstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_mmio_fir.json b/chip_data/odyssey/node_mmio_fir.json
new file mode 100644
index 0000000..138e08c
--- /dev/null
+++ b/chip_data/odyssey/node_mmio_fir.json
@@ -0,0 +1,219 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MMIO_FIR": {
+ "instances": {
+ "0": "0x08010870"
+ }
+ },
+ "MMIO_FIR_MASK": {
+ "instances": {
+ "0": "0x08010872"
+ }
+ },
+ "MMIO_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08010874"
+ }
+ },
+ "MMIO_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08010875"
+ }
+ },
+ "MMIO_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08010876"
+ }
+ },
+ "MMIO_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08010877"
+ }
+ },
+ "MMIO_FIR_WOF": {
+ "instances": {
+ "0": "0x08010878"
+ }
+ },
+ "MMIO_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801087C"
+ }
+ },
+ "MMIO_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801087E"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MMIO_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Interal SCOM logic parity error"
+ },
+ "1": {
+ "desc": "Attempt to access an unimplemented address in the AFU descriptor"
+ },
+ "2": {
+ "desc": "Error detected during MMIO inband or senor cache access"
+ },
+ "3": {
+ "desc": "Parity error in SCOM satellite component FSM"
+ },
+ "4": {
+ "desc": "Parity error in MMIO/CFG logic FSM"
+ },
+ "5": {
+ "desc": "Overflow detected in internal MMIO/CFG logic FIFO"
+ },
+ "6": {
+ "desc": "Fatal parity error detected in control register"
+ },
+ "7": {
+ "desc": "Parity error detected in informational register"
+ },
+ "8": {
+ "desc": "Both start signals asserted to Sensor cache logic"
+ },
+ "9": {
+ "desc": "Multiple parity errors on data from sequencer to sensor cache logic"
+ },
+ "10": {
+ "desc": "State machine parity error in sensor cache logic"
+ },
+ "11": {
+ "desc": "Sensor cache register parity error"
+ },
+ "12": {
+ "desc": "acTAG PASID config error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MMIO_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MMIO_FIR": [
+ {
+ "reg_name": "MMIO_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MMIO_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_ocmb_phy_fir.json b/chip_data/odyssey/node_ocmb_phy_fir.json
new file mode 100644
index 0000000..baa4df3
--- /dev/null
+++ b/chip_data/odyssey/node_ocmb_phy_fir.json
@@ -0,0 +1,236 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "OCMB_PHY_FIR": {
+ "instances": {
+ "0": "0x08010C00"
+ }
+ },
+ "OCMB_PHY_FIR_MASK": {
+ "instances": {
+ "0": "0x08010C02"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08010C04"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08010C05"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08010C06"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08010C07"
+ }
+ },
+ "OCMB_PHY_FIR_WOF": {
+ "instances": {
+ "0": "0x08010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OCMB_PHY_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "SCOM FSM or FIR register parity error"
+ },
+ "1": {
+ "desc": "RX state machine parity or mode register parity error (IOO0)"
+ },
+ "2": {
+ "desc": "reserved"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "reserved"
+ },
+ "5": {
+ "desc": "TX state machine parity or mode register parity error (IOO0)"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "reserved"
+ },
+ "8": {
+ "desc": "reserved"
+ },
+ "9": {
+ "desc": "reserved"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "reserved"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "PPE internal error"
+ },
+ "14": {
+ "desc": "PPE external error"
+ },
+ "15": {
+ "desc": "PPE Halt due to Watchdog or Interrupt"
+ },
+ "16": {
+ "desc": "PPE Halt due to Debug"
+ },
+ "17": {
+ "desc": "PPE Halted"
+ },
+ "18": {
+ "desc": "PPE Watchdog Timeout"
+ },
+ "19": {
+ "desc": "PPE Array Scrub was missed"
+ },
+ "20": {
+ "desc": "PPE Array uncorrectable error"
+ },
+ "21": {
+ "desc": "PPE Array correctable error"
+ },
+ "22": {
+ "desc": "PPE Code Recal Abort"
+ },
+ "23": {
+ "desc": "PPE Code Fatal Error"
+ },
+ "24": {
+ "desc": "PPE Code Bad Lane Warning"
+ },
+ "25": {
+ "desc": "PPE Code DFT Error"
+ },
+ "26": {
+ "desc": "PPE Code Recal Not Run"
+ },
+ "27": {
+ "desc": "PPE Code Thread Locked"
+ },
+ "28": {
+ "desc": "PPE Code Thread Active Time Exceeded"
+ },
+ "29": {
+ "desc": "reserved"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_odp_fir.json b/chip_data/odyssey/node_odp_fir.json
new file mode 100644
index 0000000..3ad5b8d
--- /dev/null
+++ b/chip_data/odyssey/node_odp_fir.json
@@ -0,0 +1,207 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "ODP_FIR": {
+ "instances": {
+ "0": "0x08013000",
+ "1": "0x08013400"
+ }
+ },
+ "ODP_FIR_MASK": {
+ "instances": {
+ "0": "0x08013002",
+ "1": "0x08013402"
+ }
+ },
+ "ODP_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08013004",
+ "1": "0x08013404"
+ }
+ },
+ "ODP_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08013005",
+ "1": "0x08013405"
+ }
+ },
+ "ODP_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08013006",
+ "1": "0x08013406"
+ }
+ },
+ "ODP_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08013007",
+ "1": "0x08013407"
+ }
+ },
+ "ODP_FIR_WOF": {
+ "instances": {
+ "0": "0x08013008",
+ "1": "0x08013408"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "ODP_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "SCOM2APB state machine parity error"
+ },
+ "2": {
+ "desc": "Write data parity error"
+ },
+ "3": {
+ "desc": "APB responder error"
+ },
+ "4": {
+ "desc": "ODPCTRL register parity error"
+ },
+ "5": {
+ "desc": "PHY error"
+ },
+ "6": {
+ "desc": "PHY Sticky Unlock Error"
+ },
+ "7": {
+ "desc": "Bsi Interrupt occurred"
+ },
+ "8": {
+ "desc": "ANIB Receive Error"
+ },
+ "9": {
+ "desc": "Parity Error (even parity) for D5ACSM Channel 1 Parity Error"
+ },
+ "10": {
+ "desc": "Parity Error (even parity) for D5ACSM Channel 0 Parity Error"
+ },
+ "11": {
+ "desc": "PHY RX FIFO Check Error"
+ },
+ "12": {
+ "desc": "PHY RX TX PPT Error"
+ },
+ "13": {
+ "desc": "PHY ECC Error ARC ECC Interrupt"
+ },
+ "14:18": {
+ "desc": "Reserved Firmware Interrupt"
+ },
+ "19": {
+ "desc": "PHY Training Failure Interrupt"
+ },
+ "20": {
+ "desc": "PHY Initialization Complete Interrupt"
+ },
+ "21": {
+ "desc": "PHY Training Complete Interrupt"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_rdf_fir.json b/chip_data/odyssey/node_rdf_fir.json
new file mode 100644
index 0000000..cd418aa
--- /dev/null
+++ b/chip_data/odyssey/node_rdf_fir.json
@@ -0,0 +1,590 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "RDF_FIR": {
+ "instances": {
+ "0": "0x08011800",
+ "1": "0x08012800"
+ }
+ },
+ "RDF_FIR_MASK": {
+ "instances": {
+ "0": "0x08011802",
+ "1": "0x08012802"
+ }
+ },
+ "RDF_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011804",
+ "1": "0x08012804"
+ }
+ },
+ "RDF_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011805",
+ "1": "0x08012805"
+ }
+ },
+ "RDF_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011806",
+ "1": "0x08012806"
+ }
+ },
+ "RDF_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011807",
+ "1": "0x08012807"
+ }
+ },
+ "RDF_FIR_WOF": {
+ "instances": {
+ "0": "0x08011808",
+ "1": "0x08012808"
+ }
+ },
+ "RDF_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801180E",
+ "1": "0x0801280E"
+ }
+ },
+ "RDF_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801180F",
+ "1": "0x0801280F"
+ }
+ },
+ "MSR": {
+ "instances": {
+ "0": "0x0801180C",
+ "1": "0x0801280C"
+ }
+ },
+ "HW_MS0": {
+ "instances": {
+ "0": "0x08011810",
+ "1": "0x08012810"
+ }
+ },
+ "HW_MS1": {
+ "instances": {
+ "0": "0x08011811",
+ "1": "0x08012811"
+ }
+ },
+ "HW_MS2": {
+ "instances": {
+ "0": "0x08011812",
+ "1": "0x08012812"
+ }
+ },
+ "HW_MS3": {
+ "instances": {
+ "0": "0x08011813",
+ "1": "0x08012813"
+ }
+ },
+ "HW_MS4": {
+ "instances": {
+ "0": "0x08011814",
+ "1": "0x08012814"
+ }
+ },
+ "HW_MS5": {
+ "instances": {
+ "0": "0x08011815",
+ "1": "0x08012815"
+ }
+ },
+ "HW_MS6": {
+ "instances": {
+ "0": "0x08011816",
+ "1": "0x08012816"
+ }
+ },
+ "HW_MS7": {
+ "instances": {
+ "0": "0x08011817",
+ "1": "0x08012817"
+ }
+ },
+ "FW_MS0": {
+ "instances": {
+ "0": "0x08011818",
+ "1": "0x08012818"
+ }
+ },
+ "FW_MS1": {
+ "instances": {
+ "0": "0x08011819",
+ "1": "0x08012819"
+ }
+ },
+ "FW_MS2": {
+ "instances": {
+ "0": "0x0801181A",
+ "1": "0x0801281A"
+ }
+ },
+ "FW_MS3": {
+ "instances": {
+ "0": "0x0801181B",
+ "1": "0x0801281B"
+ }
+ },
+ "FW_MS4": {
+ "instances": {
+ "0": "0x0801181C",
+ "1": "0x0801281C"
+ }
+ },
+ "FW_MS5": {
+ "instances": {
+ "0": "0x0801181D",
+ "1": "0x0801281D"
+ }
+ },
+ "FW_MS6": {
+ "instances": {
+ "0": "0x0801181E",
+ "1": "0x0801281E"
+ }
+ },
+ "FW_MS7": {
+ "instances": {
+ "0": "0x0801181F",
+ "1": "0x0801281F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "RDF_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal SCOM error"
+ },
+ "1": {
+ "desc": "Mainline read MPE on rank 0"
+ },
+ "2": {
+ "desc": "Mainline read MPE on rank 1"
+ },
+ "3": {
+ "desc": "Mainline read MPE on rank 2"
+ },
+ "4": {
+ "desc": "Mainline read MPE on rank 3"
+ },
+ "5": {
+ "desc": "Mainline read MPE on rank 4"
+ },
+ "6": {
+ "desc": "Mainline read MPE on rank 5"
+ },
+ "7": {
+ "desc": "Mainline read MPE on rank 6"
+ },
+ "8": {
+ "desc": "Mainline read MPE on rank 7"
+ },
+ "9": {
+ "desc": "Mainline read NCE"
+ },
+ "10": {
+ "desc": "Mainline read TCE"
+ },
+ "11": {
+ "desc": "Mainline read SCE"
+ },
+ "12": {
+ "desc": "Mainline read MCE"
+ },
+ "13": {
+ "desc": "Mainline read SUE"
+ },
+ "14": {
+ "desc": "Mainline read AUE"
+ },
+ "15": {
+ "desc": "Mainline read UE"
+ },
+ "16": {
+ "desc": "Mainline read RCD"
+ },
+ "17": {
+ "desc": "Mainline read IAUE"
+ },
+ "18": {
+ "desc": "Mainline read IUE"
+ },
+ "19": {
+ "desc": "Mainline read IRCD"
+ },
+ "20": {
+ "desc": "Mainline read IMPE"
+ },
+ "21": {
+ "desc": "Maintenance MPE on rank 0"
+ },
+ "22": {
+ "desc": "Maintenance MPE on rank 1"
+ },
+ "23": {
+ "desc": "Maintenance MPE on rank 2"
+ },
+ "24": {
+ "desc": "Maintenance MPE on rank 3"
+ },
+ "25": {
+ "desc": "Maintenance MPE on rank 4"
+ },
+ "26": {
+ "desc": "Maintenance MPE on rank 5"
+ },
+ "27": {
+ "desc": "Maintenance MPE on rank 6"
+ },
+ "28": {
+ "desc": "Maintenance MPE on rank 7"
+ },
+ "29": {
+ "desc": "Maintenance NCE"
+ },
+ "30": {
+ "desc": "Maintenance TCE"
+ },
+ "31": {
+ "desc": "Maintenance SCE"
+ },
+ "32": {
+ "desc": "Maintenance MCE"
+ },
+ "33": {
+ "desc": "Maintenance SUE"
+ },
+ "34": {
+ "desc": "Maintenance AUE"
+ },
+ "35": {
+ "desc": "Maintenance UE"
+ },
+ "36": {
+ "desc": "Maintenance RCD"
+ },
+ "37": {
+ "desc": "Maintenance IAUE"
+ },
+ "38": {
+ "desc": "Maintenance IUE"
+ },
+ "39": {
+ "desc": "Maintenance IRCD"
+ },
+ "40": {
+ "desc": "Maintenance IMPE"
+ },
+ "41": {
+ "desc": "RDDATA valid error"
+ },
+ "42": {
+ "desc": "SCOM status register parity error"
+ },
+ "43": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "44": {
+ "desc": "SCOM unrecoverable register parity error"
+ },
+ "45": {
+ "desc": "ECC corrector internal parity error"
+ },
+ "46": {
+ "desc": "Read buffer ECC CHK Cor CE DW0 Detected"
+ },
+ "47": {
+ "desc": "Read buffer ECC CHK Cor CE DW1 Detected"
+ },
+ "48": {
+ "desc": "Read buffer ECC CHK Cor UE DW0 Detected"
+ },
+ "49": {
+ "desc": "Read buffer ECC CHK Cor UE DW1 Detected"
+ },
+ "50": {
+ "desc": "Prefetch buffer ECC CHK Cor CE DW0 Detected"
+ },
+ "51": {
+ "desc": "Prefetch buffer ECC CHK Cor CE DW1 Detected"
+ },
+ "52": {
+ "desc": "Prefetch buffer ECC CHK Cor UE DW0 Detected"
+ },
+ "53": {
+ "desc": "Prefetch buffer ECC CHK Cor UE DW1 Detected"
+ },
+ "54": {
+ "desc": "Parity error on TLXT to RDF read buffer interface"
+ },
+ "55": {
+ "desc": "Parity error on TLXT to RDF read prefetch interface"
+ },
+ "56:60": {
+ "desc": "reserved"
+ },
+ "61": {
+ "desc": "SCOM register parity error for debug/wat control"
+ },
+ "62": {
+ "desc": "Reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "RDF_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "RDF_FIR": [
+ {
+ "reg_name": "RDF_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "RDF_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "MSR",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS3",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS4",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS5",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS6",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS7",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS3",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS4",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS5",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS6",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS7",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_srq_fir.json b/chip_data/odyssey/node_srq_fir.json
new file mode 100644
index 0000000..5be8898
--- /dev/null
+++ b/chip_data/odyssey/node_srq_fir.json
@@ -0,0 +1,373 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "SRQ_FIR": {
+ "instances": {
+ "0": "0x08011000"
+ }
+ },
+ "SRQ_FIR_MASK": {
+ "instances": {
+ "0": "0x08011002"
+ }
+ },
+ "SRQ_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011004"
+ }
+ },
+ "SRQ_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011005"
+ }
+ },
+ "SRQ_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011006"
+ }
+ },
+ "SRQ_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011007"
+ }
+ },
+ "SRQ_FIR_WOF": {
+ "instances": {
+ "0": "0x08011008"
+ }
+ },
+ "SRQ_ERR_RPT": {
+ "instances": {
+ "0": "0x0801101C"
+ }
+ },
+ "MBXLT0": {
+ "instances": {
+ "0": "0x08011012"
+ }
+ },
+ "MBXLT1": {
+ "instances": {
+ "0": "0x08011013"
+ }
+ },
+ "MBXLT2": {
+ "instances": {
+ "0": "0x08011014"
+ }
+ },
+ "MBXLT3": {
+ "instances": {
+ "0": "0x08011021"
+ }
+ },
+ "WESR": {
+ "instances": {
+ "0": "0x08011C06"
+ }
+ },
+ "SRQ_ERR_RPT_HOLD": {
+ "instances": {
+ "0": "0x08011C07"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "SRQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "SRQ nonrecoverable parity error"
+ },
+ "2": {
+ "desc": "refresh overrun port0"
+ },
+ "3": {
+ "desc": "WAT error"
+ },
+ "4": {
+ "desc": "RCD parity error port0"
+ },
+ "5": {
+ "desc": "MCB control logic Error in NCF"
+ },
+ "6": {
+ "desc": "Emergency throttle engaged"
+ },
+ "7": {
+ "desc": "DSM errors port0"
+ },
+ "8": {
+ "desc": "event_n was active on the DDR interface port0"
+ },
+ "9": {
+ "desc": "WRQ or RRQ is in a hung state port0"
+ },
+ "10": {
+ "desc": "state machine one hot error port0"
+ },
+ "11": {
+ "desc": "ROQ errors port0"
+ },
+ "12": {
+ "desc": "Address parity error seen internal to sequencer on read or write command port0"
+ },
+ "13": {
+ "desc": "port0 has failed due to a persistent retry"
+ },
+ "14": {
+ "desc": "informational register parity error"
+ },
+ "15": {
+ "desc": "soft error reported from error report register"
+ },
+ "16": {
+ "desc": "WDF unrecoverable mainline error"
+ },
+ "17": {
+ "desc": "WDF mmio error"
+ },
+ "18": {
+ "desc": "WDF array UE on mainline operations (SUE put in mem)"
+ },
+ "19": {
+ "desc": "WDF mainline dataflow error (SUE not reliably put in mem)"
+ },
+ "20": {
+ "desc": "WDF scom register parity error, affecting mainline config"
+ },
+ "21": {
+ "desc": "WDF scom register parity error, affecting scom ops only"
+ },
+ "22": {
+ "desc": "WDF SCOM fsm parity error"
+ },
+ "23": {
+ "desc": "WDF write buffer array CE"
+ },
+ "24": {
+ "desc": "refresh management CE port0"
+ },
+ "25": {
+ "desc": "refresh management RAA counter UE port0"
+ },
+ "26": {
+ "desc": "NCF fifo error port0"
+ },
+ "27": {
+ "desc": "NCF fifo error port1"
+ },
+ "28": {
+ "desc": "memcntl cmd xstop"
+ },
+ "29": {
+ "desc": "SRQ recoverable parity error"
+ },
+ "30": {
+ "desc": "DFI error port0"
+ },
+ "31": {
+ "desc": "xlat addr error port0"
+ },
+ "32": {
+ "desc": "refresh overrun port1"
+ },
+ "33": {
+ "desc": "RCD parity error port1"
+ },
+ "34": {
+ "desc": "DFI error port1"
+ },
+ "35": {
+ "desc": "event_n was active on the DDR interface port1"
+ },
+ "36": {
+ "desc": "WRQ or RRQ is in a hung state port1"
+ },
+ "37": {
+ "desc": "state machine one hot error port1"
+ },
+ "38": {
+ "desc": "ROQ errors port1"
+ },
+ "39": {
+ "desc": "Address parity error seen internal to sequencer on read or write command port1"
+ },
+ "40": {
+ "desc": "port1 has failed due to a persistent retry"
+ },
+ "41": {
+ "desc": "refresh management CE port1"
+ },
+ "42": {
+ "desc": "refresh management RAA counter UE port1"
+ },
+ "43": {
+ "desc": "xlat addr error port1"
+ },
+ "44": {
+ "desc": "check on ccs in progress bit"
+ },
+ "45": {
+ "desc": "DSM errors port1"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "SRQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "SRQ_FIR": [
+ {
+ "reg_name": "SRQ_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "WESR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SRQ_ERR_RPT_HOLD",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_tlx_fir.json b/chip_data/odyssey/node_tlx_fir.json
new file mode 100644
index 0000000..67ccaad
--- /dev/null
+++ b/chip_data/odyssey/node_tlx_fir.json
@@ -0,0 +1,330 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "TLX_FIR": {
+ "instances": {
+ "0": "0x08012000"
+ }
+ },
+ "TLX_FIR_MASK": {
+ "instances": {
+ "0": "0x08012002"
+ }
+ },
+ "TLX_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08012004"
+ }
+ },
+ "TLX_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08012005"
+ }
+ },
+ "TLX_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08012006"
+ }
+ },
+ "TLX_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08012007"
+ }
+ },
+ "TLX_FIR_WOF": {
+ "instances": {
+ "0": "0x08012008"
+ }
+ },
+ "SRQ_ROQ_CTL_0": {
+ "instances": {
+ "0": "0x0801100F"
+ }
+ },
+ "TLX_CFG_0": {
+ "instances": {
+ "0": "0x0801200C"
+ }
+ },
+ "TLX_CFG_1": {
+ "instances": {
+ "0": "0x0801200D"
+ }
+ },
+ "TLX_CFG_2": {
+ "instances": {
+ "0": "0x0801200E"
+ }
+ },
+ "TLX_CFG_3": {
+ "instances": {
+ "0": "0x0801200F"
+ }
+ },
+ "TLX_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801201C"
+ }
+ },
+ "TLX_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801201D"
+ }
+ },
+ "TLX_ERR_RPT_2": {
+ "instances": {
+ "0": "0x0801201E"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TLX_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "TLXT control register parity error"
+ },
+ "2": {
+ "desc": "TLX VC0 return credit overflow"
+ },
+ "3": {
+ "desc": "TLX VC3 return credit overflow"
+ },
+ "4": {
+ "desc": "TLX DCP0 return credit overflow"
+ },
+ "5": {
+ "desc": "TLX DCP3 return credit overflow"
+ },
+ "6": {
+ "desc": "TLXC error"
+ },
+ "7": {
+ "desc": "TLXC parity error"
+ },
+ "8": {
+ "desc": "TLXT config parity error"
+ },
+ "9": {
+ "desc": "TLXT response parity error"
+ },
+ "10": {
+ "desc": "TLXT framer control parity error"
+ },
+ "11": {
+ "desc": "TLXT Xarb control error"
+ },
+ "12": {
+ "desc": "TLXT DLX interface error"
+ },
+ "13": {
+ "desc": "TLX info register parity error"
+ },
+ "14": {
+ "desc": "TLX reorder queue error"
+ },
+ "15": {
+ "desc": "TLXT invalid configuration"
+ },
+ "16": {
+ "desc": "TLXR is dropping commands after a fatal error"
+ },
+ "17": {
+ "desc": "Malformed OC packet received"
+ },
+ "18": {
+ "desc": "Protocol error detected in OC downstream sequence"
+ },
+ "19": {
+ "desc": "Legal OC command not supported"
+ },
+ "20": {
+ "desc": "Legal OC command length not supported"
+ },
+ "21": {
+ "desc": "TLXR OC Misaligned"
+ },
+ "22": {
+ "desc": "MMIO returned non-zero response to a write"
+ },
+ "23": {
+ "desc": "Hardware error in TLXR control logic"
+ },
+ "24": {
+ "desc": "TLXR Info Event"
+ },
+ "25": {
+ "desc": "TLXR detected internal error"
+ },
+ "26": {
+ "desc": "TLXR Threshold errors"
+ },
+ "27": {
+ "desc": "Trace_Stop from TLXR"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "TLX_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "TLX_FIR": [
+ {
+ "reg_name": "SRQ_ROQ_CTL_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_tp_local_fir.json b/chip_data/odyssey/node_tp_local_fir.json
new file mode 100644
index 0000000..55c5ea8
--- /dev/null
+++ b/chip_data/odyssey/node_tp_local_fir.json
@@ -0,0 +1,251 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "TP_LOCAL_FIR": {
+ "instances": {
+ "0": "0x01040100"
+ }
+ },
+ "TP_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x01040102"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x01040104"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x01040105"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x01040106"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x01040107"
+ }
+ },
+ "TP_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x01040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TP_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR/LFIR parity error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - clock control error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM Access Error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - various errors"
+ },
+ "7": {
+ "desc": "DBG - SCOM parity fail"
+ },
+ "8": {
+ "desc": "unused"
+ },
+ "9": {
+ "desc": "FSI errors (OTP, I2C)"
+ },
+ "10": {
+ "desc": "Trace00 - SCOM parity error"
+ },
+ "11": {
+ "desc": "ITR - FMU error"
+ },
+ "12": {
+ "desc": "ITR - PCB error"
+ },
+ "13": {
+ "desc": "PCB master - timeout"
+ },
+ "14": {
+ "desc": "I2CM - parity errors"
+ },
+ "15:17": {
+ "desc": "unused"
+ },
+ "18": {
+ "desc": "Error reported from one or more PCB responder - PLL lock/unlock"
+ },
+ "19": {
+ "desc": "SBE - PPE internal hardware error"
+ },
+ "20": {
+ "desc": "SBE - PPE external hardware error"
+ },
+ "21": {
+ "desc": "SBE - PPE code error"
+ },
+ "22": {
+ "desc": "SBE - PPE debug code breakpoint"
+ },
+ "23": {
+ "desc": "SBE - PPE in halted state"
+ },
+ "24": {
+ "desc": "SBE - PPE watchdog timeout"
+ },
+ "25:26": {
+ "desc": "SBE - unused"
+ },
+ "27": {
+ "desc": "SBE - PPE triggers DBG"
+ },
+ "28:29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "PCB controller - multicast group member count underrun"
+ },
+ "31": {
+ "desc": "PCB controller - parity error"
+ },
+ "32:35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "PIBMEM"
+ },
+ "37": {
+ "desc": "PIBMEM"
+ },
+ "38:44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "SPI controller 0 error"
+ },
+ "46:62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "external local checkstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/eq_spattn.json b/chip_data/p10_10/eq_spattn.json
new file mode 100644
index 0000000..3172d1e
--- /dev/null
+++ b/chip_data/p10_10/eq_spattn.json
@@ -0,0 +1,502 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CORE_THREAD_STATE": {
+ "instances": {
+ "0": "0x20028412",
+ "1": "0x20024412",
+ "2": "0x20022412",
+ "3": "0x20021412",
+ "4": "0x21028412",
+ "5": "0x21024412",
+ "6": "0x21022412",
+ "7": "0x21021412",
+ "8": "0x22028412",
+ "9": "0x22024412",
+ "10": "0x22022412",
+ "11": "0x22021412",
+ "12": "0x23028412",
+ "13": "0x23024412",
+ "14": "0x23022412",
+ "15": "0x23021412",
+ "16": "0x24028412",
+ "17": "0x24024412",
+ "18": "0x24022412",
+ "19": "0x24021412",
+ "20": "0x25028412",
+ "21": "0x25024412",
+ "22": "0x25022412",
+ "23": "0x25021412",
+ "24": "0x26028412",
+ "25": "0x26024412",
+ "26": "0x26022412",
+ "27": "0x26021412",
+ "28": "0x27028412",
+ "29": "0x27024412",
+ "30": "0x27022412",
+ "31": "0x27021412"
+ }
+ },
+ "EQ_SPATTN": {
+ "instances": {
+ "0": "0x20028499",
+ "1": "0x20024499",
+ "2": "0x20022499",
+ "3": "0x20021499",
+ "4": "0x21028499",
+ "5": "0x21024499",
+ "6": "0x21022499",
+ "7": "0x21021499",
+ "8": "0x22028499",
+ "9": "0x22024499",
+ "10": "0x22022499",
+ "11": "0x22021499",
+ "12": "0x23028499",
+ "13": "0x23024499",
+ "14": "0x23022499",
+ "15": "0x23021499",
+ "16": "0x24028499",
+ "17": "0x24024499",
+ "18": "0x24022499",
+ "19": "0x24021499",
+ "20": "0x25028499",
+ "21": "0x25024499",
+ "22": "0x25022499",
+ "23": "0x25021499",
+ "24": "0x26028499",
+ "25": "0x26024499",
+ "26": "0x26022499",
+ "27": "0x26021499",
+ "28": "0x27028499",
+ "29": "0x27024499",
+ "30": "0x27022499",
+ "31": "0x27021499"
+ }
+ },
+ "EQ_SPATTN_MASK": {
+ "instances": {
+ "0": "0x2002849A",
+ "1": "0x2002449A",
+ "2": "0x2002249A",
+ "3": "0x2002149A",
+ "4": "0x2102849A",
+ "5": "0x2102449A",
+ "6": "0x2102249A",
+ "7": "0x2102149A",
+ "8": "0x2202849A",
+ "9": "0x2202449A",
+ "10": "0x2202249A",
+ "11": "0x2202149A",
+ "12": "0x2302849A",
+ "13": "0x2302449A",
+ "14": "0x2302249A",
+ "15": "0x2302149A",
+ "16": "0x2402849A",
+ "17": "0x2402449A",
+ "18": "0x2402249A",
+ "19": "0x2402149A",
+ "20": "0x2502849A",
+ "21": "0x2502449A",
+ "22": "0x2502249A",
+ "23": "0x2502149A",
+ "24": "0x2602849A",
+ "25": "0x2602449A",
+ "26": "0x2602249A",
+ "27": "0x2602149A",
+ "28": "0x2702849A",
+ "29": "0x2702449A",
+ "30": "0x2702249A",
+ "31": "0x2702149A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_CORE_THREAD_STATE": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CORE_THREAD_STATE"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000001"
+ }
+ ]
+ },
+ "shift_value": 63
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CORE_THREAD_STATE"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000001"
+ }
+ ]
+ },
+ "shift_value": 62
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "EQ_SPATTN normal core mode",
+ "child_node": {
+ "name": "EQ_SPATTN_NORMAL",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ },
+ "1": {
+ "desc": "EQ_SPATTN fused core mode",
+ "child_node": {
+ "name": "EQ_SPATTN_FUSED",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ }
+ }
+ },
+ "EQ_SPATTN_NORMAL": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0xFFFF000000000000"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "lt0_spr_instr_stop"
+ },
+ "1": {
+ "desc": "lt0_attn_complete"
+ },
+ "2": {
+ "desc": "lt0_core_checkstop_recovery_handshake"
+ },
+ "3": {
+ "desc": "lt0_core_code_to_sp"
+ },
+ "4": {
+ "desc": "lt1_spr_instr_stop"
+ },
+ "5": {
+ "desc": "lt1_attn_complete"
+ },
+ "6": {
+ "desc": "lt1_core_checkstop_recovery_handshake"
+ },
+ "7": {
+ "desc": "lt1_core_code_to_sp"
+ },
+ "8": {
+ "desc": "lt2_spr_instr_stop"
+ },
+ "9": {
+ "desc": "lt2_attn_complete"
+ },
+ "10": {
+ "desc": "lt2_core_checkstop_recovery_handshake"
+ },
+ "11": {
+ "desc": "lt2_core_code_to_sp"
+ },
+ "12": {
+ "desc": "lt3_spr_instr_stop"
+ },
+ "13": {
+ "desc": "lt3_attn_complete"
+ },
+ "14": {
+ "desc": "lt3_core_checkstop_recovery_handshake"
+ },
+ "15": {
+ "desc": "lt3_core_code_to_sp"
+ }
+ }
+ },
+ "EQ_SPATTN_FUSED": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28,
+ 30
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0xF0F0F0F000000000"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29,
+ 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0F0F0F0F00000000"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "lt0_spr_instr_stop"
+ },
+ "1": {
+ "desc": "lt0_attn_complete"
+ },
+ "2": {
+ "desc": "lt0_core_checkstop_recovery_handshake"
+ },
+ "3": {
+ "desc": "lt0_core_code_to_sp"
+ },
+ "4": {
+ "desc": "lt1_spr_instr_stop"
+ },
+ "5": {
+ "desc": "lt1_attn_complete"
+ },
+ "6": {
+ "desc": "lt1_core_checkstop_recovery_handshake"
+ },
+ "7": {
+ "desc": "lt1_core_code_to_sp"
+ },
+ "8": {
+ "desc": "lt2_spr_instr_stop"
+ },
+ "9": {
+ "desc": "lt2_attn_complete"
+ },
+ "10": {
+ "desc": "lt2_core_checkstop_recovery_handshake"
+ },
+ "11": {
+ "desc": "lt2_core_code_to_sp"
+ },
+ "12": {
+ "desc": "lt3_spr_instr_stop"
+ },
+ "13": {
+ "desc": "lt3_attn_complete"
+ },
+ "14": {
+ "desc": "lt3_core_checkstop_recovery_handshake"
+ },
+ "15": {
+ "desc": "lt3_core_code_to_sp"
+ },
+ "16": {
+ "desc": "lt4_spr_instr_stop"
+ },
+ "17": {
+ "desc": "lt4_attn_complete"
+ },
+ "18": {
+ "desc": "lt4_core_checkstop_recovery_handshake"
+ },
+ "19": {
+ "desc": "lt4_core_code_to_sp"
+ },
+ "20": {
+ "desc": "lt5_spr_instr_stop"
+ },
+ "21": {
+ "desc": "lt5_attn_complete"
+ },
+ "22": {
+ "desc": "lt5_core_checkstop_recovery_handshake"
+ },
+ "23": {
+ "desc": "lt5_core_code_to_sp"
+ },
+ "24": {
+ "desc": "lt6_spr_instr_stop"
+ },
+ "25": {
+ "desc": "lt6_attn_complete"
+ },
+ "26": {
+ "desc": "lt6_core_checkstop_recovery_handshake"
+ },
+ "27": {
+ "desc": "lt6_core_code_to_sp"
+ },
+ "28": {
+ "desc": "lt7_spr_instr_stop"
+ },
+ "29": {
+ "desc": "lt7_attn_complete"
+ },
+ "30": {
+ "desc": "lt7_core_checkstop_recovery_handshake"
+ },
+ "31": {
+ "desc": "lt7_core_code_to_sp"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/iohs_dlp_phy_config.json b/chip_data/p10_10/iohs_dlp_phy_config.json
new file mode 100644
index 0000000..6a10a84
--- /dev/null
+++ b/chip_data/p10_10/iohs_dlp_phy_config.json
@@ -0,0 +1,1317 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "IOHS_DLP_FIR": {
+ "instances": {
+ "0": "0x18011000",
+ "1": "0x19011000",
+ "2": "0x1A011000",
+ "3": "0x1B011000",
+ "4": "0x1C011000",
+ "5": "0x1D011000",
+ "6": "0x1E011000",
+ "7": "0x1F011000"
+ }
+ },
+ "IOHS_DLP_FIR_MASK": {
+ "instances": {
+ "0": "0x18011003",
+ "1": "0x19011003",
+ "2": "0x1A011003",
+ "3": "0x1B011003",
+ "4": "0x1C011003",
+ "5": "0x1D011003",
+ "6": "0x1E011003",
+ "7": "0x1F011003"
+ }
+ },
+ "IOHS_DLP_FIR_ACT0": {
+ "instances": {
+ "0": "0x18011006",
+ "1": "0x19011006",
+ "2": "0x1A011006",
+ "3": "0x1B011006",
+ "4": "0x1C011006",
+ "5": "0x1D011006",
+ "6": "0x1E011006",
+ "7": "0x1F011006"
+ }
+ },
+ "IOHS_DLP_FIR_ACT1": {
+ "instances": {
+ "0": "0x18011007",
+ "1": "0x19011007",
+ "2": "0x1A011007",
+ "3": "0x1B011007",
+ "4": "0x1C011007",
+ "5": "0x1D011007",
+ "6": "0x1E011007",
+ "7": "0x1F011007"
+ }
+ },
+ "IOHS_DLP_FIR_WOF": {
+ "instances": {
+ "0": "0x18011008",
+ "1": "0x19011008",
+ "2": "0x1A011008",
+ "3": "0x1B011008",
+ "4": "0x1C011008",
+ "5": "0x1D011008",
+ "6": "0x1E011008",
+ "7": "0x1F011008"
+ }
+ },
+ "IOHS_DLP_CONFIG": {
+ "instances": {
+ "0": "0x1801100A",
+ "1": "0x1901100A",
+ "2": "0x1A01100A",
+ "3": "0x1B01100A",
+ "4": "0x1C01100A",
+ "5": "0x1D01100A",
+ "6": "0x1E01100A",
+ "7": "0x1F01100A"
+ }
+ },
+ "IOHS_DLP_CONTROL": {
+ "instances": {
+ "0": "0x1801100B",
+ "1": "0x1901100B",
+ "2": "0x1A01100B",
+ "3": "0x1B01100B",
+ "4": "0x1C01100B",
+ "5": "0x1D01100B",
+ "6": "0x1E01100B",
+ "7": "0x1F01100B"
+ }
+ },
+ "IOHS_DLP_PHY_CONFIG": {
+ "instances": {
+ "0": "0x1801100C",
+ "1": "0x1901100C",
+ "2": "0x1A01100C",
+ "3": "0x1B01100C",
+ "4": "0x1C01100C",
+ "5": "0x1D01100C",
+ "6": "0x1E01100C",
+ "7": "0x1F01100C"
+ }
+ },
+ "IOHS_DLP_SEC_CONFIG": {
+ "instances": {
+ "0": "0x1801100D",
+ "1": "0x1901100D",
+ "2": "0x1A01100D",
+ "3": "0x1B01100D",
+ "4": "0x1C01100D",
+ "5": "0x1D01100D",
+ "6": "0x1E01100D",
+ "7": "0x1F01100D"
+ }
+ },
+ "IOHS_DLP_OPTICAL_CONFIG": {
+ "instances": {
+ "0": "0x1801100F",
+ "1": "0x1901100F",
+ "2": "0x1A01100F",
+ "3": "0x1B01100F",
+ "4": "0x1C01100F",
+ "5": "0x1D01100F",
+ "6": "0x1E01100F",
+ "7": "0x1F01100F"
+ }
+ },
+ "IOHS_DLP_LINK0_TX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011010",
+ "1": "0x19011010",
+ "2": "0x1A011010",
+ "3": "0x1B011010",
+ "4": "0x1C011010",
+ "5": "0x1D011010",
+ "6": "0x1E011010",
+ "7": "0x1F011010"
+ }
+ },
+ "IOHS_DLP_LINK1_TX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011011",
+ "1": "0x19011011",
+ "2": "0x1A011011",
+ "3": "0x1B011011",
+ "4": "0x1C011011",
+ "5": "0x1D011011",
+ "6": "0x1E011011",
+ "7": "0x1F011011"
+ }
+ },
+ "IOHS_DLP_LINK0_RX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011012",
+ "1": "0x19011012",
+ "2": "0x1A011012",
+ "3": "0x1B011012",
+ "4": "0x1C011012",
+ "5": "0x1D011012",
+ "6": "0x1E011012",
+ "7": "0x1F011012"
+ }
+ },
+ "IOHS_DLP_LINK1_RX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011013",
+ "1": "0x19011013",
+ "2": "0x1A011013",
+ "3": "0x1B011013",
+ "4": "0x1C011013",
+ "5": "0x1D011013",
+ "6": "0x1E011013",
+ "7": "0x1F011013"
+ }
+ },
+ "IOHS_DLP_LINK0_INFO": {
+ "instances": {
+ "0": "0x18011014",
+ "1": "0x19011014",
+ "2": "0x1A011014",
+ "3": "0x1B011014",
+ "4": "0x1C011014",
+ "5": "0x1D011014",
+ "6": "0x1E011014",
+ "7": "0x1F011014"
+ }
+ },
+ "IOHS_DLP_LINK1_INFO": {
+ "instances": {
+ "0": "0x18011015",
+ "1": "0x19011015",
+ "2": "0x1A011015",
+ "3": "0x1B011015",
+ "4": "0x1C011015",
+ "5": "0x1D011015",
+ "6": "0x1E011015",
+ "7": "0x1F011015"
+ }
+ },
+ "IOHS_DLP_LINK0_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011016",
+ "1": "0x19011016",
+ "2": "0x1A011016",
+ "3": "0x1B011016",
+ "4": "0x1C011016",
+ "5": "0x1D011016",
+ "6": "0x1E011016",
+ "7": "0x1F011016"
+ }
+ },
+ "IOHS_DLP_LINK1_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011017",
+ "1": "0x19011017",
+ "2": "0x1A011017",
+ "3": "0x1B011017",
+ "4": "0x1C011017",
+ "5": "0x1D011017",
+ "6": "0x1E011017",
+ "7": "0x1F011017"
+ }
+ },
+ "IOHS_DLP_REPLAY_THRESHOLD": {
+ "instances": {
+ "0": "0x18011018",
+ "1": "0x19011018",
+ "2": "0x1A011018",
+ "3": "0x1B011018",
+ "4": "0x1C011018",
+ "5": "0x1D011018",
+ "6": "0x1E011018",
+ "7": "0x1F011018"
+ }
+ },
+ "IOHS_DLP_SL_ECC_THRESHOLD": {
+ "instances": {
+ "0": "0x18011019",
+ "1": "0x19011019",
+ "2": "0x1A011019",
+ "3": "0x1B011019",
+ "4": "0x1C011019",
+ "5": "0x1D011019",
+ "6": "0x1E011019",
+ "7": "0x1F011019"
+ }
+ },
+ "IOHS_DLP_LINK0_SYN_CAPTURE": {
+ "instances": {
+ "0": "0x18011022",
+ "1": "0x19011022",
+ "2": "0x1A011022",
+ "3": "0x1B011022",
+ "4": "0x1C011022",
+ "5": "0x1D011022",
+ "6": "0x1E011022",
+ "7": "0x1F011022"
+ }
+ },
+ "IOHS_DLP_LINK1_SYN_CAPTURE": {
+ "instances": {
+ "0": "0x18011023",
+ "1": "0x19011023",
+ "2": "0x1A011023",
+ "3": "0x1B011023",
+ "4": "0x1C011023",
+ "5": "0x1D011023",
+ "6": "0x1E011023",
+ "7": "0x1F011023"
+ }
+ },
+ "IOHS_DLP_LINK0_EDPL_STATUS": {
+ "instances": {
+ "0": "0x18011024",
+ "1": "0x19011024",
+ "2": "0x1A011024",
+ "3": "0x1B011024",
+ "4": "0x1C011024",
+ "5": "0x1D011024",
+ "6": "0x1E011024",
+ "7": "0x1F011024"
+ }
+ },
+ "IOHS_DLP_LINK1_EDPL_STATUS": {
+ "instances": {
+ "0": "0x18011025",
+ "1": "0x19011025",
+ "2": "0x1A011025",
+ "3": "0x1B011025",
+ "4": "0x1C011025",
+ "5": "0x1D011025",
+ "6": "0x1E011025",
+ "7": "0x1F011025"
+ }
+ },
+ "IOHS_DLP_LINK0_QUALITY": {
+ "instances": {
+ "0": "0x18011026",
+ "1": "0x19011026",
+ "2": "0x1A011026",
+ "3": "0x1B011026",
+ "4": "0x1C011026",
+ "5": "0x1D011026",
+ "6": "0x1E011026",
+ "7": "0x1F011026"
+ }
+ },
+ "IOHS_DLP_LINK1_QUALITY": {
+ "instances": {
+ "0": "0x18011027",
+ "1": "0x19011027",
+ "2": "0x1A011027",
+ "3": "0x1B011027",
+ "4": "0x1C011027",
+ "5": "0x1D011027",
+ "6": "0x1E011027",
+ "7": "0x1F011027"
+ }
+ },
+ "IOHS_DLP_DLL_STATUS": {
+ "instances": {
+ "0": "0x18011028",
+ "1": "0x19011028",
+ "2": "0x1A011028",
+ "3": "0x1B011028",
+ "4": "0x1C011028",
+ "5": "0x1D011028",
+ "6": "0x1E011028",
+ "7": "0x1F011028"
+ }
+ },
+ "IOHS_DLP_MISC_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011029",
+ "1": "0x19011029",
+ "2": "0x1A011029",
+ "3": "0x1B011029",
+ "4": "0x1C011029",
+ "5": "0x1D011029",
+ "6": "0x1E011029",
+ "7": "0x1F011029"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "IOHS_DLP_PHY_CONFIG": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "62": {
+ "desc": "Attention from IOHS_DLP_FIR in OpenCAPI mode",
+ "child_node": {
+ "name": "IOHS_DLP_FIR_OC",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "63": {
+ "desc": "Attention from IOHS_DLP_FIR in SMP mode",
+ "child_node": {
+ "name": "IOHS_DLP_FIR_SMP",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "IOHS_DLP_FIR_OC": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "unused"
+ },
+ "1": {
+ "desc": "unused"
+ },
+ "2": {
+ "desc": "unused"
+ },
+ "3": {
+ "desc": "unused"
+ },
+ "4": {
+ "desc": "unused"
+ },
+ "5": {
+ "desc": "unused"
+ },
+ "6": {
+ "desc": "link0 crc error"
+ },
+ "7": {
+ "desc": "link1 crc error"
+ },
+ "8": {
+ "desc": "link0 nak received"
+ },
+ "9": {
+ "desc": "link1 nak received"
+ },
+ "10": {
+ "desc": "unused"
+ },
+ "11": {
+ "desc": "unused"
+ },
+ "12": {
+ "desc": "unused"
+ },
+ "13": {
+ "desc": "unused"
+ },
+ "14": {
+ "desc": "unused"
+ },
+ "15": {
+ "desc": "unused"
+ },
+ "16": {
+ "desc": "unused"
+ },
+ "17": {
+ "desc": "unused"
+ },
+ "18": {
+ "desc": "unused"
+ },
+ "19": {
+ "desc": "unused"
+ },
+ "20": {
+ "desc": "link0 loss block align"
+ },
+ "21": {
+ "desc": "link1 loss block align"
+ },
+ "22": {
+ "desc": "link0 invalid block"
+ },
+ "23": {
+ "desc": "link1 invalid block"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "link0 deskew overflow"
+ },
+ "27": {
+ "desc": "link1 deskew overflow"
+ },
+ "28": {
+ "desc": "link0 sw retrain"
+ },
+ "29": {
+ "desc": "link1 sw retrain"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "link0 no forward progress"
+ },
+ "35": {
+ "desc": "link1 no forward progress"
+ },
+ "36": {
+ "desc": "link0 training set received"
+ },
+ "37": {
+ "desc": "link1 training set received"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "link0 degraded mode"
+ },
+ "45": {
+ "desc": "link1 degraded mode"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "link0 dlx error"
+ },
+ "49": {
+ "desc": "link1 dlx error"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "link0 correctable array error"
+ },
+ "53": {
+ "desc": "link1 correctable array error"
+ },
+ "54": {
+ "desc": "link0 uncorrectable array error"
+ },
+ "55": {
+ "desc": "link1 uncorrectable array error"
+ },
+ "56": {
+ "desc": "link0 dlx clock frequency error"
+ },
+ "57": {
+ "desc": "link1 dlx clock frequency error"
+ },
+ "58": {
+ "desc": "link0 unrecoverable error"
+ },
+ "59": {
+ "desc": "link1 unrecoverable error"
+ },
+ "60": {
+ "desc": "link0 internal error"
+ },
+ "61": {
+ "desc": "link1 internal error"
+ }
+ }
+ },
+ "IOHS_DLP_FIR_SMP": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "link0 trained"
+ },
+ "1": {
+ "desc": "link1 trained"
+ },
+ "2": {
+ "desc": "link0 op irq"
+ },
+ "3": {
+ "desc": "link1 op irq"
+ },
+ "4": {
+ "desc": "link0 replay threshold"
+ },
+ "5": {
+ "desc": "link1 replay threshold"
+ },
+ "6": {
+ "desc": "link0 crc error"
+ },
+ "7": {
+ "desc": "link1 crc error"
+ },
+ "8": {
+ "desc": "link0 nak received"
+ },
+ "9": {
+ "desc": "link1 nak received"
+ },
+ "10": {
+ "desc": "link0 replay buffer full"
+ },
+ "11": {
+ "desc": "link1 replay buffer full"
+ },
+ "12": {
+ "desc": "link0 sl ecc threshold"
+ },
+ "13": {
+ "desc": "link1 sl ecc threshold"
+ },
+ "14": {
+ "desc": "link0 sl ecc correctable"
+ },
+ "15": {
+ "desc": "link1 sl ecc correctable"
+ },
+ "16": {
+ "desc": "link0 sl ecc ue"
+ },
+ "17": {
+ "desc": "link1 sl ecc ue"
+ },
+ "18": {
+ "desc": "link0 retrain threshold"
+ },
+ "19": {
+ "desc": "link1 retrain threshold"
+ },
+ "20": {
+ "desc": "link0 loss block align"
+ },
+ "21": {
+ "desc": "link1 loss block align"
+ },
+ "22": {
+ "desc": "link0 invalid block"
+ },
+ "23": {
+ "desc": "link1 invalid block"
+ },
+ "24": {
+ "desc": "link0 deskew error"
+ },
+ "25": {
+ "desc": "link1 deskew error"
+ },
+ "26": {
+ "desc": "link0 deskew overflow"
+ },
+ "27": {
+ "desc": "link1 deskew overflow"
+ },
+ "28": {
+ "desc": "link0 sw retrain"
+ },
+ "29": {
+ "desc": "link1 sw retrain"
+ },
+ "30": {
+ "desc": "link0 ack queue overflow"
+ },
+ "31": {
+ "desc": "link1 ack queue overflow"
+ },
+ "32": {
+ "desc": "link0 ack queue underflow"
+ },
+ "33": {
+ "desc": "link1 ack queue underflow"
+ },
+ "34": {
+ "desc": "link0 num replay"
+ },
+ "35": {
+ "desc": "link1 num replay"
+ },
+ "36": {
+ "desc": "link0 training set received"
+ },
+ "37": {
+ "desc": "link1 training set received"
+ },
+ "38": {
+ "desc": "link0 prbs select error"
+ },
+ "39": {
+ "desc": "link1 prbs select error"
+ },
+ "40": {
+ "desc": "link0 tcomplete bad"
+ },
+ "41": {
+ "desc": "link1 tcomplete bad"
+ },
+ "42": {
+ "desc": "link0 no spare lane available"
+ },
+ "43": {
+ "desc": "link1 no spare lane available"
+ },
+ "44": {
+ "desc": "link0 spare done"
+ },
+ "45": {
+ "desc": "link1 spare done"
+ },
+ "46": {
+ "desc": "link0 too many crc errors"
+ },
+ "47": {
+ "desc": "link1 too many crc errors"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "link0 osc switch"
+ },
+ "51": {
+ "desc": "link1 osc switch"
+ },
+ "52": {
+ "desc": "link0 correctable array error"
+ },
+ "53": {
+ "desc": "link1 correctable array error"
+ },
+ "54": {
+ "desc": "link0 uncorrectable array error"
+ },
+ "55": {
+ "desc": "link1 uncorrectable array error"
+ },
+ "56": {
+ "desc": "link0 training failed"
+ },
+ "57": {
+ "desc": "link1 training failed"
+ },
+ "58": {
+ "desc": "link0 unrecoverable error"
+ },
+ "59": {
+ "desc": "link1 unrecoverable error"
+ },
+ "60": {
+ "desc": "link0 internal error"
+ },
+ "61": {
+ "desc": "link1 internal error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "IOHS_DLP_FIR_SMP",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "IOHS_DLP_FIR_SMP": [
+ {
+ "reg_name": "IOHS_DLP_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_SEC_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_OPTICAL_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_TX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_TX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_RX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_RX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_REPLAY_THRESHOLD",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_SL_ECC_THRESHOLD",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_SYN_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_SYN_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_EDPL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_EDPL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_QUALITY",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_QUALITY",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_DLL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_MISC_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_10/mc_omi_dl_err_rpt.json b/chip_data/p10_10/mc_omi_dl_err_rpt.json
new file mode 100644
index 0000000..94b7b17
--- /dev/null
+++ b/chip_data/p10_10/mc_omi_dl_err_rpt.json
@@ -0,0 +1,106 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "isolation_nodes": {
+ "MC_OMI_DL_ERR_RPT": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "52": {
+ "desc": "spare"
+ },
+ "53": {
+ "desc": "flit hammer"
+ },
+ "54": {
+ "desc": "illegal TX lane reversal request"
+ },
+ "55": {
+ "desc": "RX receiving slow A"
+ },
+ "56": {
+ "desc": "RX receiving illegal run length"
+ },
+ "57": {
+ "desc": "control parity error"
+ },
+ "58": {
+ "desc": "spare"
+ },
+ "59": {
+ "desc": "truncated flit from TL"
+ },
+ "60": {
+ "desc": "illegal run length from TL"
+ },
+ "61": {
+ "desc": "Ack pointer overflow"
+ },
+ "62": {
+ "desc": "UE on control flit replay buffer"
+ },
+ "63": {
+ "desc": "UE on control flit frame buffer"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_eq.json b/chip_data/p10_10/node_cfir_eq.json
new file mode 100644
index 0000000..ac4ba4f
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_eq.json
@@ -0,0 +1,1227 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_EQ_CS": {
+ "instances": {
+ "0": "0x20040000",
+ "1": "0x21040000",
+ "2": "0x22040000",
+ "3": "0x23040000",
+ "4": "0x24040000",
+ "5": "0x25040000",
+ "6": "0x26040000",
+ "7": "0x27040000"
+ }
+ },
+ "CFIR_EQ_CS_MASK": {
+ "instances": {
+ "0": "0x20040040",
+ "1": "0x21040040",
+ "2": "0x22040040",
+ "3": "0x23040040",
+ "4": "0x24040040",
+ "5": "0x25040040",
+ "6": "0x26040040",
+ "7": "0x27040040"
+ }
+ },
+ "CFIR_EQ_RE": {
+ "instances": {
+ "0": "0x20040001",
+ "1": "0x21040001",
+ "2": "0x22040001",
+ "3": "0x23040001",
+ "4": "0x24040001",
+ "5": "0x25040001",
+ "6": "0x26040001",
+ "7": "0x27040001"
+ }
+ },
+ "CFIR_EQ_RE_MASK": {
+ "instances": {
+ "0": "0x20040041",
+ "1": "0x21040041",
+ "2": "0x22040041",
+ "3": "0x23040041",
+ "4": "0x24040041",
+ "5": "0x25040041",
+ "6": "0x26040041",
+ "7": "0x27040041"
+ }
+ },
+ "CFIR_EQ_SPA": {
+ "instances": {
+ "0": "0x20040002",
+ "1": "0x21040002",
+ "2": "0x22040002",
+ "3": "0x23040002",
+ "4": "0x24040002",
+ "5": "0x25040002",
+ "6": "0x26040002",
+ "7": "0x27040002"
+ }
+ },
+ "CFIR_EQ_SPA_MASK": {
+ "instances": {
+ "0": "0x20040042",
+ "1": "0x21040042",
+ "2": "0x22040042",
+ "3": "0x23040042",
+ "4": "0x24040042",
+ "5": "0x25040042",
+ "6": "0x26040042",
+ "7": "0x27040042"
+ }
+ },
+ "CFIR_EQ_UCS": {
+ "instances": {
+ "0": "0x20040003",
+ "1": "0x21040003",
+ "2": "0x22040003",
+ "3": "0x23040003",
+ "4": "0x24040003",
+ "5": "0x25040003",
+ "6": "0x26040003",
+ "7": "0x27040003"
+ }
+ },
+ "CFIR_EQ_UCS_MASK": {
+ "instances": {
+ "0": "0x20040043",
+ "1": "0x21040043",
+ "2": "0x22040043",
+ "3": "0x23040043",
+ "4": "0x24040043",
+ "5": "0x25040043",
+ "6": "0x26040043",
+ "7": "0x27040043"
+ }
+ },
+ "CFIR_EQ_HA": {
+ "instances": {
+ "0": "0x20040004",
+ "1": "0x21040004",
+ "2": "0x22040004",
+ "3": "0x23040004",
+ "4": "0x24040004",
+ "5": "0x25040004",
+ "6": "0x26040004",
+ "7": "0x27040004"
+ }
+ },
+ "CFIR_EQ_HA_MASK": {
+ "instances": {
+ "0": "0x20040044",
+ "1": "0x21040044",
+ "2": "0x22040044",
+ "3": "0x23040044",
+ "4": "0x24040044",
+ "5": "0x25040044",
+ "6": "0x26040044",
+ "7": "0x27040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_EQ_CS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from EQ_QME_FIR",
+ "child_node": {
+ "name": "EQ_QME_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_RE": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from EQ_QME_FIR",
+ "child_node": {
+ "name": "EQ_QME_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_SPA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "7": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "8": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "9": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "10": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "12": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "13": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "14": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "15": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "17": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "18": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "19": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "20": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_UCS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_HA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_iohs.json b/chip_data/p10_10/node_cfir_iohs.json
new file mode 100644
index 0000000..0a0d83f
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_iohs.json
@@ -0,0 +1,411 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_IOHS_CS": {
+ "instances": {
+ "0": "0x18040000",
+ "1": "0x19040000",
+ "2": "0x1A040000",
+ "3": "0x1B040000",
+ "4": "0x1C040000",
+ "5": "0x1D040000",
+ "6": "0x1E040000",
+ "7": "0x1F040000"
+ }
+ },
+ "CFIR_IOHS_CS_MASK": {
+ "instances": {
+ "0": "0x18040040",
+ "1": "0x19040040",
+ "2": "0x1A040040",
+ "3": "0x1B040040",
+ "4": "0x1C040040",
+ "5": "0x1D040040",
+ "6": "0x1E040040",
+ "7": "0x1F040040"
+ }
+ },
+ "CFIR_IOHS_RE": {
+ "instances": {
+ "0": "0x18040001",
+ "1": "0x19040001",
+ "2": "0x1A040001",
+ "3": "0x1B040001",
+ "4": "0x1C040001",
+ "5": "0x1D040001",
+ "6": "0x1E040001",
+ "7": "0x1F040001"
+ }
+ },
+ "CFIR_IOHS_RE_MASK": {
+ "instances": {
+ "0": "0x18040041",
+ "1": "0x19040041",
+ "2": "0x1A040041",
+ "3": "0x1B040041",
+ "4": "0x1C040041",
+ "5": "0x1D040041",
+ "6": "0x1E040041",
+ "7": "0x1F040041"
+ }
+ },
+ "CFIR_IOHS_SPA": {
+ "instances": {
+ "0": "0x18040002",
+ "1": "0x19040002",
+ "2": "0x1A040002",
+ "3": "0x1B040002",
+ "4": "0x1C040002",
+ "5": "0x1D040002",
+ "6": "0x1E040002",
+ "7": "0x1F040002"
+ }
+ },
+ "CFIR_IOHS_SPA_MASK": {
+ "instances": {
+ "0": "0x18040042",
+ "1": "0x19040042",
+ "2": "0x1A040042",
+ "3": "0x1B040042",
+ "4": "0x1C040042",
+ "5": "0x1D040042",
+ "6": "0x1E040042",
+ "7": "0x1F040042"
+ }
+ },
+ "CFIR_IOHS_UCS": {
+ "instances": {
+ "0": "0x18040003",
+ "1": "0x19040003",
+ "2": "0x1A040003",
+ "3": "0x1B040003",
+ "4": "0x1C040003",
+ "5": "0x1D040003",
+ "6": "0x1E040003",
+ "7": "0x1F040003"
+ }
+ },
+ "CFIR_IOHS_UCS_MASK": {
+ "instances": {
+ "0": "0x18040043",
+ "1": "0x19040043",
+ "2": "0x1A040043",
+ "3": "0x1B040043",
+ "4": "0x1C040043",
+ "5": "0x1D040043",
+ "6": "0x1E040043",
+ "7": "0x1F040043"
+ }
+ },
+ "CFIR_IOHS_HA": {
+ "instances": {
+ "0": "0x18040004",
+ "1": "0x19040004",
+ "2": "0x1A040004",
+ "3": "0x1B040004",
+ "4": "0x1C040004",
+ "5": "0x1D040004",
+ "6": "0x1E040004",
+ "7": "0x1F040004"
+ }
+ },
+ "CFIR_IOHS_HA_MASK": {
+ "instances": {
+ "0": "0x18040044",
+ "1": "0x19040044",
+ "2": "0x1A040044",
+ "3": "0x1B040044",
+ "4": "0x1C040044",
+ "5": "0x1D040044",
+ "6": "0x1E040044",
+ "7": "0x1F040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_IOHS_CS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_RE": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_SPA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_UCS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_HA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_mc.json b/chip_data/p10_10/node_cfir_mc.json
new file mode 100644
index 0000000..20f781c
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_mc.json
@@ -0,0 +1,735 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_MC_CS": {
+ "instances": {
+ "0": "0x0C040000",
+ "1": "0x0D040000",
+ "2": "0x0E040000",
+ "3": "0x0F040000"
+ }
+ },
+ "CFIR_MC_CS_MASK": {
+ "instances": {
+ "0": "0x0C040040",
+ "1": "0x0D040040",
+ "2": "0x0E040040",
+ "3": "0x0F040040"
+ }
+ },
+ "CFIR_MC_RE": {
+ "instances": {
+ "0": "0x0C040001",
+ "1": "0x0D040001",
+ "2": "0x0E040001",
+ "3": "0x0F040001"
+ }
+ },
+ "CFIR_MC_RE_MASK": {
+ "instances": {
+ "0": "0x0C040041",
+ "1": "0x0D040041",
+ "2": "0x0E040041",
+ "3": "0x0F040041"
+ }
+ },
+ "CFIR_MC_SPA": {
+ "instances": {
+ "0": "0x0C040002",
+ "1": "0x0D040002",
+ "2": "0x0E040002",
+ "3": "0x0F040002"
+ }
+ },
+ "CFIR_MC_SPA_MASK": {
+ "instances": {
+ "0": "0x0C040042",
+ "1": "0x0D040042",
+ "2": "0x0E040042",
+ "3": "0x0F040042"
+ }
+ },
+ "CFIR_MC_UCS": {
+ "instances": {
+ "0": "0x0C040003",
+ "1": "0x0D040003",
+ "2": "0x0E040003",
+ "3": "0x0F040003"
+ }
+ },
+ "CFIR_MC_UCS_MASK": {
+ "instances": {
+ "0": "0x0C040043",
+ "1": "0x0D040043",
+ "2": "0x0E040043",
+ "3": "0x0F040043"
+ }
+ },
+ "CFIR_MC_HA": {
+ "instances": {
+ "0": "0x0C040004",
+ "1": "0x0D040004",
+ "2": "0x0E040004",
+ "3": "0x0F040004"
+ }
+ },
+ "CFIR_MC_HA_MASK": {
+ "instances": {
+ "0": "0x0C040044",
+ "1": "0x0D040044",
+ "2": "0x0E040044",
+ "3": "0x0F040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_MC_CS": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_RE": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_SPA": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_UCS": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_HA": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_n0.json b/chip_data/p10_10/node_cfir_n0.json
new file mode 100644
index 0000000..6ddacbd
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_n0.json
@@ -0,0 +1,474 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_N0_CS": {
+ "instances": {
+ "0": "0x02040000"
+ }
+ },
+ "CFIR_N0_CS_MASK": {
+ "instances": {
+ "0": "0x02040040"
+ }
+ },
+ "CFIR_N0_RE": {
+ "instances": {
+ "0": "0x02040001"
+ }
+ },
+ "CFIR_N0_RE_MASK": {
+ "instances": {
+ "0": "0x02040041"
+ }
+ },
+ "CFIR_N0_SPA": {
+ "instances": {
+ "0": "0x02040002"
+ }
+ },
+ "CFIR_N0_SPA_MASK": {
+ "instances": {
+ "0": "0x02040042"
+ }
+ },
+ "CFIR_N0_UCS": {
+ "instances": {
+ "0": "0x02040003"
+ }
+ },
+ "CFIR_N0_UCS_MASK": {
+ "instances": {
+ "0": "0x02040043"
+ }
+ },
+ "CFIR_N0_HA": {
+ "instances": {
+ "0": "0x02040004"
+ }
+ },
+ "CFIR_N0_HA_MASK": {
+ "instances": {
+ "0": "0x02040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_N0_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 5
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 5
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_n1.json b/chip_data/p10_10/node_cfir_n1.json
new file mode 100644
index 0000000..f227b4e
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_n1.json
@@ -0,0 +1,906 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_N1_CS": {
+ "instances": {
+ "0": "0x03040000"
+ }
+ },
+ "CFIR_N1_CS_MASK": {
+ "instances": {
+ "0": "0x03040040"
+ }
+ },
+ "CFIR_N1_RE": {
+ "instances": {
+ "0": "0x03040001"
+ }
+ },
+ "CFIR_N1_RE_MASK": {
+ "instances": {
+ "0": "0x03040041"
+ }
+ },
+ "CFIR_N1_SPA": {
+ "instances": {
+ "0": "0x03040002"
+ }
+ },
+ "CFIR_N1_SPA_MASK": {
+ "instances": {
+ "0": "0x03040042"
+ }
+ },
+ "CFIR_N1_UCS": {
+ "instances": {
+ "0": "0x03040003"
+ }
+ },
+ "CFIR_N1_UCS_MASK": {
+ "instances": {
+ "0": "0x03040043"
+ }
+ },
+ "CFIR_N1_HA": {
+ "instances": {
+ "0": "0x03040004"
+ }
+ },
+ "CFIR_N1_HA_MASK": {
+ "instances": {
+ "0": "0x03040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_N1_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from HCA_FIR",
+ "child_node": {
+ "name": "HCA_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from LPC_FIR",
+ "child_node": {
+ "name": "LPC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from PB_EXT_FIR",
+ "child_node": {
+ "name": "PB_EXT_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from PSIHB_FIR",
+ "child_node": {
+ "name": "PSIHB_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from PBAF_FIR",
+ "child_node": {
+ "name": "PBAF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from HCA_FIR",
+ "child_node": {
+ "name": "HCA_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from LPC_FIR",
+ "child_node": {
+ "name": "LPC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from PSIHB_FIR",
+ "child_node": {
+ "name": "PSIHB_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from PBAF_FIR",
+ "child_node": {
+ "name": "PBAF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_paue.json b/chip_data/p10_10/node_cfir_paue.json
new file mode 100644
index 0000000..95e844d
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_paue.json
@@ -0,0 +1,473 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_PAUE_CS": {
+ "instances": {
+ "0": "0x10040000",
+ "1": "0x11040000"
+ }
+ },
+ "CFIR_PAUE_CS_MASK": {
+ "instances": {
+ "0": "0x10040040",
+ "1": "0x11040040"
+ }
+ },
+ "CFIR_PAUE_RE": {
+ "instances": {
+ "0": "0x10040001",
+ "1": "0x11040001"
+ }
+ },
+ "CFIR_PAUE_RE_MASK": {
+ "instances": {
+ "0": "0x10040041",
+ "1": "0x11040041"
+ }
+ },
+ "CFIR_PAUE_SPA": {
+ "instances": {
+ "0": "0x10040002",
+ "1": "0x11040002"
+ }
+ },
+ "CFIR_PAUE_SPA_MASK": {
+ "instances": {
+ "0": "0x10040042",
+ "1": "0x11040042"
+ }
+ },
+ "CFIR_PAUE_UCS": {
+ "instances": {
+ "0": "0x10040003",
+ "1": "0x11040003"
+ }
+ },
+ "CFIR_PAUE_UCS_MASK": {
+ "instances": {
+ "0": "0x10040043",
+ "1": "0x11040043"
+ }
+ },
+ "CFIR_PAUE_HA": {
+ "instances": {
+ "0": "0x10040004",
+ "1": "0x11040004"
+ }
+ },
+ "CFIR_PAUE_HA_MASK": {
+ "instances": {
+ "0": "0x10040044",
+ "1": "0x11040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PAUE_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_pauw.json b/chip_data/p10_10/node_cfir_pauw.json
new file mode 100644
index 0000000..4189839
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_pauw.json
@@ -0,0 +1,563 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_PAUW_CS": {
+ "instances": {
+ "0": "0x12040000",
+ "1": "0x13040000"
+ }
+ },
+ "CFIR_PAUW_CS_MASK": {
+ "instances": {
+ "0": "0x12040040",
+ "1": "0x13040040"
+ }
+ },
+ "CFIR_PAUW_RE": {
+ "instances": {
+ "0": "0x12040001",
+ "1": "0x13040001"
+ }
+ },
+ "CFIR_PAUW_RE_MASK": {
+ "instances": {
+ "0": "0x12040041",
+ "1": "0x13040041"
+ }
+ },
+ "CFIR_PAUW_SPA": {
+ "instances": {
+ "0": "0x12040002",
+ "1": "0x13040002"
+ }
+ },
+ "CFIR_PAUW_SPA_MASK": {
+ "instances": {
+ "0": "0x12040042",
+ "1": "0x13040042"
+ }
+ },
+ "CFIR_PAUW_UCS": {
+ "instances": {
+ "0": "0x12040003",
+ "1": "0x13040003"
+ }
+ },
+ "CFIR_PAUW_UCS_MASK": {
+ "instances": {
+ "0": "0x12040043",
+ "1": "0x13040043"
+ }
+ },
+ "CFIR_PAUW_HA": {
+ "instances": {
+ "0": "0x12040004",
+ "1": "0x13040004"
+ }
+ },
+ "CFIR_PAUW_HA_MASK": {
+ "instances": {
+ "0": "0x12040044",
+ "1": "0x13040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PAUW_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PAU_DL_FIR",
+ "child_node": {
+ "name": "PAU_DL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_pci.json b/chip_data/p10_10/node_cfir_pci.json
new file mode 100644
index 0000000..a9bba86
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_pci.json
@@ -0,0 +1,453 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_PCI_CS": {
+ "instances": {
+ "0": "0x08040000",
+ "1": "0x09040000"
+ }
+ },
+ "CFIR_PCI_CS_MASK": {
+ "instances": {
+ "0": "0x08040040",
+ "1": "0x09040040"
+ }
+ },
+ "CFIR_PCI_RE": {
+ "instances": {
+ "0": "0x08040001",
+ "1": "0x09040001"
+ }
+ },
+ "CFIR_PCI_RE_MASK": {
+ "instances": {
+ "0": "0x08040041",
+ "1": "0x09040041"
+ }
+ },
+ "CFIR_PCI_SPA": {
+ "instances": {
+ "0": "0x08040002",
+ "1": "0x09040002"
+ }
+ },
+ "CFIR_PCI_SPA_MASK": {
+ "instances": {
+ "0": "0x08040042",
+ "1": "0x09040042"
+ }
+ },
+ "CFIR_PCI_UCS": {
+ "instances": {
+ "0": "0x08040003",
+ "1": "0x09040003"
+ }
+ },
+ "CFIR_PCI_UCS_MASK": {
+ "instances": {
+ "0": "0x08040043",
+ "1": "0x09040043"
+ }
+ },
+ "CFIR_PCI_HA": {
+ "instances": {
+ "0": "0x08040004",
+ "1": "0x09040004"
+ }
+ },
+ "CFIR_PCI_HA_MASK": {
+ "instances": {
+ "0": "0x08040044",
+ "1": "0x09040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PCI_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_cfir_tp.json b/chip_data/p10_10/node_cfir_tp.json
new file mode 100644
index 0000000..33f4e85
--- /dev/null
+++ b/chip_data/p10_10/node_cfir_tp.json
@@ -0,0 +1,294 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "CFIR_TP_CS": {
+ "instances": {
+ "0": "0x01040000"
+ }
+ },
+ "CFIR_TP_CS_MASK": {
+ "instances": {
+ "0": "0x01040040"
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": {
+ "0": "0x01040001"
+ }
+ },
+ "CFIR_TP_RE_MASK": {
+ "instances": {
+ "0": "0x01040041"
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": {
+ "0": "0x01040002"
+ }
+ },
+ "CFIR_TP_SPA_MASK": {
+ "instances": {
+ "0": "0x01040042"
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": {
+ "0": "0x01040003"
+ }
+ },
+ "CFIR_TP_UCS_MASK": {
+ "instances": {
+ "0": "0x01040043"
+ }
+ },
+ "CFIR_TP_HA": {
+ "instances": {
+ "0": "0x01040004"
+ }
+ },
+ "CFIR_TP_HA_MASK": {
+ "instances": {
+ "0": "0x01040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_TP_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from OCC_FIR",
+ "child_node": {
+ "name": "OCC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PBAO_FIR",
+ "child_node": {
+ "name": "PBAO_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from OCC_FIR",
+ "child_node": {
+ "name": "OCC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PBAO_FIR",
+ "child_node": {
+ "name": "PBAO_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_core_fir.json b/chip_data/p10_10/node_eq_core_fir.json
new file mode 100644
index 0000000..d6ea36c
--- /dev/null
+++ b/chip_data/p10_10/node_eq_core_fir.json
@@ -0,0 +1,534 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_CORE_FIR": {
+ "instances": {
+ "0": "0x20028440",
+ "1": "0x20024440",
+ "2": "0x20022440",
+ "3": "0x20021440",
+ "4": "0x21028440",
+ "5": "0x21024440",
+ "6": "0x21022440",
+ "7": "0x21021440",
+ "8": "0x22028440",
+ "9": "0x22024440",
+ "10": "0x22022440",
+ "11": "0x22021440",
+ "12": "0x23028440",
+ "13": "0x23024440",
+ "14": "0x23022440",
+ "15": "0x23021440",
+ "16": "0x24028440",
+ "17": "0x24024440",
+ "18": "0x24022440",
+ "19": "0x24021440",
+ "20": "0x25028440",
+ "21": "0x25024440",
+ "22": "0x25022440",
+ "23": "0x25021440",
+ "24": "0x26028440",
+ "25": "0x26024440",
+ "26": "0x26022440",
+ "27": "0x26021440",
+ "28": "0x27028440",
+ "29": "0x27024440",
+ "30": "0x27022440",
+ "31": "0x27021440"
+ }
+ },
+ "EQ_CORE_FIR_MASK": {
+ "instances": {
+ "0": "0x20028443",
+ "1": "0x20024443",
+ "2": "0x20022443",
+ "3": "0x20021443",
+ "4": "0x21028443",
+ "5": "0x21024443",
+ "6": "0x21022443",
+ "7": "0x21021443",
+ "8": "0x22028443",
+ "9": "0x22024443",
+ "10": "0x22022443",
+ "11": "0x22021443",
+ "12": "0x23028443",
+ "13": "0x23024443",
+ "14": "0x23022443",
+ "15": "0x23021443",
+ "16": "0x24028443",
+ "17": "0x24024443",
+ "18": "0x24022443",
+ "19": "0x24021443",
+ "20": "0x25028443",
+ "21": "0x25024443",
+ "22": "0x25022443",
+ "23": "0x25021443",
+ "24": "0x26028443",
+ "25": "0x26024443",
+ "26": "0x26022443",
+ "27": "0x26021443",
+ "28": "0x27028443",
+ "29": "0x27024443",
+ "30": "0x27022443",
+ "31": "0x27021443"
+ }
+ },
+ "EQ_CORE_FIR_ACT0": {
+ "instances": {
+ "0": "0x20028446",
+ "1": "0x20024446",
+ "2": "0x20022446",
+ "3": "0x20021446",
+ "4": "0x21028446",
+ "5": "0x21024446",
+ "6": "0x21022446",
+ "7": "0x21021446",
+ "8": "0x22028446",
+ "9": "0x22024446",
+ "10": "0x22022446",
+ "11": "0x22021446",
+ "12": "0x23028446",
+ "13": "0x23024446",
+ "14": "0x23022446",
+ "15": "0x23021446",
+ "16": "0x24028446",
+ "17": "0x24024446",
+ "18": "0x24022446",
+ "19": "0x24021446",
+ "20": "0x25028446",
+ "21": "0x25024446",
+ "22": "0x25022446",
+ "23": "0x25021446",
+ "24": "0x26028446",
+ "25": "0x26024446",
+ "26": "0x26022446",
+ "27": "0x26021446",
+ "28": "0x27028446",
+ "29": "0x27024446",
+ "30": "0x27022446",
+ "31": "0x27021446"
+ }
+ },
+ "EQ_CORE_FIR_ACT1": {
+ "instances": {
+ "0": "0x20028447",
+ "1": "0x20024447",
+ "2": "0x20022447",
+ "3": "0x20021447",
+ "4": "0x21028447",
+ "5": "0x21024447",
+ "6": "0x21022447",
+ "7": "0x21021447",
+ "8": "0x22028447",
+ "9": "0x22024447",
+ "10": "0x22022447",
+ "11": "0x22021447",
+ "12": "0x23028447",
+ "13": "0x23024447",
+ "14": "0x23022447",
+ "15": "0x23021447",
+ "16": "0x24028447",
+ "17": "0x24024447",
+ "18": "0x24022447",
+ "19": "0x24021447",
+ "20": "0x25028447",
+ "21": "0x25024447",
+ "22": "0x25022447",
+ "23": "0x25021447",
+ "24": "0x26028447",
+ "25": "0x26024447",
+ "26": "0x26022447",
+ "27": "0x26021447",
+ "28": "0x27028447",
+ "29": "0x27024447",
+ "30": "0x27022447",
+ "31": "0x27021447"
+ }
+ },
+ "EQ_CORE_FIR_WOF": {
+ "instances": {
+ "0": "0x20028448",
+ "1": "0x20024448",
+ "2": "0x20022448",
+ "3": "0x20021448",
+ "4": "0x21028448",
+ "5": "0x21024448",
+ "6": "0x21022448",
+ "7": "0x21021448",
+ "8": "0x22028448",
+ "9": "0x22024448",
+ "10": "0x22022448",
+ "11": "0x22021448",
+ "12": "0x23028448",
+ "13": "0x23024448",
+ "14": "0x23022448",
+ "15": "0x23021448",
+ "16": "0x24028448",
+ "17": "0x24024448",
+ "18": "0x24022448",
+ "19": "0x24021448",
+ "20": "0x25028448",
+ "21": "0x25024448",
+ "22": "0x25022448",
+ "23": "0x25021448",
+ "24": "0x26028448",
+ "25": "0x26024448",
+ "26": "0x26022448",
+ "27": "0x26021448",
+ "28": "0x27028448",
+ "29": "0x27024448",
+ "30": "0x27022448",
+ "31": "0x27021448"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_CORE_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_WOF"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "IFU SRAM recoverable error (ICACHE parity error, etc)"
+ },
+ "1": {
+ "desc": "TC checkstop"
+ },
+ "2": {
+ "desc": "IFU RegFile recoverable error"
+ },
+ "3": {
+ "desc": "IFU RegFile core checkstop"
+ },
+ "4": {
+ "desc": "IFU logic recoverable error"
+ },
+ "5": {
+ "desc": "IFU logic core checkstop"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "VSU Inference Accumulator recoverable error"
+ },
+ "8": {
+ "desc": "Recovery core checkstop"
+ },
+ "9": {
+ "desc": "VSU Slice Targeted File (STF) recoverable error"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "ISU logic recoverable error"
+ },
+ "12": {
+ "desc": "ISU logic core checkstop"
+ },
+ "13": {
+ "desc": "ISU recoverable if not in MT window"
+ },
+ "14": {
+ "desc": "MCHK received while ME=0 - non recoverable"
+ },
+ "15": {
+ "desc": "UE from L2"
+ },
+ "16": {
+ "desc": "Number of UEs from L2 above threshold"
+ },
+ "17": {
+ "desc": "UE on CI load"
+ },
+ "18": {
+ "desc": "MMU TLB parity recoverable error"
+ },
+ "19": {
+ "desc": "MMU SLB parity recoverable error"
+ },
+ "20": {
+ "desc": "reserved"
+ },
+ "21": {
+ "desc": "MMU CXT recoverable error"
+ },
+ "22": {
+ "desc": "MMU logic core checkstop"
+ },
+ "23": {
+ "desc": "MMU system checkstop"
+ },
+ "24": {
+ "desc": "VSU logic recoverable error"
+ },
+ "25": {
+ "desc": "VSU logic core checkstop"
+ },
+ "26": {
+ "desc": "Thread in maintenance mode and receives recovery request"
+ },
+ "27": {
+ "desc": "reserved"
+ },
+ "28": {
+ "desc": "PC system checkstop - Recoverable error received when recovery disabled"
+ },
+ "29": {
+ "desc": "LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)"
+ },
+ "30": {
+ "desc": "LSU set deleted"
+ },
+ "31": {
+ "desc": "LSU RegFile recoverable error"
+ },
+ "32": {
+ "desc": "LSU RegFile core checkstop"
+ },
+ "33": {
+ "desc": "MMU TLB multi hit error occurred"
+ },
+ "34": {
+ "desc": "MMU SLB multi hit error occurred"
+ },
+ "35": {
+ "desc": "LSU ERAT multi hit error occurred"
+ },
+ "36": {
+ "desc": "PC forward progress error"
+ },
+ "37": {
+ "desc": "LSU logic recoverable error"
+ },
+ "38": {
+ "desc": "LSU logic core checkstop"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "LSU system checkstop"
+ },
+ "42": {
+ "desc": "reserved"
+ },
+ "43": {
+ "desc": "PC thread hang recoverable error"
+ },
+ "44": {
+ "desc": "reserved"
+ },
+ "45": {
+ "desc": "PC logic checkstop"
+ },
+ "46": {
+ "desc": "PC TimeBase Facility checkstop"
+ },
+ "47": {
+ "desc": "PC TimeBase Facility checkstop"
+ },
+ "48": {
+ "desc": "reserved"
+ },
+ "49": {
+ "desc": "reserved"
+ },
+ "50": {
+ "desc": "reserved"
+ },
+ "51": {
+ "desc": "reserved"
+ },
+ "52": {
+ "desc": "Hang Recovery Failed"
+ },
+ "53": {
+ "desc": "Core Hang detected"
+ },
+ "54": {
+ "desc": "reserved"
+ },
+ "55": {
+ "desc": "Nest Hang detected"
+ },
+ "56": {
+ "desc": "Other Core Chiplet recoverable error"
+ },
+ "57": {
+ "desc": "Other Core Chiplet core checkstop"
+ },
+ "58": {
+ "desc": "Other Core Chiplet system checkstop"
+ },
+ "59": {
+ "desc": "SCOM satellite error detected"
+ },
+ "60": {
+ "desc": "Debug Trigger error inject"
+ },
+ "61": {
+ "desc": "SCOM or Firmware recoverable error inject"
+ },
+ "62": {
+ "desc": "Firmware checkstop error inject"
+ },
+ "63": {
+ "desc": "PHYP checkstop via SPRC/SPRD"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_CORE_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_l2_fir.json b/chip_data/p10_10/node_eq_l2_fir.json
new file mode 100644
index 0000000..e69146b
--- /dev/null
+++ b/chip_data/p10_10/node_eq_l2_fir.json
@@ -0,0 +1,394 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_L2_FIR": {
+ "instances": {
+ "0": "0x20028000",
+ "1": "0x20024000",
+ "2": "0x20022000",
+ "3": "0x20021000",
+ "4": "0x21028000",
+ "5": "0x21024000",
+ "6": "0x21022000",
+ "7": "0x21021000",
+ "8": "0x22028000",
+ "9": "0x22024000",
+ "10": "0x22022000",
+ "11": "0x22021000",
+ "12": "0x23028000",
+ "13": "0x23024000",
+ "14": "0x23022000",
+ "15": "0x23021000",
+ "16": "0x24028000",
+ "17": "0x24024000",
+ "18": "0x24022000",
+ "19": "0x24021000",
+ "20": "0x25028000",
+ "21": "0x25024000",
+ "22": "0x25022000",
+ "23": "0x25021000",
+ "24": "0x26028000",
+ "25": "0x26024000",
+ "26": "0x26022000",
+ "27": "0x26021000",
+ "28": "0x27028000",
+ "29": "0x27024000",
+ "30": "0x27022000",
+ "31": "0x27021000"
+ }
+ },
+ "EQ_L2_FIR_MASK": {
+ "instances": {
+ "0": "0x20028003",
+ "1": "0x20024003",
+ "2": "0x20022003",
+ "3": "0x20021003",
+ "4": "0x21028003",
+ "5": "0x21024003",
+ "6": "0x21022003",
+ "7": "0x21021003",
+ "8": "0x22028003",
+ "9": "0x22024003",
+ "10": "0x22022003",
+ "11": "0x22021003",
+ "12": "0x23028003",
+ "13": "0x23024003",
+ "14": "0x23022003",
+ "15": "0x23021003",
+ "16": "0x24028003",
+ "17": "0x24024003",
+ "18": "0x24022003",
+ "19": "0x24021003",
+ "20": "0x25028003",
+ "21": "0x25024003",
+ "22": "0x25022003",
+ "23": "0x25021003",
+ "24": "0x26028003",
+ "25": "0x26024003",
+ "26": "0x26022003",
+ "27": "0x26021003",
+ "28": "0x27028003",
+ "29": "0x27024003",
+ "30": "0x27022003",
+ "31": "0x27021003"
+ }
+ },
+ "EQ_L2_FIR_ACT0": {
+ "instances": {
+ "0": "0x20028006",
+ "1": "0x20024006",
+ "2": "0x20022006",
+ "3": "0x20021006",
+ "4": "0x21028006",
+ "5": "0x21024006",
+ "6": "0x21022006",
+ "7": "0x21021006",
+ "8": "0x22028006",
+ "9": "0x22024006",
+ "10": "0x22022006",
+ "11": "0x22021006",
+ "12": "0x23028006",
+ "13": "0x23024006",
+ "14": "0x23022006",
+ "15": "0x23021006",
+ "16": "0x24028006",
+ "17": "0x24024006",
+ "18": "0x24022006",
+ "19": "0x24021006",
+ "20": "0x25028006",
+ "21": "0x25024006",
+ "22": "0x25022006",
+ "23": "0x25021006",
+ "24": "0x26028006",
+ "25": "0x26024006",
+ "26": "0x26022006",
+ "27": "0x26021006",
+ "28": "0x27028006",
+ "29": "0x27024006",
+ "30": "0x27022006",
+ "31": "0x27021006"
+ }
+ },
+ "EQ_L2_FIR_ACT1": {
+ "instances": {
+ "0": "0x20028007",
+ "1": "0x20024007",
+ "2": "0x20022007",
+ "3": "0x20021007",
+ "4": "0x21028007",
+ "5": "0x21024007",
+ "6": "0x21022007",
+ "7": "0x21021007",
+ "8": "0x22028007",
+ "9": "0x22024007",
+ "10": "0x22022007",
+ "11": "0x22021007",
+ "12": "0x23028007",
+ "13": "0x23024007",
+ "14": "0x23022007",
+ "15": "0x23021007",
+ "16": "0x24028007",
+ "17": "0x24024007",
+ "18": "0x24022007",
+ "19": "0x24021007",
+ "20": "0x25028007",
+ "21": "0x25024007",
+ "22": "0x25022007",
+ "23": "0x25021007",
+ "24": "0x26028007",
+ "25": "0x26024007",
+ "26": "0x26022007",
+ "27": "0x26021007",
+ "28": "0x27028007",
+ "29": "0x27024007",
+ "30": "0x27022007",
+ "31": "0x27021007"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_L2_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "L2 cache read CE"
+ },
+ "1": {
+ "desc": "L2 cache read UE"
+ },
+ "2": {
+ "desc": "L2 cache read SUE"
+ },
+ "3": {
+ "desc": "Hw directory initiated line delete"
+ },
+ "4": {
+ "desc": "UE or SUE detected by on modified line"
+ },
+ "5": {
+ "desc": "UE or SUE detected on non-modified line"
+ },
+ "6": {
+ "desc": "L2 directory read CE"
+ },
+ "7": {
+ "desc": "L2 directory read UE"
+ },
+ "8": {
+ "desc": "L2 directory CE due to stuck bit"
+ },
+ "9": {
+ "desc": "L2 directory stuck bit CE repair failed"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "LRU read error detected"
+ },
+ "12": {
+ "desc": "RC timed out waiting for powerbus to return data"
+ },
+ "13": {
+ "desc": "NCU timed out waiting for powerbus to return data"
+ },
+ "14": {
+ "desc": "Internal h/w control error"
+ },
+ "15": {
+ "desc": "LRU all members in a class line deleted"
+ },
+ "16": {
+ "desc": "Cache Inhibited Ld/St hit a line in the L2 cache"
+ },
+ "17": {
+ "desc": "(RC) load received pb cresp addr error"
+ },
+ "18": {
+ "desc": "(RC) store received pb cresp addr error"
+ },
+ "19": {
+ "desc": "RC incoming Power Bus data had a CE error"
+ },
+ "20": {
+ "desc": "RC incoming Power Bus data had a UE error"
+ },
+ "21": {
+ "desc": "RC incoming Power Bus data had a SUE error"
+ },
+ "22": {
+ "desc": "Targetted nodal request got rty_inc cresp"
+ },
+ "23": {
+ "desc": "RC fabric op Ld cresp addr error for hyp"
+ },
+ "24": {
+ "desc": "RCDAT read parity error"
+ },
+ "25": {
+ "desc": "L2 castout or CN cresp addr err"
+ },
+ "26": {
+ "desc": "LVDIR took a parity error"
+ },
+ "27": {
+ "desc": "Bad topology table config software error"
+ },
+ "28": {
+ "desc": "Darn timed out waiting for data"
+ },
+ "29": {
+ "desc": "Early hang in L2"
+ },
+ "30": {
+ "desc": "Unexpected cast-out or push during chip_contained"
+ },
+ "31": {
+ "desc": "reserved"
+ },
+ "32": {
+ "desc": "Time out during PEC sequence trying to correct l2dir error"
+ },
+ "33": {
+ "desc": "reserved"
+ },
+ "34": {
+ "desc": "reserved"
+ },
+ "35": {
+ "desc": "reserved"
+ },
+ "36": {
+ "desc": "Cache CE and UE in short time period"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_L2_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_l3_fir.json b/chip_data/p10_10/node_eq_l3_fir.json
new file mode 100644
index 0000000..35ca70e
--- /dev/null
+++ b/chip_data/p10_10/node_eq_l3_fir.json
@@ -0,0 +1,373 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_L3_FIR": {
+ "instances": {
+ "0": "0x20018600",
+ "1": "0x20014600",
+ "2": "0x20012600",
+ "3": "0x20011600",
+ "4": "0x21018600",
+ "5": "0x21014600",
+ "6": "0x21012600",
+ "7": "0x21011600",
+ "8": "0x22018600",
+ "9": "0x22014600",
+ "10": "0x22012600",
+ "11": "0x22011600",
+ "12": "0x23018600",
+ "13": "0x23014600",
+ "14": "0x23012600",
+ "15": "0x23011600",
+ "16": "0x24018600",
+ "17": "0x24014600",
+ "18": "0x24012600",
+ "19": "0x24011600",
+ "20": "0x25018600",
+ "21": "0x25014600",
+ "22": "0x25012600",
+ "23": "0x25011600",
+ "24": "0x26018600",
+ "25": "0x26014600",
+ "26": "0x26012600",
+ "27": "0x26011600",
+ "28": "0x27018600",
+ "29": "0x27014600",
+ "30": "0x27012600",
+ "31": "0x27011600"
+ }
+ },
+ "EQ_L3_FIR_MASK": {
+ "instances": {
+ "0": "0x20018603",
+ "1": "0x20014603",
+ "2": "0x20012603",
+ "3": "0x20011603",
+ "4": "0x21018603",
+ "5": "0x21014603",
+ "6": "0x21012603",
+ "7": "0x21011603",
+ "8": "0x22018603",
+ "9": "0x22014603",
+ "10": "0x22012603",
+ "11": "0x22011603",
+ "12": "0x23018603",
+ "13": "0x23014603",
+ "14": "0x23012603",
+ "15": "0x23011603",
+ "16": "0x24018603",
+ "17": "0x24014603",
+ "18": "0x24012603",
+ "19": "0x24011603",
+ "20": "0x25018603",
+ "21": "0x25014603",
+ "22": "0x25012603",
+ "23": "0x25011603",
+ "24": "0x26018603",
+ "25": "0x26014603",
+ "26": "0x26012603",
+ "27": "0x26011603",
+ "28": "0x27018603",
+ "29": "0x27014603",
+ "30": "0x27012603",
+ "31": "0x27011603"
+ }
+ },
+ "EQ_L3_FIR_ACT0": {
+ "instances": {
+ "0": "0x20018606",
+ "1": "0x20014606",
+ "2": "0x20012606",
+ "3": "0x20011606",
+ "4": "0x21018606",
+ "5": "0x21014606",
+ "6": "0x21012606",
+ "7": "0x21011606",
+ "8": "0x22018606",
+ "9": "0x22014606",
+ "10": "0x22012606",
+ "11": "0x22011606",
+ "12": "0x23018606",
+ "13": "0x23014606",
+ "14": "0x23012606",
+ "15": "0x23011606",
+ "16": "0x24018606",
+ "17": "0x24014606",
+ "18": "0x24012606",
+ "19": "0x24011606",
+ "20": "0x25018606",
+ "21": "0x25014606",
+ "22": "0x25012606",
+ "23": "0x25011606",
+ "24": "0x26018606",
+ "25": "0x26014606",
+ "26": "0x26012606",
+ "27": "0x26011606",
+ "28": "0x27018606",
+ "29": "0x27014606",
+ "30": "0x27012606",
+ "31": "0x27011606"
+ }
+ },
+ "EQ_L3_FIR_ACT1": {
+ "instances": {
+ "0": "0x20018607",
+ "1": "0x20014607",
+ "2": "0x20012607",
+ "3": "0x20011607",
+ "4": "0x21018607",
+ "5": "0x21014607",
+ "6": "0x21012607",
+ "7": "0x21011607",
+ "8": "0x22018607",
+ "9": "0x22014607",
+ "10": "0x22012607",
+ "11": "0x22011607",
+ "12": "0x23018607",
+ "13": "0x23014607",
+ "14": "0x23012607",
+ "15": "0x23011607",
+ "16": "0x24018607",
+ "17": "0x24014607",
+ "18": "0x24012607",
+ "19": "0x24011607",
+ "20": "0x25018607",
+ "21": "0x25014607",
+ "22": "0x25012607",
+ "23": "0x25011607",
+ "24": "0x26018607",
+ "25": "0x26014607",
+ "26": "0x26012607",
+ "27": "0x26011607",
+ "28": "0x27018607",
+ "29": "0x27014607",
+ "30": "0x27012607",
+ "31": "0x27011607"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_L3_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "No members available for a CGC"
+ },
+ "1": {
+ "desc": "L3 attempted to master a CP (Castout/Push) command"
+ },
+ "2": {
+ "desc": "Access attempted to use invalid topology table entry"
+ },
+ "3": {
+ "desc": "L3 cache CE and UE within a short period"
+ },
+ "4": {
+ "desc": "CE detected on L3 cache read"
+ },
+ "5": {
+ "desc": "UE detected on L3 cache read"
+ },
+ "6": {
+ "desc": "SUE detected on L3 cache read"
+ },
+ "7": {
+ "desc": "L3 cache write data CE from Power Bus"
+ },
+ "8": {
+ "desc": "L3 cache write data UE from Power Bus"
+ },
+ "9": {
+ "desc": "L3 cache write data sue from Power Bus"
+ },
+ "10": {
+ "desc": "L3 cache write data CE from L2"
+ },
+ "11": {
+ "desc": "L3 cache write data UE from L2"
+ },
+ "12": {
+ "desc": "L3 cache write SUE from L2"
+ },
+ "13": {
+ "desc": "L3 DIR read CE"
+ },
+ "14": {
+ "desc": "L3 Dir read UE"
+ },
+ "15": {
+ "desc": "Dir error not found during corr seq"
+ },
+ "16": {
+ "desc": "Received addr_error cresp on Snoop Machine or Castout Operation"
+ },
+ "17": {
+ "desc": "Received addr_error cresp for Prefetch Operation"
+ },
+ "18": {
+ "desc": "L3_PB_HANG_POLL"
+ },
+ "19": {
+ "desc": "Invalid LRU count error"
+ },
+ "20": {
+ "desc": "Reserved"
+ },
+ "21": {
+ "desc": "Reserved"
+ },
+ "22": {
+ "desc": "Reserved"
+ },
+ "23": {
+ "desc": "Prefetch or Write Inject machine PowerBus data hang check"
+ },
+ "24": {
+ "desc": "L3 Hw control err"
+ },
+ "25": {
+ "desc": "Cache inhibited op in L3 directory"
+ },
+ "26": {
+ "desc": "L3 line delete CE done"
+ },
+ "27": {
+ "desc": "L3 snooped an incoming LCO"
+ },
+ "28": {
+ "desc": "LRU intended to victimize a line, but invalid line selected"
+ },
+ "29": {
+ "desc": "L3 cache congruence class deleted"
+ },
+ "30": {
+ "desc": "Incoming LCO ID mismatch"
+ },
+ "31": {
+ "desc": "L3 PowerBus Master Write CRESP ack_dead"
+ },
+ "32": {
+ "desc": "PB Master Read received ack_dead CRESP"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_L3_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_local_fir.json b/chip_data/p10_10/node_eq_local_fir.json
new file mode 100644
index 0000000..a94d5bf
--- /dev/null
+++ b/chip_data/p10_10/node_eq_local_fir.json
@@ -0,0 +1,469 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_LOCAL_FIR": {
+ "instances": {
+ "0": "0x20040100",
+ "1": "0x21040100",
+ "2": "0x22040100",
+ "3": "0x23040100",
+ "4": "0x24040100",
+ "5": "0x25040100",
+ "6": "0x26040100",
+ "7": "0x27040100"
+ }
+ },
+ "EQ_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x20040103",
+ "1": "0x21040103",
+ "2": "0x22040103",
+ "3": "0x23040103",
+ "4": "0x24040103",
+ "5": "0x25040103",
+ "6": "0x26040103",
+ "7": "0x27040103"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x20040106",
+ "1": "0x21040106",
+ "2": "0x22040106",
+ "3": "0x23040106",
+ "4": "0x24040106",
+ "5": "0x25040106",
+ "6": "0x26040106",
+ "7": "0x27040106"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x20040107",
+ "1": "0x21040107",
+ "2": "0x22040107",
+ "3": "0x23040107",
+ "4": "0x24040107",
+ "5": "0x25040107",
+ "6": "0x26040107",
+ "7": "0x27040107"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x20040109",
+ "1": "0x21040109",
+ "2": "0x22040109",
+ "3": "0x23040109",
+ "4": "0x24040109",
+ "5": "0x25040109",
+ "6": "0x26040109",
+ "7": "0x27040109"
+ }
+ },
+ "EQ_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x20040108",
+ "1": "0x21040108",
+ "2": "0x22040108",
+ "3": "0x23040108",
+ "4": "0x24040108",
+ "5": "0x25040108",
+ "6": "0x26040108",
+ "7": "0x27040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM1 - internal error"
+ },
+ "7": {
+ "desc": "THERM1 - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP1 - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP1 - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP1 - Voltage sense error"
+ },
+ "11": {
+ "desc": "THERM2 - internal error"
+ },
+ "12": {
+ "desc": "THERM2 - pcb error"
+ },
+ "13": {
+ "desc": "THERMTRIP2 - Critical temperature indicator"
+ },
+ "14": {
+ "desc": "THERMTRIP2 - Fatal temperature indicator"
+ },
+ "15": {
+ "desc": "VOLTTRIP2 - Voltage sense error"
+ },
+ "16": {
+ "desc": "DBG - scom parity fail"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "L30 Trace Err"
+ },
+ "21": {
+ "desc": "L31 Trace Err"
+ },
+ "22": {
+ "desc": "L32 Trace Err"
+ },
+ "23": {
+ "desc": "L33 Trace Err"
+ },
+ "24": {
+ "desc": "DCADJ FIR ERR Core 0"
+ },
+ "25": {
+ "desc": "DCADJ FIR ERR Core 1"
+ },
+ "26": {
+ "desc": "DCADJ FIR ERR Core 2"
+ },
+ "27": {
+ "desc": "DCADJ FIR ERR Core 3"
+ },
+ "28": {
+ "desc": "SKEWADJ FIR ERR Core0"
+ },
+ "29": {
+ "desc": "SKEWADJ FIR ERR Core1"
+ },
+ "30": {
+ "desc": "SKEWADJ FIR ERR Core2"
+ },
+ "31": {
+ "desc": "SKEWADJ FIR ERR Core3"
+ },
+ "32": {
+ "desc": "DC_SCOM_ERR_0"
+ },
+ "33": {
+ "desc": "DC_SCOM_ERR_1"
+ },
+ "34": {
+ "desc": "DC_SCOM_ERR_2"
+ },
+ "35": {
+ "desc": "DC_SCOM_ERR_3"
+ },
+ "36": {
+ "desc": "SKEW_SCOM_ERR_0"
+ },
+ "37": {
+ "desc": "SKEW_SCOM_ERR_1"
+ },
+ "38": {
+ "desc": "SKEW_SCOM_ERR_2"
+ },
+ "39": {
+ "desc": "SKEW_SCOM_ERR_3"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_ncu_fir.json b/chip_data/p10_10/node_eq_ncu_fir.json
new file mode 100644
index 0000000..566f3fd
--- /dev/null
+++ b/chip_data/p10_10/node_eq_ncu_fir.json
@@ -0,0 +1,361 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_NCU_FIR": {
+ "instances": {
+ "0": "0x20018640",
+ "1": "0x20014640",
+ "2": "0x20012640",
+ "3": "0x20011640",
+ "4": "0x21018640",
+ "5": "0x21014640",
+ "6": "0x21012640",
+ "7": "0x21011640",
+ "8": "0x22018640",
+ "9": "0x22014640",
+ "10": "0x22012640",
+ "11": "0x22011640",
+ "12": "0x23018640",
+ "13": "0x23014640",
+ "14": "0x23012640",
+ "15": "0x23011640",
+ "16": "0x24018640",
+ "17": "0x24014640",
+ "18": "0x24012640",
+ "19": "0x24011640",
+ "20": "0x25018640",
+ "21": "0x25014640",
+ "22": "0x25012640",
+ "23": "0x25011640",
+ "24": "0x26018640",
+ "25": "0x26014640",
+ "26": "0x26012640",
+ "27": "0x26011640",
+ "28": "0x27018640",
+ "29": "0x27014640",
+ "30": "0x27012640",
+ "31": "0x27011640"
+ }
+ },
+ "EQ_NCU_FIR_MASK": {
+ "instances": {
+ "0": "0x20018643",
+ "1": "0x20014643",
+ "2": "0x20012643",
+ "3": "0x20011643",
+ "4": "0x21018643",
+ "5": "0x21014643",
+ "6": "0x21012643",
+ "7": "0x21011643",
+ "8": "0x22018643",
+ "9": "0x22014643",
+ "10": "0x22012643",
+ "11": "0x22011643",
+ "12": "0x23018643",
+ "13": "0x23014643",
+ "14": "0x23012643",
+ "15": "0x23011643",
+ "16": "0x24018643",
+ "17": "0x24014643",
+ "18": "0x24012643",
+ "19": "0x24011643",
+ "20": "0x25018643",
+ "21": "0x25014643",
+ "22": "0x25012643",
+ "23": "0x25011643",
+ "24": "0x26018643",
+ "25": "0x26014643",
+ "26": "0x26012643",
+ "27": "0x26011643",
+ "28": "0x27018643",
+ "29": "0x27014643",
+ "30": "0x27012643",
+ "31": "0x27011643"
+ }
+ },
+ "EQ_NCU_FIR_ACT0": {
+ "instances": {
+ "0": "0x20018646",
+ "1": "0x20014646",
+ "2": "0x20012646",
+ "3": "0x20011646",
+ "4": "0x21018646",
+ "5": "0x21014646",
+ "6": "0x21012646",
+ "7": "0x21011646",
+ "8": "0x22018646",
+ "9": "0x22014646",
+ "10": "0x22012646",
+ "11": "0x22011646",
+ "12": "0x23018646",
+ "13": "0x23014646",
+ "14": "0x23012646",
+ "15": "0x23011646",
+ "16": "0x24018646",
+ "17": "0x24014646",
+ "18": "0x24012646",
+ "19": "0x24011646",
+ "20": "0x25018646",
+ "21": "0x25014646",
+ "22": "0x25012646",
+ "23": "0x25011646",
+ "24": "0x26018646",
+ "25": "0x26014646",
+ "26": "0x26012646",
+ "27": "0x26011646",
+ "28": "0x27018646",
+ "29": "0x27014646",
+ "30": "0x27012646",
+ "31": "0x27011646"
+ }
+ },
+ "EQ_NCU_FIR_ACT1": {
+ "instances": {
+ "0": "0x20018647",
+ "1": "0x20014647",
+ "2": "0x20012647",
+ "3": "0x20011647",
+ "4": "0x21018647",
+ "5": "0x21014647",
+ "6": "0x21012647",
+ "7": "0x21011647",
+ "8": "0x22018647",
+ "9": "0x22014647",
+ "10": "0x22012647",
+ "11": "0x22011647",
+ "12": "0x23018647",
+ "13": "0x23014647",
+ "14": "0x23012647",
+ "15": "0x23011647",
+ "16": "0x24018647",
+ "17": "0x24014647",
+ "18": "0x24012647",
+ "19": "0x24011647",
+ "20": "0x25018647",
+ "21": "0x25014647",
+ "22": "0x25012647",
+ "23": "0x25011647",
+ "24": "0x26018647",
+ "25": "0x26014647",
+ "26": "0x26012647",
+ "27": "0x26011647",
+ "28": "0x27018647",
+ "29": "0x27014647",
+ "30": "0x27012647",
+ "31": "0x27011647"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_NCU_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NCU store queue control error"
+ },
+ "1": {
+ "desc": "TLBIE control error"
+ },
+ "2": {
+ "desc": "TLBIE or SLBIEG received illegal fields from core"
+ },
+ "3": {
+ "desc": "Store address machine received addr_err cresp"
+ },
+ "4": {
+ "desc": "Load address machine received addr_err cresp"
+ },
+ "5": {
+ "desc": "Topology table error - tried accessing invalid entry"
+ },
+ "6": {
+ "desc": "An NCU machine triggerd PB into early hang recovery"
+ },
+ "7": {
+ "desc": "MSGSND received addr_err"
+ },
+ "8": {
+ "desc": "Store data parity error from regfile detected"
+ },
+ "9": {
+ "desc": "Store timed out on PB"
+ },
+ "10": {
+ "desc": "TLBIE master timed out on PB"
+ },
+ "11": {
+ "desc": "TLBIE snooper timed out waiting for core"
+ },
+ "12": {
+ "desc": "IMA received addr_err cresp"
+ },
+ "13": {
+ "desc": "TLBIE/sync machine received addr_err cresp"
+ },
+ "14": {
+ "desc": "PMISC received address error cresp"
+ },
+ "15": {
+ "desc": "spare"
+ },
+ "16": {
+ "desc": "spare"
+ },
+ "17": {
+ "desc": "spare"
+ },
+ "18": {
+ "desc": "spare"
+ },
+ "19": {
+ "desc": "Targeted nodal request got rty_inc cresp"
+ },
+ "20": {
+ "desc": "Darn ttype while darn not enabled"
+ },
+ "21": {
+ "desc": "Darn Address Error cresp"
+ },
+ "22": {
+ "desc": "spare"
+ },
+ "23": {
+ "desc": "spare"
+ },
+ "24": {
+ "desc": "spare"
+ },
+ "25": {
+ "desc": "spare"
+ },
+ "26": {
+ "desc": "spare"
+ },
+ "27": {
+ "desc": "spare"
+ },
+ "28": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_NCU_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_eq_qme_fir.json b/chip_data/p10_10/node_eq_qme_fir.json
new file mode 100644
index 0000000..6e59b5a
--- /dev/null
+++ b/chip_data/p10_10/node_eq_qme_fir.json
@@ -0,0 +1,236 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_QME_FIR": {
+ "instances": {
+ "0": "0x200E0000",
+ "1": "0x210E0000",
+ "2": "0x220E0000",
+ "3": "0x230E0000",
+ "4": "0x240E0000",
+ "5": "0x250E0000",
+ "6": "0x260E0000",
+ "7": "0x270E0000"
+ }
+ },
+ "EQ_QME_FIR_MASK": {
+ "instances": {
+ "0": "0x200E0004",
+ "1": "0x210E0004",
+ "2": "0x220E0004",
+ "3": "0x230E0004",
+ "4": "0x240E0004",
+ "5": "0x250E0004",
+ "6": "0x260E0004",
+ "7": "0x270E0004"
+ }
+ },
+ "EQ_QME_FIR_ACT0": {
+ "instances": {
+ "0": "0x200E0008",
+ "1": "0x210E0008",
+ "2": "0x220E0008",
+ "3": "0x230E0008",
+ "4": "0x240E0008",
+ "5": "0x250E0008",
+ "6": "0x260E0008",
+ "7": "0x270E0008"
+ }
+ },
+ "EQ_QME_FIR_ACT1": {
+ "instances": {
+ "0": "0x200E000C",
+ "1": "0x210E000C",
+ "2": "0x220E000C",
+ "3": "0x230E000C",
+ "4": "0x240E000C",
+ "5": "0x250E000C",
+ "6": "0x260E000C",
+ "7": "0x270E000C"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_QME_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PPE halted due to an error"
+ },
+ "1": {
+ "desc": "PPE asserted debug trigger"
+ },
+ "2": {
+ "desc": "Spare trigger for testing or workarounds"
+ },
+ "3": {
+ "desc": "PPE asserted a watchdog timeout condition"
+ },
+ "4": {
+ "desc": "QME hardware detected its own timeout on the PCB Slave interface"
+ },
+ "5": {
+ "desc": "Block Copy Engine or QME PPE direct access error from the Fabric"
+ },
+ "6": {
+ "desc": "SRAM Uncorrectable Error"
+ },
+ "7": {
+ "desc": "SRAM Correctable Error"
+ },
+ "8": {
+ "desc": "Resonant Clock Table array Parity Error"
+ },
+ "9": {
+ "desc": "PIG request of PCB interrupt before its previous interrupt completed"
+ },
+ "10": {
+ "desc": "Scrub timer tick occurred when scrub is still pending"
+ },
+ "11": {
+ "desc": "QME_LFIR_CTFS_ERR"
+ },
+ "12": {
+ "desc": "QME_LFIR_CPMS_ERR"
+ },
+ "13": {
+ "desc": "PGPE Heartbeat Lost from a hw deadman timer controlled by QHB"
+ },
+ "14": {
+ "desc": "BCE forward progress error"
+ },
+ "15": {
+ "desc": "Resclk TARGET_PSTATE Change Protocol Error"
+ },
+ "16": {
+ "desc": "PCB Network or Endpoint Reset occurred when QME was not halted"
+ },
+ "17": {
+ "desc": "Firmware cleared special wakeup request before SPECIAL_WKUP_DONE"
+ },
+ "18": {
+ "desc": "A new special wakeup right after previous cleared"
+ },
+ "19": {
+ "desc": "Core External Interrupt wakeup sources present but disabled by threads"
+ },
+ "20": {
+ "desc": "Core External Interrupt present but the chiplet is deconfigured"
+ },
+ "21": {
+ "desc": "Reserved"
+ },
+ "22": {
+ "desc": "PB read cmd waited too long for lost data (hang)"
+ },
+ "23": {
+ "desc": "PPE tried to write a protected addr as defined by the SWPR[n] register"
+ },
+ "24": {
+ "desc": "DTC Sequencer read a UE from SRAM"
+ },
+ "25": {
+ "desc": "Correctable error detected on incoming data for a PowerBus read"
+ },
+ "26": {
+ "desc": "UE Detected on incoming data for a PowerBus read"
+ },
+ "27": {
+ "desc": "SUE Detected on incoming data for a PowerBus read"
+ },
+ "28": {
+ "desc": "PB Request address hit an invalid entry in the TOPOLOGY XLATE TABLE"
+ },
+ "29": {
+ "desc": "Parity error detected on a powerbus tag"
+ },
+ "30": {
+ "desc": "Code attempted to write the PIG register when the previous request was still pending"
+ },
+ "31": {
+ "desc": "Local access error bit(s) set"
+ },
+ "32": {
+ "desc": "CE detected on read to the SSA located in QME powerbus routing logic"
+ },
+ "33": {
+ "desc": "UE detected on read to the SSA located in QME powerbus routing logic"
+ },
+ "34": {
+ "desc": "spare"
+ },
+ "35": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_gfir.json b/chip_data/p10_10/node_gfir.json
new file mode 100644
index 0000000..ff8a469
--- /dev/null
+++ b/chip_data/p10_10/node_gfir.json
@@ -0,0 +1,1435 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "GFIR_CS": {
+ "instances": {
+ "0": "0x570F001C"
+ }
+ },
+ "GFIR_RE": {
+ "instances": {
+ "0": "0x570F001B"
+ }
+ },
+ "GFIR_SPA": {
+ "instances": {
+ "0": "0x570F001A"
+ }
+ },
+ "GFIR_UCS": {
+ "instances": {
+ "0": "0x570F002A"
+ }
+ },
+ "GFIR_HA": {
+ "instances": {
+ "0": "0x570F002B"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "GFIR_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_CS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_RE"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_SPA"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_UCS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_HA"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ }
+ },
+ "root_nodes": {
+ "CS": {
+ "name": "GFIR_CS",
+ "inst": 0
+ },
+ "RE": {
+ "name": "GFIR_RE",
+ "inst": 0
+ },
+ "SPA": {
+ "name": "GFIR_SPA",
+ "inst": 0
+ },
+ "UCS": {
+ "name": "GFIR_UCS",
+ "inst": 0
+ },
+ "HA": {
+ "name": "GFIR_HA",
+ "inst": 0
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_hca_fir.json b/chip_data/p10_10/node_hca_fir.json
new file mode 100644
index 0000000..dcb8341
--- /dev/null
+++ b/chip_data/p10_10/node_hca_fir.json
@@ -0,0 +1,197 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "HCA_FIR": {
+ "instances": {
+ "0": "0x03011D40"
+ }
+ },
+ "HCA_FIR_MASK": {
+ "instances": {
+ "0": "0x03011D43"
+ }
+ },
+ "HCA_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011D46"
+ }
+ },
+ "HCA_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011D47"
+ }
+ },
+ "HCA_FIR_WOF": {
+ "instances": {
+ "0": "0x03011D48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "HCA_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Powerbus rcmd address parity error"
+ },
+ "1": {
+ "desc": "Powerbus rcmd ttag parity error"
+ },
+ "2": {
+ "desc": "Powerbus cresp ttag parity error"
+ },
+ "3": {
+ "desc": "Powerbus cresp atag parity error"
+ },
+ "4": {
+ "desc": "HCA updt received addr_err cresp"
+ },
+ "5": {
+ "desc": "HCA updt received invalid cresp"
+ },
+ "6": {
+ "desc": "HCA updt received unexpected cresp"
+ },
+ "7": {
+ "desc": "HCA detected powerbus hang"
+ },
+ "8": {
+ "desc": "HCA rcmd hits both BARs"
+ },
+ "9": {
+ "desc": "HCA cache array correctable error"
+ },
+ "10": {
+ "desc": "HCA cache array uncorrectable error"
+ },
+ "11": {
+ "desc": "HCA rcmd drop counter overflow"
+ },
+ "12": {
+ "desc": "HCA updt command drop counter overflow"
+ },
+ "13": {
+ "desc": "HCA updt lost decay request. No pbi machine available."
+ },
+ "14": {
+ "desc": "ADU or PSI SMF error"
+ },
+ "15": {
+ "desc": "Spare FIR bit"
+ },
+ "16": {
+ "desc": "ADU recoverable error 0"
+ },
+ "17": {
+ "desc": "ADU recoverable error 1"
+ },
+ "18": {
+ "desc": "ADU recoverable error 2"
+ },
+ "19": {
+ "desc": "ADU recoverable error 3"
+ },
+ "20": {
+ "desc": "ADU recoverable error 4"
+ },
+ "21": {
+ "desc": "ADU recoverable error 5"
+ },
+ "22": {
+ "desc": "ADU checkstop error 0"
+ },
+ "23": {
+ "desc": "ADU checkstop error 1"
+ },
+ "24": {
+ "desc": "ADU checkstop error 2"
+ },
+ "25": {
+ "desc": "ADU checkstop error 3"
+ },
+ "26": {
+ "desc": "ADU checkstop error 4"
+ },
+ "27": {
+ "desc": "ADU checkstop error 5"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "HCA_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_int_cq_fir.json b/chip_data/p10_10/node_int_cq_fir.json
new file mode 100644
index 0000000..8b6747f
--- /dev/null
+++ b/chip_data/p10_10/node_int_cq_fir.json
@@ -0,0 +1,336 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "INT_CQ_FIR": {
+ "instances": {
+ "0": "0x02010830"
+ }
+ },
+ "INT_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02010833"
+ }
+ },
+ "INT_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010836"
+ }
+ },
+ "INT_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010837"
+ }
+ },
+ "INT_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02010838"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "INT_CQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CE while consuming data from the PowerBus Data ramp"
+ },
+ "1": {
+ "desc": "UE while consuming data from the PowerBus Data ramp"
+ },
+ "2": {
+ "desc": "SUE while consuming data from the PowerBus Data ramp"
+ },
+ "3": {
+ "desc": "CE while reading the PowerBus Data In Array"
+ },
+ "4": {
+ "desc": "UE detected while reading the PowerBus Data In Array"
+ },
+ "5": {
+ "desc": "CE while reading the PowerBus Data Out Array"
+ },
+ "6": {
+ "desc": "UE while reading the PowerBus Data Out Array"
+ },
+ "7": {
+ "desc": "CE while consuming data on the AIB Data Bus"
+ },
+ "8": {
+ "desc": "UE while consuming data on the AIB Data Bus"
+ },
+ "9": {
+ "desc": "Received an unsolicited master Combined Response"
+ },
+ "10": {
+ "desc": "Received unsolicited PowerBus data"
+ },
+ "11": {
+ "desc": "Parity error detected on AIB credit signals from PC"
+ },
+ "12": {
+ "desc": "Parity error detected on AIB credit available signals from PC"
+ },
+ "13": {
+ "desc": "Parity error detected on AIB credit signals from VC"
+ },
+ "14": {
+ "desc": "Parity error detected on AIB credit available signals from VC"
+ },
+ "15": {
+ "desc": "Parity error detected on AIB Command Control"
+ },
+ "16": {
+ "desc": "Parity error detected on AIB Command Bus"
+ },
+ "17": {
+ "desc": "Parity error detected on AIB Data Control"
+ },
+ "18": {
+ "desc": "Parity err detected in a PowerBus interface(Rcmdx, cRespx, Data rtag)"
+ },
+ "19": {
+ "desc": "Slave CI Store or CI Load to an improper location"
+ },
+ "20": {
+ "desc": "Slave CI Store or CI Load to an invalid Set Translation Table entry"
+ },
+ "21": {
+ "desc": "Slave CI Store or CI Load error (targeting IC_BAR)"
+ },
+ "22": {
+ "desc": "Slave CI Store or CI Load error (not targetting IC_BAR)"
+ },
+ "23": {
+ "desc": "Migration Register Table (MRT) access - invalid entry selected"
+ },
+ "24": {
+ "desc": "Migration Register Table (MRT) access - size error"
+ },
+ "25": {
+ "desc": "SCOM satellite error"
+ },
+ "26": {
+ "desc": "Topology ID Index Translation Table Entry Invalid"
+ },
+ "27": {
+ "desc": "Master Write Queue has flagged a PowerBus operational hang"
+ },
+ "28": {
+ "desc": "Master Read Queue has flagged a PowerBus operational hang"
+ },
+ "29": {
+ "desc": "Master Interrupt Queue has flagged a PowerBus operational hang"
+ },
+ "30": {
+ "desc": "Master Read Queue has flagged a PowerBus data hang"
+ },
+ "31": {
+ "desc": "CI Store Queue has flagged a PowerBus data hang"
+ },
+ "32": {
+ "desc": "CI Load Queue has flagged an AIB data hang"
+ },
+ "33": {
+ "desc": "Bad cResp received during a Master Write command"
+ },
+ "34": {
+ "desc": "Bad cResp received during a Master Read command"
+ },
+ "35": {
+ "desc": "Bad cResp received during a Master Interrupt command"
+ },
+ "36": {
+ "desc": "A Master Read machine received cResp of abort_trm or abort_trm_ed"
+ },
+ "37": {
+ "desc": "Master Interrupt Protocol Error"
+ },
+ "38": {
+ "desc": "Master Memory Op Targeted Secure Memory"
+ },
+ "39": {
+ "desc": "AIB Fence Raised"
+ },
+ "40": {
+ "desc": "Parity error detected on CQs configuration registers"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "Command Queue (FSM) severe error summary"
+ },
+ "43": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "44": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "45": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "46": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "47": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "48": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "49": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "50": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "51": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "52": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "53": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "54": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "55": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "56": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "57": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "58": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "59": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "60": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "61": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ },
+ "62": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ },
+ "63": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "INT_CQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_iohs_local_fir.json b/chip_data/p10_10/node_iohs_local_fir.json
new file mode 100644
index 0000000..a303b13
--- /dev/null
+++ b/chip_data/p10_10/node_iohs_local_fir.json
@@ -0,0 +1,469 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "IOHS_LOCAL_FIR": {
+ "instances": {
+ "0": "0x18040100",
+ "1": "0x19040100",
+ "2": "0x1A040100",
+ "3": "0x1B040100",
+ "4": "0x1C040100",
+ "5": "0x1D040100",
+ "6": "0x1E040100",
+ "7": "0x1F040100"
+ }
+ },
+ "IOHS_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x18040103",
+ "1": "0x19040103",
+ "2": "0x1A040103",
+ "3": "0x1B040103",
+ "4": "0x1C040103",
+ "5": "0x1D040103",
+ "6": "0x1E040103",
+ "7": "0x1F040103"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x18040106",
+ "1": "0x19040106",
+ "2": "0x1A040106",
+ "3": "0x1B040106",
+ "4": "0x1C040106",
+ "5": "0x1D040106",
+ "6": "0x1E040106",
+ "7": "0x1F040106"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x18040107",
+ "1": "0x19040107",
+ "2": "0x1A040107",
+ "3": "0x1B040107",
+ "4": "0x1C040107",
+ "5": "0x1D040107",
+ "6": "0x1E040107",
+ "7": "0x1F040107"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x18040109",
+ "1": "0x19040109",
+ "2": "0x1A040109",
+ "3": "0x1B040109",
+ "4": "0x1C040109",
+ "5": "0x1D040109",
+ "6": "0x1E040109",
+ "7": "0x1F040109"
+ }
+ },
+ "IOHS_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x18040108",
+ "1": "0x19040108",
+ "2": "0x1A040108",
+ "3": "0x1B040108",
+ "4": "0x1C040108",
+ "5": "0x1D040108",
+ "6": "0x1E040108",
+ "7": "0x1F040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "IOHS_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - interal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_lpc_fir.json b/chip_data/p10_10/node_lpc_fir.json
new file mode 100644
index 0000000..7d7131f
--- /dev/null
+++ b/chip_data/p10_10/node_lpc_fir.json
@@ -0,0 +1,135 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "LPC_FIR": {
+ "instances": {
+ "0": "0x03012000"
+ }
+ },
+ "LPC_FIR_MASK": {
+ "instances": {
+ "0": "0x03012003"
+ }
+ },
+ "LPC_FIR_ACT0": {
+ "instances": {
+ "0": "0x03012006"
+ }
+ },
+ "LPC_FIR_ACT1": {
+ "instances": {
+ "0": "0x03012007"
+ }
+ },
+ "LPC_FIR_WOF": {
+ "instances": {
+ "0": "0x03012008"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "LPC_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OPB_Master_LS_received_a_transfer_size_value_unequal_to_1-_or_2-_or_4-Byte"
+ },
+ "1": {
+ "desc": "OPB_Master_LS_received_a_invalid_command_no_ci_store_and_no_ci_load"
+ },
+ "2": {
+ "desc": "OPB_Master_LS_received_a_address_which_was_not_aligned_to_the_received_transfer_size"
+ },
+ "3": {
+ "desc": "OPB_Master_LS_detected_OPB_ErrAck_which_was_activated_by_the_accessed_OPB_slave"
+ },
+ "4": {
+ "desc": "the_OPB_arbiter_activated_the_OPB_Timeout_signal_Typical_reason_is_that_the_OPB_access_did_not_hit_any_available_OPB_slave"
+ },
+ "5": {
+ "desc": "the_OPB_Master_LS_was_not_able_to_end_the_requested_OPB_access_within_the_OPB_Master_LS_hang_timeout_time"
+ },
+ "6": {
+ "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_command_buffer"
+ },
+ "7": {
+ "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_data_buffer"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_dstl_fir.json b/chip_data/p10_10/node_mc_dstl_fir.json
new file mode 100644
index 0000000..2a9f6b1
--- /dev/null
+++ b/chip_data/p10_10/node_mc_dstl_fir.json
@@ -0,0 +1,409 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_DSTL_FIR": {
+ "instances": {
+ "0": "0x0C010D00",
+ "1": "0x0C010D40",
+ "2": "0x0D010D00",
+ "3": "0x0D010D40",
+ "4": "0x0E010D00",
+ "5": "0x0E010D40",
+ "6": "0x0F010D00",
+ "7": "0x0F010D40"
+ }
+ },
+ "MC_DSTL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010D03",
+ "1": "0x0C010D43",
+ "2": "0x0D010D03",
+ "3": "0x0D010D43",
+ "4": "0x0E010D03",
+ "5": "0x0E010D43",
+ "6": "0x0F010D03",
+ "7": "0x0F010D43"
+ }
+ },
+ "MC_DSTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010D06",
+ "1": "0x0C010D46",
+ "2": "0x0D010D06",
+ "3": "0x0D010D46",
+ "4": "0x0E010D06",
+ "5": "0x0E010D46",
+ "6": "0x0F010D06",
+ "7": "0x0F010D46"
+ }
+ },
+ "MC_DSTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010D07",
+ "1": "0x0C010D47",
+ "2": "0x0D010D07",
+ "3": "0x0D010D47",
+ "4": "0x0E010D07",
+ "5": "0x0E010D47",
+ "6": "0x0F010D07",
+ "7": "0x0F010D47"
+ }
+ },
+ "MC_DSTL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010D09",
+ "1": "0x0C010D49",
+ "2": "0x0D010D09",
+ "3": "0x0D010D49",
+ "4": "0x0E010D09",
+ "5": "0x0E010D49",
+ "6": "0x0F010D09",
+ "7": "0x0F010D49"
+ }
+ },
+ "MC_DSTL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010D08",
+ "1": "0x0C010D48",
+ "2": "0x0D010D08",
+ "3": "0x0D010D48",
+ "4": "0x0E010D08",
+ "5": "0x0E010D48",
+ "6": "0x0F010D08",
+ "7": "0x0F010D48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_DSTL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Subchannel A AFU initiated Checkstop"
+ },
+ "1": {
+ "desc": "Subchannel A AFU initiated Recoverable Attention"
+ },
+ "2": {
+ "desc": "Subchannel A AFU initiated Special Attention"
+ },
+ "3": {
+ "desc": "Subchannel A AFU initiated Application Interrupt Attention"
+ },
+ "4": {
+ "desc": "Subchannel B AFU initiated Checkstop"
+ },
+ "5": {
+ "desc": "Subchannel B AFU initiated Recoverable Attention"
+ },
+ "6": {
+ "desc": "Subchannel B AFU initiated Special Attention"
+ },
+ "7": {
+ "desc": "Subchannel B AFU initiated Application Interrupt Attention"
+ },
+ "8": {
+ "desc": "Error on parity bits protecting incoming command from MCS to DSTL"
+ },
+ "9": {
+ "desc": "A credit reset was attempted while rd and wdf buffers in use"
+ },
+ "10": {
+ "desc": "Config reg recoverable parity error"
+ },
+ "11": {
+ "desc": "Config reg fatal parity error"
+ },
+ "12": {
+ "desc": "Subchannel A counter error"
+ },
+ "13": {
+ "desc": "Subchannel B counter error"
+ },
+ "14": {
+ "desc": "Subchannel A valid cmd timeout error"
+ },
+ "15": {
+ "desc": "Subchannel B valid cmd timeout error"
+ },
+ "16": {
+ "desc": "Subchannel A buffer overuse error"
+ },
+ "17": {
+ "desc": "Subchannel B buffer overuse error"
+ },
+ "18": {
+ "desc": "Subchannel A DL link down"
+ },
+ "19": {
+ "desc": "Subchannel B DL link down"
+ },
+ "20": {
+ "desc": "Subchannel A has entered the fail state"
+ },
+ "21": {
+ "desc": "Subchannel B has entered the fail state"
+ },
+ "22": {
+ "desc": "Subchannel A Channel timeout"
+ },
+ "23": {
+ "desc": "Subchannel B Channel timeout"
+ },
+ "24": {
+ "desc": "decrypt err: scom reg has parity error"
+ },
+ "25": {
+ "desc": "decrypt err: attempt to write or access key when locked"
+ },
+ "26": {
+ "desc": "decrypt err: address pipe parity error"
+ },
+ "27": {
+ "desc": "decrypt err: CL to decrypt parity error on valid tag"
+ },
+ "28": {
+ "desc": "decrypt err: parity error on USTL decrypt DMX interface"
+ },
+ "29": {
+ "desc": "encrypt err: scom reg has parity error"
+ },
+ "30": {
+ "desc": "encrypt err: attempt to write or access key when locked"
+ },
+ "31": {
+ "desc": "encrypt err: parity error on address encryption rounds"
+ },
+ "32": {
+ "desc": "encrypt err: parity error on data encryption rounds"
+ },
+ "33": {
+ "desc": "Subchannel A AFU Application Interrupt Attention while another in process"
+ },
+ "34": {
+ "desc": "Subchannel B AFU Application Interrupt Attention while another in process"
+ },
+ "35": {
+ "desc": "A parity error local to Subchhanel A occurred"
+ },
+ "36": {
+ "desc": "A parity error local to Subchhanel B occurred"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_DSTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_fir.json b/chip_data/p10_10/node_mc_fir.json
new file mode 100644
index 0000000..2e23008
--- /dev/null
+++ b/chip_data/p10_10/node_mc_fir.json
@@ -0,0 +1,336 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_FIR": {
+ "instances": {
+ "0": "0x0C010C00",
+ "1": "0x0D010C00",
+ "2": "0x0E010C00",
+ "3": "0x0F010C00"
+ }
+ },
+ "MC_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010C03",
+ "1": "0x0D010C03",
+ "2": "0x0E010C03",
+ "3": "0x0F010C03"
+ }
+ },
+ "MC_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010C06",
+ "1": "0x0D010C06",
+ "2": "0x0E010C06",
+ "3": "0x0F010C06"
+ }
+ },
+ "MC_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010C07",
+ "1": "0x0D010C07",
+ "2": "0x0E010C07",
+ "3": "0x0F010C07"
+ }
+ },
+ "MC_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010C09",
+ "1": "0x0D010C09",
+ "2": "0x0E010C09",
+ "3": "0x0F010C09"
+ }
+ },
+ "MC_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010C08",
+ "1": "0x0D010C08",
+ "2": "0x0E010C08",
+ "3": "0x0F010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "MC internal recoverable error"
+ },
+ "1": {
+ "desc": "MC internal non-recoverable error"
+ },
+ "2": {
+ "desc": "MC powerbus protocol error"
+ },
+ "3": {
+ "desc": "MC inband bar with incorrect ttype"
+ },
+ "4": {
+ "desc": "MC multiple BAR hit"
+ },
+ "5": {
+ "desc": "Non-zero ECC syndrome for PowerBus write data"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "reserved"
+ },
+ "8": {
+ "desc": "Command list state machine timeout"
+ },
+ "9": {
+ "desc": "reserved"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "WAT0 event occurred"
+ },
+ "12": {
+ "desc": "WAT1 event occurred"
+ },
+ "13": {
+ "desc": "WAT2 event occurred"
+ },
+ "14": {
+ "desc": "WAT3 event occurred"
+ },
+ "15": {
+ "desc": "Plus One Prefetch generated command did not hit any BARs"
+ },
+ "16": {
+ "desc": "Plus One Prefetch generated command hit config or mmio BAR"
+ },
+ "17": {
+ "desc": "Parity Error in WAT/Debug config register"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Incoming Powerbus Command hit multiple valid configured topology IDs"
+ },
+ "21": {
+ "desc": "reserved"
+ },
+ "22": {
+ "desc": "Secure mem facility access privilege error by originating thread"
+ },
+ "23": {
+ "desc": "Multiple sync cmds received by an MC, or while one is pending"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_local_fir.json b/chip_data/p10_10/node_mc_local_fir.json
new file mode 100644
index 0000000..038c95a
--- /dev/null
+++ b/chip_data/p10_10/node_mc_local_fir.json
@@ -0,0 +1,445 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_LOCAL_FIR": {
+ "instances": {
+ "0": "0x0C040100",
+ "1": "0x0D040100",
+ "2": "0x0E040100",
+ "3": "0x0F040100"
+ }
+ },
+ "MC_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C040103",
+ "1": "0x0D040103",
+ "2": "0x0E040103",
+ "3": "0x0F040103"
+ }
+ },
+ "MC_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C040106",
+ "1": "0x0D040106",
+ "2": "0x0E040106",
+ "3": "0x0F040106"
+ }
+ },
+ "MC_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C040107",
+ "1": "0x0D040107",
+ "2": "0x0E040107",
+ "3": "0x0F040107"
+ }
+ },
+ "MC_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C040109",
+ "1": "0x0D040109",
+ "2": "0x0E040109",
+ "3": "0x0F040109"
+ }
+ },
+ "MC_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C040108",
+ "1": "0x0D040108",
+ "2": "0x0E040108",
+ "3": "0x0F040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_misc_fir.json b/chip_data/p10_10/node_mc_misc_fir.json
new file mode 100644
index 0000000..ed38bf0
--- /dev/null
+++ b/chip_data/p10_10/node_mc_misc_fir.json
@@ -0,0 +1,300 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_MISC_FIR": {
+ "instances": {
+ "0": "0x0C010F00",
+ "1": "0x0D010F00",
+ "2": "0x0E010F00",
+ "3": "0x0F010F00"
+ }
+ },
+ "MC_MISC_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010F03",
+ "1": "0x0D010F03",
+ "2": "0x0E010F03",
+ "3": "0x0F010F03"
+ }
+ },
+ "MC_MISC_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010F06",
+ "1": "0x0D010F06",
+ "2": "0x0E010F06",
+ "3": "0x0F010F06"
+ }
+ },
+ "MC_MISC_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010F07",
+ "1": "0x0D010F07",
+ "2": "0x0E010F07",
+ "3": "0x0F010F07"
+ }
+ },
+ "MC_MISC_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010F09",
+ "1": "0x0D010F09",
+ "2": "0x0E010F09",
+ "3": "0x0F010F09"
+ }
+ },
+ "MC_MISC_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010F08",
+ "1": "0x0D010F08",
+ "2": "0x0E010F08",
+ "3": "0x0F010F08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_MISC_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "WAT Debug Bus Attention"
+ },
+ "1": {
+ "desc": "SCOM DBGSRC Register parity Error"
+ },
+ "2": {
+ "desc": "SCOM Recoverable Register Parity Error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "Application interrupt received from OCMB on channel 0, subchannel A"
+ },
+ "5": {
+ "desc": "Application interrupt received from OCMB on channel 0, subchannel B"
+ },
+ "6": {
+ "desc": "Application interrupt received from OCMB on channel 1, subchannel A"
+ },
+ "7": {
+ "desc": "Application interrupt received from OCMB on channel 1, subchannel B"
+ },
+ "8": {
+ "desc": "Parity Error taken on MCEBUSEN[0,1,2,3] regs"
+ },
+ "9": {
+ "desc": "Parity Error taken on WAT* Regs"
+ },
+ "10": {
+ "desc": "Reserved"
+ },
+ "11": {
+ "desc": "Reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_MISC_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_omi_dl_fir.json b/chip_data/p10_10/node_mc_omi_dl_fir.json
new file mode 100644
index 0000000..97adfb4
--- /dev/null
+++ b/chip_data/p10_10/node_mc_omi_dl_fir.json
@@ -0,0 +1,398 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_OMI_DL_FIR": {
+ "instances": {
+ "0": "0x0C011400",
+ "1": "0x0C011800",
+ "2": "0x0D011400",
+ "3": "0x0D011800",
+ "4": "0x0E011400",
+ "5": "0x0E011800",
+ "6": "0x0F011400",
+ "7": "0x0F011800"
+ }
+ },
+ "MC_OMI_DL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C011403",
+ "1": "0x0C011803",
+ "2": "0x0D011403",
+ "3": "0x0D011803",
+ "4": "0x0E011403",
+ "5": "0x0E011803",
+ "6": "0x0F011403",
+ "7": "0x0F011803"
+ }
+ },
+ "MC_OMI_DL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C011406",
+ "1": "0x0C011806",
+ "2": "0x0D011406",
+ "3": "0x0D011806",
+ "4": "0x0E011406",
+ "5": "0x0E011806",
+ "6": "0x0F011406",
+ "7": "0x0F011806"
+ }
+ },
+ "MC_OMI_DL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C011407",
+ "1": "0x0C011807",
+ "2": "0x0D011407",
+ "3": "0x0D011807",
+ "4": "0x0E011407",
+ "5": "0x0E011807",
+ "6": "0x0F011407",
+ "7": "0x0F011807"
+ }
+ },
+ "MC_OMI_DL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C011408",
+ "1": "0x0C011808",
+ "2": "0x0D011408",
+ "3": "0x0D011808",
+ "4": "0x0E011408",
+ "5": "0x0E011808",
+ "6": "0x0F011408",
+ "7": "0x0F011808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_OMI_DL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OMI-DL0 fatal error",
+ "child_node": {
+ "name": "MC_OMI_DL_ERR_RPT",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ }
+ },
+ "1": {
+ "desc": "OMI-DL0 UE on data flit"
+ },
+ "2": {
+ "desc": "OMI-DL0 CE on TL flit"
+ },
+ "3": {
+ "desc": "OMI-DL0 detected a CRC error"
+ },
+ "4": {
+ "desc": "OMI-DL0 received a nack"
+ },
+ "5": {
+ "desc": "OMI-DL0 running in degraded mode"
+ },
+ "6": {
+ "desc": "OMI-DL0 parity error detection on a lane"
+ },
+ "7": {
+ "desc": "OMI-DL0 retrained due to no forward progress"
+ },
+ "8": {
+ "desc": "OMI-DL0 remote side initiated a retrain"
+ },
+ "9": {
+ "desc": "OMI-DL0 retrain due to internal error or software"
+ },
+ "10": {
+ "desc": "OMI-DL0 threshold reached"
+ },
+ "11": {
+ "desc": "OMI-DL0 trained"
+ },
+ "12": {
+ "desc": "OMI-DL0 endpoint error bit 0"
+ },
+ "13": {
+ "desc": "OMI-DL0 endpoint error bit 1"
+ },
+ "14": {
+ "desc": "OMI-DL0 endpoint error bit 2"
+ },
+ "15": {
+ "desc": "OMI-DL0 endpoint error bit 3"
+ },
+ "16": {
+ "desc": "OMI-DL0 endpoint error bit 4"
+ },
+ "17": {
+ "desc": "OMI-DL0 endpoint error bit 5"
+ },
+ "18": {
+ "desc": "OMI-DL0 endpoint error bit 6"
+ },
+ "19": {
+ "desc": "OMI-DL0 endpoint error bit 7"
+ },
+ "20": {
+ "desc": "OMI-DL1 fatal error",
+ "child_node": {
+ "name": "MC_OMI_DL_ERR_RPT",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ }
+ },
+ "21": {
+ "desc": "OMI-DL1 UE on data flit"
+ },
+ "22": {
+ "desc": "OMI-DL1 CE on TL flit"
+ },
+ "23": {
+ "desc": "OMI-DL1 detected a CRC error"
+ },
+ "24": {
+ "desc": "OMI-DL1 received a nack"
+ },
+ "25": {
+ "desc": "OMI-DL1 running in degraded mode"
+ },
+ "26": {
+ "desc": "OMI-DL1 parity error detection on a lane"
+ },
+ "27": {
+ "desc": "OMI-DL1 retrained due to no forward progress"
+ },
+ "28": {
+ "desc": "OMI-DL1 remote side initiated a retrain"
+ },
+ "29": {
+ "desc": "OMI-DL1 retrain due to internal error or software"
+ },
+ "30": {
+ "desc": "OMI-DL1 threshold reached"
+ },
+ "31": {
+ "desc": "OMI-DL1 trained"
+ },
+ "32": {
+ "desc": "OMI-DL1 endpoint error bit 0"
+ },
+ "33": {
+ "desc": "OMI-DL1 endpoint error bit 1"
+ },
+ "34": {
+ "desc": "OMI-DL1 endpoint error bit 2"
+ },
+ "35": {
+ "desc": "OMI-DL1 endpoint error bit 3"
+ },
+ "36": {
+ "desc": "OMI-DL1 endpoint error bit 4"
+ },
+ "37": {
+ "desc": "OMI-DL1 endpoint error bit 5"
+ },
+ "38": {
+ "desc": "OMI-DL1 endpoint error bit 6"
+ },
+ "39": {
+ "desc": "OMI-DL1 endpoint error bit 7"
+ },
+ "40": {
+ "desc": "OMI-DL2 unused"
+ },
+ "41": {
+ "desc": "OMI-DL2 unused"
+ },
+ "42": {
+ "desc": "OMI-DL2 unused"
+ },
+ "43": {
+ "desc": "OMI-DL2 unused"
+ },
+ "44": {
+ "desc": "OMI-DL2 unused"
+ },
+ "45": {
+ "desc": "OMI-DL2 unused"
+ },
+ "46": {
+ "desc": "OMI-DL2 unused"
+ },
+ "47": {
+ "desc": "OMI-DL2 unused"
+ },
+ "48": {
+ "desc": "OMI-DL2 unused"
+ },
+ "49": {
+ "desc": "OMI-DL2 unused"
+ },
+ "50": {
+ "desc": "OMI-DL2 unused"
+ },
+ "51": {
+ "desc": "OMI-DL2 unused"
+ },
+ "52": {
+ "desc": "OMI-DL2 unused"
+ },
+ "53": {
+ "desc": "OMI-DL2 unused"
+ },
+ "54": {
+ "desc": "OMI-DL2 unused"
+ },
+ "55": {
+ "desc": "OMI-DL2 unused"
+ },
+ "56": {
+ "desc": "OMI-DL2 unused"
+ },
+ "57": {
+ "desc": "OMI-DL2 unused"
+ },
+ "58": {
+ "desc": "OMI-DL2 unused"
+ },
+ "59": {
+ "desc": "OMI-DL2 unused"
+ },
+ "60": {
+ "desc": "Performance monitor wrapped"
+ },
+ "61": {
+ "desc": "OMI-DL common FIR Register"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_OMI_DL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mc_ustl_fir.json b/chip_data/p10_10/node_mc_ustl_fir.json
new file mode 100644
index 0000000..d138b6c
--- /dev/null
+++ b/chip_data/p10_10/node_mc_ustl_fir.json
@@ -0,0 +1,478 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_USTL_FIR": {
+ "instances": {
+ "0": "0x0C010E00",
+ "1": "0x0C010E40",
+ "2": "0x0D010E00",
+ "3": "0x0D010E40",
+ "4": "0x0E010E00",
+ "5": "0x0E010E40",
+ "6": "0x0F010E00",
+ "7": "0x0F010E40"
+ }
+ },
+ "MC_USTL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010E03",
+ "1": "0x0C010E43",
+ "2": "0x0D010E03",
+ "3": "0x0D010E43",
+ "4": "0x0E010E03",
+ "5": "0x0E010E43",
+ "6": "0x0F010E03",
+ "7": "0x0F010E43"
+ }
+ },
+ "MC_USTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010E06",
+ "1": "0x0C010E46",
+ "2": "0x0D010E06",
+ "3": "0x0D010E46",
+ "4": "0x0E010E06",
+ "5": "0x0E010E46",
+ "6": "0x0F010E06",
+ "7": "0x0F010E46"
+ }
+ },
+ "MC_USTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010E07",
+ "1": "0x0C010E47",
+ "2": "0x0D010E07",
+ "3": "0x0D010E47",
+ "4": "0x0E010E07",
+ "5": "0x0E010E47",
+ "6": "0x0F010E07",
+ "7": "0x0F010E47"
+ }
+ },
+ "MC_USTL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010E09",
+ "1": "0x0C010E49",
+ "2": "0x0D010E09",
+ "3": "0x0D010E49",
+ "4": "0x0E010E09",
+ "5": "0x0E010E49",
+ "6": "0x0F010E09",
+ "7": "0x0F010E49"
+ }
+ },
+ "MC_USTL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010E08",
+ "1": "0x0C010E48",
+ "2": "0x0D010E08",
+ "3": "0x0D010E48",
+ "4": "0x0E010E08",
+ "5": "0x0E010E48",
+ "6": "0x0F010E08",
+ "7": "0x0F010E48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_USTL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Unexpected Flit Data showed up for Chana"
+ },
+ "1": {
+ "desc": "Unexpected Flit Data showed up for Chanb"
+ },
+ "2": {
+ "desc": "A unsupported template for a command flit for chana"
+ },
+ "3": {
+ "desc": "A unsupported template for a command flit for chanb"
+ },
+ "4": {
+ "desc": "Reserved"
+ },
+ "5": {
+ "desc": "Reserved"
+ },
+ "6": {
+ "desc": "WDF CE detected on buffer output"
+ },
+ "7": {
+ "desc": "WDF UE detected on buffer output"
+ },
+ "8": {
+ "desc": "WDF SUE detected on buffer output"
+ },
+ "9": {
+ "desc": "WDF buffer overrun detected"
+ },
+ "10": {
+ "desc": "WDF detected parity on USTL tag interface"
+ },
+ "11": {
+ "desc": "WDF detected a scom sequencer error"
+ },
+ "12": {
+ "desc": "WDF detected a pwctl sequencer error"
+ },
+ "13": {
+ "desc": "WDF detected a parity error on the misc_reg scom register"
+ },
+ "14": {
+ "desc": "Parity Error detected in WDF for CL pop"
+ },
+ "15": {
+ "desc": "WDF detected a non-zero syndrome (CE ore UE) from USTL"
+ },
+ "16": {
+ "desc": "WDF CMD parity errror"
+ },
+ "17": {
+ "desc": "Unused"
+ },
+ "18": {
+ "desc": "Unused"
+ },
+ "19": {
+ "desc": "Read Buffers overflowed/underflowed (more than 64 in use)"
+ },
+ "20": {
+ "desc": "WRT CE detected on buffer output"
+ },
+ "21": {
+ "desc": "WRT UE detected on buffer output"
+ },
+ "22": {
+ "desc": "WRT SUE detected on buffer output"
+ },
+ "23": {
+ "desc": "WRT detected a scom sequencer error"
+ },
+ "24": {
+ "desc": "WRT detected a parity error on the misc_reg scom register"
+ },
+ "25": {
+ "desc": "WRT Data Syndrome not equal to 0 for input for write buffer"
+ },
+ "26": {
+ "desc": "No buffer error; Buffer manager parity error"
+ },
+ "27": {
+ "desc": "A fail response set as checkstop occurred for chana"
+ },
+ "28": {
+ "desc": "A fail response set as checkstop occurred for chanb"
+ },
+ "29": {
+ "desc": "A fail response set as recoverable occurred for chana"
+ },
+ "30": {
+ "desc": "A fail response set as recoverable occurred for chanb"
+ },
+ "31": {
+ "desc": "A lol drop set as checkstop occurred for chana"
+ },
+ "32": {
+ "desc": "A lol drop set as checkstop occurred for chanb"
+ },
+ "33": {
+ "desc": "A lol drop set as recoverable occurred for chana"
+ },
+ "34": {
+ "desc": "A lol drop set as recoverable occurred for chanb"
+ },
+ "35": {
+ "desc": "flit data pariry error from dl for chana"
+ },
+ "36": {
+ "desc": "flit data pariry error from dl for chanb"
+ },
+ "37": {
+ "desc": "internal fifo parity error for chana"
+ },
+ "38": {
+ "desc": "internal fifo parity error for chanb"
+ },
+ "39": {
+ "desc": "Unexpected read or write response received, chana"
+ },
+ "40": {
+ "desc": "Unexpected read or write response received, chanb"
+ },
+ "41": {
+ "desc": "Bad data set for data that is not valid chana"
+ },
+ "42": {
+ "desc": "Bad data set for data that is not valid chanb"
+ },
+ "43": {
+ "desc": "Memory read data returned in template 0, chana"
+ },
+ "44": {
+ "desc": "Memory read data returned in template 0, chanb"
+ },
+ "45": {
+ "desc": "Recieved mmio response while in LOL mode chana"
+ },
+ "46": {
+ "desc": "Recieved mmio response while in LOL mode chanb"
+ },
+ "47": {
+ "desc": "valid bad data or SUE received channel a"
+ },
+ "48": {
+ "desc": "Valid bad data or SUE received chanb"
+ },
+ "49": {
+ "desc": "ChanA excessive data error"
+ },
+ "50": {
+ "desc": "ChanB excessive data error"
+ },
+ "51": {
+ "desc": "Commit state where commit data is not marked as valid"
+ },
+ "52": {
+ "desc": "Commit state where commit data is not marked as valid"
+ },
+ "53": {
+ "desc": "A fifo in the ustl chana overflowed"
+ },
+ "54": {
+ "desc": "A fifo in the ustl chanb overflowed"
+ },
+ "55": {
+ "desc": "Invalid command decoded in USTL FF subchannel A"
+ },
+ "56": {
+ "desc": "Invalid command decoded in USTL FF subchannel B"
+ },
+ "57": {
+ "desc": "Fatal register parity error"
+ },
+ "58": {
+ "desc": "recov register parity error"
+ },
+ "59": {
+ "desc": "ChanA response invalid(dlength and/or dpart received)"
+ },
+ "60": {
+ "desc": "ChanB response invalid(dlength and/or dpart received)"
+ },
+ "61": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_USTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_mcd_fir.json b/chip_data/p10_10/node_mcd_fir.json
new file mode 100644
index 0000000..cedbe4d
--- /dev/null
+++ b/chip_data/p10_10/node_mcd_fir.json
@@ -0,0 +1,169 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MCD_FIR": {
+ "instances": {
+ "0": "0x03010800"
+ }
+ },
+ "MCD_FIR_MASK": {
+ "instances": {
+ "0": "0x03010803"
+ }
+ },
+ "MCD_FIR_ACT0": {
+ "instances": {
+ "0": "0x03010806"
+ }
+ },
+ "MCD_FIR_ACT1": {
+ "instances": {
+ "0": "0x03010807"
+ }
+ },
+ "MCD_FIR_WOF": {
+ "instances": {
+ "0": "0x03010808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MCD_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "MCD array ECC correctable error"
+ },
+ "1": {
+ "desc": "MCD array ECC uncorrectable error"
+ },
+ "2": {
+ "desc": "MCD PowerBus address parity error"
+ },
+ "3": {
+ "desc": "MCD invalid state error"
+ },
+ "4": {
+ "desc": "Hang poll timer expired on cl_probe"
+ },
+ "5": {
+ "desc": "PowerBus address error cresp received"
+ },
+ "6": {
+ "desc": "MCD received a unsolicited CRESP"
+ },
+ "7": {
+ "desc": "MCD powerbus ttag parity error"
+ },
+ "8": {
+ "desc": "MCD scom register update error"
+ },
+ "9": {
+ "desc": "MCD received a ack_dead_cresp"
+ },
+ "10": {
+ "desc": "MCD configuration register had a parity error"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_n0_local_fir.json b/chip_data/p10_10/node_n0_local_fir.json
new file mode 100644
index 0000000..679074f
--- /dev/null
+++ b/chip_data/p10_10/node_n0_local_fir.json
@@ -0,0 +1,427 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "N0_LOCAL_FIR": {
+ "instances": {
+ "0": "0x02040100"
+ }
+ },
+ "N0_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x02040103"
+ }
+ },
+ "N0_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x02040106"
+ }
+ },
+ "N0_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x02040107"
+ }
+ },
+ "N0_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x02040109"
+ }
+ },
+ "N0_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x02040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "N0_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_n1_local_fir.json b/chip_data/p10_10/node_n1_local_fir.json
new file mode 100644
index 0000000..f9d5310
--- /dev/null
+++ b/chip_data/p10_10/node_n1_local_fir.json
@@ -0,0 +1,427 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "N1_LOCAL_FIR": {
+ "instances": {
+ "0": "0x03040100"
+ }
+ },
+ "N1_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x03040103"
+ }
+ },
+ "N1_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x03040106"
+ }
+ },
+ "N1_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x03040107"
+ }
+ },
+ "N1_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x03040109"
+ }
+ },
+ "N1_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x03040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "N1_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "Firmware signaled power bus quiesce failed"
+ },
+ "57": {
+ "desc": "Firmware signaled power bus system quiesce failed"
+ },
+ "58": {
+ "desc": "Firmware signaled deadman timer tigger occurred"
+ },
+ "59": {
+ "desc": "Fimware signaled power bus chip quiesce failed"
+ },
+ "60": {
+ "desc": "Hypervisor / Hostboot / OPAL initiated Terminate Immediate"
+ },
+ "61": {
+ "desc": "Host detected LPC timeout"
+ },
+ "62": {
+ "desc": "reserved for software use"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_nmmu_cq_fir.json b/chip_data/p10_10/node_nmmu_cq_fir.json
new file mode 100644
index 0000000..1672947
--- /dev/null
+++ b/chip_data/p10_10/node_nmmu_cq_fir.json
@@ -0,0 +1,207 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "NMMU_CQ_FIR": {
+ "instances": {
+ "0": "0x02010C00",
+ "1": "0x03010C00"
+ }
+ },
+ "NMMU_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02010C03",
+ "1": "0x03010C03"
+ }
+ },
+ "NMMU_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010C06",
+ "1": "0x03010C06"
+ }
+ },
+ "NMMU_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010C07",
+ "1": "0x03010C07"
+ }
+ },
+ "NMMU_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02010C08",
+ "1": "0x03010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NMMU_CQ_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PBI internal parity error"
+ },
+ "1": {
+ "desc": "PowerBus command hang error"
+ },
+ "2": {
+ "desc": "PowerBus read address error"
+ },
+ "3": {
+ "desc": "PowerBus write address error"
+ },
+ "4": {
+ "desc": "PowerBus miscellaneous error"
+ },
+ "5": {
+ "desc": "Reserved"
+ },
+ "6": {
+ "desc": "PowerBus Xlate UE error"
+ },
+ "7": {
+ "desc": "PowerBus Xlate SUE error"
+ },
+ "8": {
+ "desc": "PowerBus CE error"
+ },
+ "9": {
+ "desc": "PowerBus UE error"
+ },
+ "10": {
+ "desc": "PowerBus SUE error"
+ },
+ "11": {
+ "desc": "Inbound LCO_ARRAY CE error"
+ },
+ "12": {
+ "desc": "Inbound LCO_ARRAY UE error"
+ },
+ "13": {
+ "desc": "Inbound LCO_ARRAY SUE error"
+ },
+ "14": {
+ "desc": "Inbound array CE error"
+ },
+ "15": {
+ "desc": "Inbound array UE error"
+ },
+ "16": {
+ "desc": "internal state error"
+ },
+ "17": {
+ "desc": "ACK_DEAD cresp received by read command"
+ },
+ "18": {
+ "desc": "ACK_DEAD cresp received by write command"
+ },
+ "19": {
+ "desc": "Link check aborted while waiting on data"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NMMU_CQ_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_nmmu_fir.json b/chip_data/p10_10/node_nmmu_fir.json
new file mode 100644
index 0000000..1523cd3
--- /dev/null
+++ b/chip_data/p10_10/node_nmmu_fir.json
@@ -0,0 +1,276 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "NMMU_FIR": {
+ "instances": {
+ "0": "0x02010C40",
+ "1": "0x03010C40"
+ }
+ },
+ "NMMU_FIR_MASK": {
+ "instances": {
+ "0": "0x02010C43",
+ "1": "0x03010C43"
+ }
+ },
+ "NMMU_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010C46",
+ "1": "0x03010C46"
+ }
+ },
+ "NMMU_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010C47",
+ "1": "0x03010C47"
+ }
+ },
+ "NMMU_FIR_WOF": {
+ "instances": {
+ "0": "0x02010C48",
+ "1": "0x03010C48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NMMU_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Fabric DIn xlat array CE error detected"
+ },
+ "1": {
+ "desc": "Fabric DIn xlat array UE error detected"
+ },
+ "2": {
+ "desc": "Fabric DIn xlat array SUE error detected"
+ },
+ "3": {
+ "desc": "Fabric mst rd array CE error detected"
+ },
+ "4": {
+ "desc": "Fabric mst rd array UE error detected"
+ },
+ "5": {
+ "desc": "Fabric mst rd array SUE error detected"
+ },
+ "6": {
+ "desc": "Fabric xlat protocol error detected"
+ },
+ "7": {
+ "desc": "Fabric xlat op timeout detected"
+ },
+ "8": {
+ "desc": "SLB directory parity error detected"
+ },
+ "9": {
+ "desc": "SLB cache parity error detected"
+ },
+ "10": {
+ "desc": "SLB lru parity error detected"
+ },
+ "11": {
+ "desc": "SLB multi-hit error detected"
+ },
+ "12": {
+ "desc": "TLB directory parity error detected"
+ },
+ "13": {
+ "desc": "TLB cache parity error detected"
+ },
+ "14": {
+ "desc": "TLB lru parity error detected"
+ },
+ "15": {
+ "desc": "TLB multi-hit error detected"
+ },
+ "16": {
+ "desc": "Segment fault detected"
+ },
+ "17": {
+ "desc": "Page fault detected due to no matching pte"
+ },
+ "18": {
+ "desc": "Page fault detected due to basic prot chk fail"
+ },
+ "19": {
+ "desc": "Page fault detected due to virt prot chk fail"
+ },
+ "20": {
+ "desc": "Page fault detected due to seid mismatch"
+ },
+ "21": {
+ "desc": "Address error cresp detected by twsm for read"
+ },
+ "22": {
+ "desc": "PTE update fail due to armwf mismatch"
+ },
+ "23": {
+ "desc": "Address error cresp detected by twsm for write"
+ },
+ "24": {
+ "desc": "Unsupported radix cfg for guest-side"
+ },
+ "25": {
+ "desc": "Unsupported radix cfg for host-side"
+ },
+ "26": {
+ "desc": "Invalid wimg setting detected"
+ },
+ "27": {
+ "desc": "Invalid radix quad access detected"
+ },
+ "28": {
+ "desc": "Unexpected access to foreign address space"
+ },
+ "29": {
+ "desc": "Prefetch abort/fail detected"
+ },
+ "30": {
+ "desc": "Context cache array parity error detected"
+ },
+ "31": {
+ "desc": "Radix pwc array parity error detected"
+ },
+ "32": {
+ "desc": "Tablewalk sm control error detected"
+ },
+ "33": {
+ "desc": "Castout sm control error detected"
+ },
+ "34": {
+ "desc": "Check-in sm control error detected"
+ },
+ "35": {
+ "desc": "Invalidate sm control error detected"
+ },
+ "36": {
+ "desc": "Tablewalk sm timeout error detected"
+ },
+ "37": {
+ "desc": "Castout sm timeout error detected"
+ },
+ "38": {
+ "desc": "Check-in sm timeout error detected"
+ },
+ "39": {
+ "desc": "Invalidate sm timeout error detected"
+ },
+ "40": {
+ "desc": "NX local checkstop error detected"
+ },
+ "41": {
+ "desc": "fbc snoop invalidate filter parity error"
+ },
+ "42": {
+ "desc": "fabric purge threshold exceeded"
+ },
+ "43": {
+ "desc": "NPU local checkstop error detected"
+ },
+ "44": {
+ "desc": "FBC local checkstop error detected"
+ },
+ "45": {
+ "desc": "FBC local checkstop error detected"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_nx_cq_fir.json b/chip_data/p10_10/node_nx_cq_fir.json
new file mode 100644
index 0000000..e591590
--- /dev/null
+++ b/chip_data/p10_10/node_nx_cq_fir.json
@@ -0,0 +1,267 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "NX_CQ_FIR": {
+ "instances": {
+ "0": "0x02011080"
+ }
+ },
+ "NX_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02011083"
+ }
+ },
+ "NX_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011086"
+ }
+ },
+ "NX_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011087"
+ }
+ },
+ "NX_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02011088"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NX_CQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PBI internal parity error"
+ },
+ "1": {
+ "desc": "PowerBus CE error"
+ },
+ "2": {
+ "desc": "PowerBus UE error"
+ },
+ "3": {
+ "desc": "PowerBus SUE error"
+ },
+ "4": {
+ "desc": "Inbound array CE error"
+ },
+ "5": {
+ "desc": "Inbound array UE error"
+ },
+ "6": {
+ "desc": "Paste request rejected"
+ },
+ "7": {
+ "desc": "PowerBus command hang error"
+ },
+ "8": {
+ "desc": "PowerBus read address error"
+ },
+ "9": {
+ "desc": "PowerBus write address error"
+ },
+ "10": {
+ "desc": "PowerBus miscellaneous error"
+ },
+ "11": {
+ "desc": "MMIO BAR parity error"
+ },
+ "12": {
+ "desc": "UMAC detected SUE on WC Interrupt"
+ },
+ "13": {
+ "desc": "ACK_DEAD cresp received by read command"
+ },
+ "14": {
+ "desc": "ACK_DEAD cresp received by write command"
+ },
+ "15": {
+ "desc": "Reserved. Used to be PowerBus Link Abort in P9"
+ },
+ "16": {
+ "desc": "Hang poll time expired on internal transfer"
+ },
+ "17": {
+ "desc": "Parity error on ERAT arrays"
+ },
+ "18": {
+ "desc": "Correctable error on ERAT arrays"
+ },
+ "19": {
+ "desc": "Uncorrectable error on ERAT arrays"
+ },
+ "20": {
+ "desc": "Special uncorrectable error on ERAT arrays"
+ },
+ "21": {
+ "desc": "Hang on checkin/checkout request to NMMU"
+ },
+ "22": {
+ "desc": "ERAT control logic error"
+ },
+ "23": {
+ "desc": "Uncorrectable error on the Powerbus data for xlate"
+ },
+ "24": {
+ "desc": "Special uncorrectable error on the Powerbus data for xlate"
+ },
+ "25": {
+ "desc": "ACK_DEAD cresp received by UMAC read command"
+ },
+ "26": {
+ "desc": "Link check aborted while waiting on UMAC data"
+ },
+ "27": {
+ "desc": "Uncorrectable error on CRB QW0/4"
+ },
+ "28": {
+ "desc": "Special uncorrectable error on CRB QW0/4"
+ },
+ "29": {
+ "desc": "UMAC has detected a control logic error"
+ },
+ "30": {
+ "desc": "Other SCOM satellite parity error"
+ },
+ "31": {
+ "desc": "SCOM write to RNG when not allowed"
+ },
+ "32": {
+ "desc": "A first noise source in the RNG has failed"
+ },
+ "33": {
+ "desc": "A second noise source in the RNG has failed"
+ },
+ "34": {
+ "desc": "RNG has detected a control logic error"
+ },
+ "35": {
+ "desc": "NMMU has signaled local checkstop"
+ },
+ "36": {
+ "desc": "VAS has signaled local checkstop"
+ },
+ "37": {
+ "desc": "PBCQ has detected a control logic error"
+ },
+ "38": {
+ "desc": "PBCQ has detected a failed link on an interrupt"
+ },
+ "39": {
+ "desc": "UMAC has detected an SUE on interrupt address"
+ },
+ "40": {
+ "desc": "SMF error"
+ },
+ "41": {
+ "desc": "Topology index error detected in NX"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NX_CQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_nx_dma_eng_fir.json b/chip_data/p10_10/node_nx_dma_eng_fir.json
new file mode 100644
index 0000000..80b0e35
--- /dev/null
+++ b/chip_data/p10_10/node_nx_dma_eng_fir.json
@@ -0,0 +1,285 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "NX_DMA_ENG_FIR": {
+ "instances": {
+ "0": "0x02011100"
+ }
+ },
+ "NX_DMA_ENG_FIR_MASK": {
+ "instances": {
+ "0": "0x02011103"
+ }
+ },
+ "NX_DMA_ENG_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011106"
+ }
+ },
+ "NX_DMA_ENG_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011107"
+ }
+ },
+ "NX_DMA_ENG_FIR_WOF": {
+ "instances": {
+ "0": "0x02011108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NX_DMA_ENG_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "DMA hang timer expired"
+ },
+ "1": {
+ "desc": "SHM invalid state"
+ },
+ "2": {
+ "desc": "reserved"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "Channel 0 842 engine ECC CE"
+ },
+ "5": {
+ "desc": "Channel 0 842 engine ECC UE"
+ },
+ "6": {
+ "desc": "Channel 1 842 engine ECC CE"
+ },
+ "7": {
+ "desc": "Channel 1 842 engine ECC UE"
+ },
+ "8": {
+ "desc": "DMA Non-zero CSB CC detected"
+ },
+ "9": {
+ "desc": "DMA array ECC CE"
+ },
+ "10": {
+ "desc": "DMA outbound write/inbound read ECC CE"
+ },
+ "11": {
+ "desc": "Channel 4 GZIP ECC CE"
+ },
+ "12": {
+ "desc": "Channel 4 GZIP ECC UE"
+ },
+ "13": {
+ "desc": "Channel 4 GZIP ECC PE"
+ },
+ "14": {
+ "desc": "Error from other SCOM satellites"
+ },
+ "15": {
+ "desc": "DMA invalid state error (unrecoverable)"
+ },
+ "16": {
+ "desc": "DMA invalid state error (unrecoverable)"
+ },
+ "17": {
+ "desc": "DMA array ECC UE"
+ },
+ "18": {
+ "desc": "DMA outbound write/inbound read ECC UE"
+ },
+ "19": {
+ "desc": "DMA inbound read error"
+ },
+ "20": {
+ "desc": "Channel 0 842 invalid state error"
+ },
+ "21": {
+ "desc": "Channel 1 842 invalid state error"
+ },
+ "22": {
+ "desc": "Channel 2 SYM invalid state error"
+ },
+ "23": {
+ "desc": "Channel 3 SYM invalid state error"
+ },
+ "24": {
+ "desc": "Channel 4 GZIP invalid state error"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "reserved"
+ },
+ "27": {
+ "desc": "reserved"
+ },
+ "28": {
+ "desc": "reserved"
+ },
+ "29": {
+ "desc": "reserved"
+ },
+ "30": {
+ "desc": "reserved"
+ },
+ "31": {
+ "desc": "UE error on CRB QW0 or QW4"
+ },
+ "32": {
+ "desc": "SUE error on CRB QW0 or QW4"
+ },
+ "33": {
+ "desc": "SUE error on something other than CRB QW0 or QW4"
+ },
+ "34": {
+ "desc": "Channel 0 842 watchdog timer expired"
+ },
+ "35": {
+ "desc": "Channel 1 842 watchdog timer expired"
+ },
+ "36": {
+ "desc": "Channel 2 SYM watchdog timer expired"
+ },
+ "37": {
+ "desc": "Channel 3 SYM watchdog timer expired"
+ },
+ "38": {
+ "desc": "Hypervisor local checkstop"
+ },
+ "39": {
+ "desc": "Channel 4 Gzip watchdog timer expired"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "reserved"
+ },
+ "43": {
+ "desc": "reserved"
+ },
+ "44": {
+ "desc": "reserved"
+ },
+ "45": {
+ "desc": "reserved"
+ },
+ "46": {
+ "desc": "reserved"
+ },
+ "47": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NX_DMA_ENG_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_occ_fir.json b/chip_data/p10_10/node_occ_fir.json
new file mode 100644
index 0000000..9d6367d
--- /dev/null
+++ b/chip_data/p10_10/node_occ_fir.json
@@ -0,0 +1,294 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "OCC_FIR": {
+ "instances": {
+ "0": "0x01010800"
+ }
+ },
+ "OCC_FIR_MASK": {
+ "instances": {
+ "0": "0x01010803"
+ }
+ },
+ "OCC_FIR_ACT0": {
+ "instances": {
+ "0": "0x01010806"
+ }
+ },
+ "OCC_FIR_ACT1": {
+ "instances": {
+ "0": "0x01010807"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OCC_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OCC_FW0"
+ },
+ "1": {
+ "desc": "OCC_FW1"
+ },
+ "2": {
+ "desc": "OCC_QME_ERROR_NOTIFY"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "OCC Heartbeat Error"
+ },
+ "5": {
+ "desc": "GPE0 asserted a watchdog timeout condition"
+ },
+ "6": {
+ "desc": "GPE1 asserted a watchdog timeout condition"
+ },
+ "7": {
+ "desc": "GPE2 asserted a watchdog timeout condition"
+ },
+ "8": {
+ "desc": "GPE3 asserted a watchdog timeout condition"
+ },
+ "9": {
+ "desc": "GPE0 asserted an error condition that caused it to halt."
+ },
+ "10": {
+ "desc": "GPE1 asserted an error condition that caused it to halt."
+ },
+ "11": {
+ "desc": "GPE2 asserted an error condition that caused it to halt."
+ },
+ "12": {
+ "desc": "GPE3 asserted an error condition that caused it to halt."
+ },
+ "13": {
+ "desc": "OCB Error to PM Hcode for PM Complex Restart"
+ },
+ "14": {
+ "desc": "SRAM UE to PM Hcode for PM Complex Restart"
+ },
+ "15": {
+ "desc": "SRAM CE"
+ },
+ "16": {
+ "desc": "GPE0 asserted a halt condition"
+ },
+ "17": {
+ "desc": "GPE1 asserted a halt condition"
+ },
+ "18": {
+ "desc": "GPE2 asserted a halt condition"
+ },
+ "19": {
+ "desc": "GPE3 asserted a halt condition"
+ },
+ "20": {
+ "desc": "GPE0 attempted to write outside the region defined in GPESWPR"
+ },
+ "21": {
+ "desc": "GPE1 attempted to write outside the region defined in GPESWPR"
+ },
+ "22": {
+ "desc": "GPE2 attempted to write outside the region defined in GPESWPR"
+ },
+ "23": {
+ "desc": "GPE3 attempted to write outside the region defined in GPESWPR"
+ },
+ "24": {
+ "desc": "Safe Mode for debug use"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "EXTERNAL_TRAP"
+ },
+ "27": {
+ "desc": "PPC405 Core Reset Output asserted (OCC firmware)"
+ },
+ "28": {
+ "desc": "PPC405 Chip Reset Output asserted (OCC firmware)"
+ },
+ "29": {
+ "desc": "PPC405 System Reset Output asserted (OCC firmware)"
+ },
+ "30": {
+ "desc": "PPC405 Wait State asserted (OCC firmware)"
+ },
+ "31": {
+ "desc": "PPC405 Stop Ack output asserted"
+ },
+ "32": {
+ "desc": "OCB Direct Bridge Error"
+ },
+ "33": {
+ "desc": "OCB PIB Address Parity Error"
+ },
+ "34": {
+ "desc": "Indirect Channel Error"
+ },
+ "35": {
+ "desc": "Parity error detected on OPIT interrupt bus"
+ },
+ "36": {
+ "desc": "OPIT interrupt state machine error occurred"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "JTAG accelerator error"
+ },
+ "43": {
+ "desc": "Any OCI Slave error occurreds"
+ },
+ "44": {
+ "desc": "PPC405 cache UE"
+ },
+ "45": {
+ "desc": "PPC405 cache CE"
+ },
+ "46": {
+ "desc": "PPC405 Machine Check"
+ },
+ "47": {
+ "desc": "SRAM spare direct error Summary"
+ },
+ "48": {
+ "desc": "Read, write, or parity error in the SRAM tank controller"
+ },
+ "49": {
+ "desc": "reserved"
+ },
+ "50": {
+ "desc": "reserved"
+ },
+ "51": {
+ "desc": "OCI slave error for GPE0"
+ },
+ "52": {
+ "desc": "OCI slave error for GPE1"
+ },
+ "53": {
+ "desc": "OCI slave error for GPE2"
+ },
+ "54": {
+ "desc": "OCI slave error for GPE3"
+ },
+ "55": {
+ "desc": "PPC405 ICU timeout on OCI request"
+ },
+ "56": {
+ "desc": "PPC405 DCU timeout on OCI request"
+ },
+ "57": {
+ "desc": "OCC fault occurred (to achieve safe mode)"
+ },
+ "58": {
+ "desc": "Read by HYP as part of the communication of a Power Management fault"
+ },
+ "59": {
+ "desc": "reserved"
+ },
+ "60": {
+ "desc": "reserved"
+ },
+ "61": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "OCC_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_dl_fir.json b/chip_data/p10_10/node_pau_dl_fir.json
new file mode 100644
index 0000000..e52e01d
--- /dev/null
+++ b/chip_data/p10_10/node_pau_dl_fir.json
@@ -0,0 +1,257 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_DL_FIR": {
+ "instances": {
+ "0": "0x10012C40",
+ "1": "0x11012C40",
+ "2": "0x12012C40",
+ "3": "0x13012C40"
+ }
+ },
+ "PAU_DL_FIR_MASK": {
+ "instances": {
+ "0": "0x10012C43",
+ "1": "0x11012C43",
+ "2": "0x12012C43",
+ "3": "0x13012C43"
+ }
+ },
+ "PAU_DL_FIR_ACT0": {
+ "instances": {
+ "0": "0x10012C46",
+ "1": "0x11012C46",
+ "2": "0x12012C46",
+ "3": "0x13012C46"
+ }
+ },
+ "PAU_DL_FIR_ACT1": {
+ "instances": {
+ "0": "0x10012C47",
+ "1": "0x11012C47",
+ "2": "0x12012C47",
+ "3": "0x13012C47"
+ }
+ },
+ "PAU_DL_FIR_WOF": {
+ "instances": {
+ "0": "0x10012C48",
+ "1": "0x11012C48",
+ "2": "0x12012C48",
+ "3": "0x13012C48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_DL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_DL_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "1": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "2": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "3": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "4": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "5": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "6": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "7": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "8": {
+ "desc": "FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred."
+ },
+ "9": {
+ "desc": "FIR Register - A PPE internal error has occurred."
+ },
+ "10": {
+ "desc": "FIR Register - A PPE external error has occurred."
+ },
+ "11": {
+ "desc": "FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred."
+ },
+ "12": {
+ "desc": "FIR Register - A PPE Halt due to Debug has occurred."
+ },
+ "13": {
+ "desc": "FIR Register - PPE Halted."
+ },
+ "14": {
+ "desc": "FIR Register - A PPE Watchdog Timeout has occurred."
+ },
+ "15": {
+ "desc": "FIR Register - A PPE Array Scrub was missed."
+ },
+ "16": {
+ "desc": "FIR Register - A PPE Array uncorrectable error has occurred."
+ },
+ "17": {
+ "desc": "FIR Register - A PPE Array correctable error has occurred."
+ },
+ "18": {
+ "desc": "FIR Register - A PPE Code Recal Abort has occurred."
+ },
+ "19": {
+ "desc": "FIR Register - A PPE Code Fatal Error has occurred."
+ },
+ "20": {
+ "desc": "FIR Register - A PPE Code Warning has occurred."
+ },
+ "21": {
+ "desc": "FIR Register - A PPE Code DFT Error has occurred."
+ },
+ "22": {
+ "desc": "FIR Register - A PPE Code Recal Not Run has occurred."
+ },
+ "23": {
+ "desc": "FIR Register - A PPE Code Thread Locked has occurred."
+ },
+ "24": {
+ "desc": "FIR Register - A PPE Code FIR 6 has occurred."
+ },
+ "25": {
+ "desc": "FIR Register - A PPE Code FIR 7 has occurred."
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_fir_0.json b/chip_data/p10_10/node_pau_fir_0.json
new file mode 100644
index 0000000..483f561
--- /dev/null
+++ b/chip_data/p10_10/node_pau_fir_0.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_FIR_0": {
+ "instances": {
+ "0": "0x10010C00",
+ "3": "0x11010C00",
+ "4": "0x12010C00",
+ "5": "0x12011400",
+ "6": "0x13010C00",
+ "7": "0x13011400"
+ }
+ },
+ "PAU_FIR_0_MASK": {
+ "instances": {
+ "0": "0x10010C03",
+ "3": "0x11010C03",
+ "4": "0x12010C03",
+ "5": "0x12011403",
+ "6": "0x13010C03",
+ "7": "0x13011403"
+ }
+ },
+ "PAU_FIR_0_ACT0": {
+ "instances": {
+ "0": "0x10010C06",
+ "3": "0x11010C06",
+ "4": "0x12010C06",
+ "5": "0x12011406",
+ "6": "0x13010C06",
+ "7": "0x13011406"
+ }
+ },
+ "PAU_FIR_0_ACT1": {
+ "instances": {
+ "0": "0x10010C07",
+ "3": "0x11010C07",
+ "4": "0x12010C07",
+ "5": "0x12011407",
+ "6": "0x13010C07",
+ "7": "0x13011407"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_0": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NTL array CE"
+ },
+ "1": {
+ "desc": "NTL header array UE"
+ },
+ "2": {
+ "desc": "NTL data array UE"
+ },
+ "3": {
+ "desc": "NTL NVLInk Control/Header/AE Parity error"
+ },
+ "4": {
+ "desc": "NTL NVLink Data Parity error"
+ },
+ "5": {
+ "desc": "NTL NVLink Malformed Packet"
+ },
+ "6": {
+ "desc": "NTL NVLink Unsupported Packet"
+ },
+ "7": {
+ "desc": "NTL NVLink Config errors"
+ },
+ "8": {
+ "desc": "NTL NVLink CRC errors or LMD=Stomp"
+ },
+ "9": {
+ "desc": "NTL PRI errors"
+ },
+ "10": {
+ "desc": "NTL logic error"
+ },
+ "11": {
+ "desc": "NTL LMD=Data Poison"
+ },
+ "12": {
+ "desc": "NTL data array SUE"
+ },
+ "13": {
+ "desc": "CQ CTL/SM ASBE Array single-bit correctable error"
+ },
+ "14": {
+ "desc": "CQ CTL/SM PBR PowerBus Recoverable"
+ },
+ "15": {
+ "desc": "CQ CTL/SM REG Register ring error"
+ },
+ "16": {
+ "desc": "CQ CTL/SM DUE Data Uncorrectable error for MMIO store data"
+ },
+ "17": {
+ "desc": "CQ CTL/SM UT=1 to frozen PE"
+ },
+ "18": {
+ "desc": "CQ CTL/SM NCF NVLink configuration error"
+ },
+ "19": {
+ "desc": "CQ CTL/SM NVF NVLink fatal"
+ },
+ "20": {
+ "desc": "CQ CTL/SM OCR OpenCAPI Recoverable, Command failed, and brick not fenced."
+ },
+ "21": {
+ "desc": "CQ CTL/SM AUE Array uncorrectable error"
+ },
+ "22": {
+ "desc": "CQ CTL/SM PBP PowerBus parity error"
+ },
+ "23": {
+ "desc": "CQ CTL/SM PBF PowerBus Fatal"
+ },
+ "24": {
+ "desc": "CQ CTL/SM PBC PowerBus configuration error"
+ },
+ "25": {
+ "desc": "CQ CTL/SM FWD Forward-Progress"
+ },
+ "26": {
+ "desc": "CQ CTL/SM NLG PAU Logic error"
+ },
+ "27": {
+ "desc": "Cresp=Addr_Error received for a load command"
+ },
+ "28": {
+ "desc": "Cresp=Addr_Error received for a store command"
+ },
+ "29": {
+ "desc": "CQ DAT ECC UE on data/BE arrays"
+ },
+ "30": {
+ "desc": "CQ DAT ECC CE on data/BE arrays"
+ },
+ "31": {
+ "desc": "CQ DAT parity error on data/BE latches"
+ },
+ "32": {
+ "desc": "CQ DAT parity errors on configuration registers"
+ },
+ "33": {
+ "desc": "CQ DAT parity errors on received PowerBus rtag"
+ },
+ "34": {
+ "desc": "CQ DAT parity errors on internal state latches"
+ },
+ "35": {
+ "desc": "CQ DAT logic error"
+ },
+ "36": {
+ "desc": "CQ DAT ECC SUE on data/BE arrays"
+ },
+ "37": {
+ "desc": "CQ DAT ECC SUE on PB receive data"
+ },
+ "38": {
+ "desc": "CQ DAT Reserved, macro bit 9"
+ },
+ "39": {
+ "desc": "CQ DAT Reserved, macro bit 10"
+ },
+ "40": {
+ "desc": "XTS internal logic error"
+ },
+ "41": {
+ "desc": "XTS correctable errors in XTS internal SRAM"
+ },
+ "42": {
+ "desc": "XTS uncorrectable errors in XTS internal SRAM"
+ },
+ "43": {
+ "desc": "XTS correctable error on incoming stack transactions"
+ },
+ "44": {
+ "desc": "XTS uncorrectable/protocol errors on incoming stack transaction"
+ },
+ "45": {
+ "desc": "XTS protocol errors on incoming PBUS transaction"
+ },
+ "46": {
+ "desc": "XTS Translate Request Fail"
+ },
+ "47": {
+ "desc": "XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command."
+ },
+ "48": {
+ "desc": "XTS Reserved, macro bit 8"
+ },
+ "49": {
+ "desc": "XTS Reserved, macro bit 9"
+ },
+ "50": {
+ "desc": "XTS Reserved, macro bit 10"
+ },
+ "51": {
+ "desc": "XTS Reserved, macro bit 11"
+ },
+ "52": {
+ "desc": "XTS Reserved, macro bit 12"
+ },
+ "53": {
+ "desc": "XTS Reserved, macro bit 13"
+ },
+ "54": {
+ "desc": "XTS Reserved, macro bit 14"
+ },
+ "55": {
+ "desc": "XTS Reserved, macro bit 15"
+ },
+ "56": {
+ "desc": "XTS Reserved, macro bit 16"
+ },
+ "57": {
+ "desc": "XTS Reserved, macro bit 17"
+ },
+ "58": {
+ "desc": "XTS Reserved, macro bit 18"
+ },
+ "59": {
+ "desc": "AME Reserved, interrupt"
+ },
+ "60": {
+ "desc": "AME data ECC UE"
+ },
+ "61": {
+ "desc": "AME data SUE"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_fir_1.json b/chip_data/p10_10/node_pau_fir_1.json
new file mode 100644
index 0000000..a2c5778
--- /dev/null
+++ b/chip_data/p10_10/node_pau_fir_1.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_FIR_1": {
+ "instances": {
+ "0": "0x10010C40",
+ "3": "0x11010C40",
+ "4": "0x12010C40",
+ "5": "0x12011440",
+ "6": "0x13010C40",
+ "7": "0x13011440"
+ }
+ },
+ "PAU_FIR_1_MASK": {
+ "instances": {
+ "0": "0x10010C43",
+ "3": "0x11010C43",
+ "4": "0x12010C43",
+ "5": "0x12011443",
+ "6": "0x13010C43",
+ "7": "0x13011443"
+ }
+ },
+ "PAU_FIR_1_ACT0": {
+ "instances": {
+ "0": "0x10010C46",
+ "3": "0x11010C46",
+ "4": "0x12010C46",
+ "5": "0x12011446",
+ "6": "0x13010C46",
+ "7": "0x13011446"
+ }
+ },
+ "PAU_FIR_1_ACT1": {
+ "instances": {
+ "0": "0x10010C47",
+ "3": "0x11010C47",
+ "4": "0x12010C47",
+ "5": "0x12011447",
+ "6": "0x13010C47",
+ "7": "0x13011447"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_1": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NDL Brick0 stall"
+ },
+ "1": {
+ "desc": "NDL Brick0 nostall"
+ },
+ "2": {
+ "desc": "NDL Brick1 stall"
+ },
+ "3": {
+ "desc": "NDL Brick1 nostall"
+ },
+ "4": {
+ "desc": "NDL Brick2 stall"
+ },
+ "5": {
+ "desc": "NDL Brick2 nostall"
+ },
+ "6": {
+ "desc": "NDL Brick3 stall"
+ },
+ "7": {
+ "desc": "NDL Brick3 nostall"
+ },
+ "8": {
+ "desc": "NDL Brick4 stall"
+ },
+ "9": {
+ "desc": "NDL Brick4 nostall"
+ },
+ "10": {
+ "desc": "NDL Brick5 stall"
+ },
+ "11": {
+ "desc": "NDL Brick5 nostall"
+ },
+ "12": {
+ "desc": "MISC Register ring error"
+ },
+ "13": {
+ "desc": "MISC Parity error from interrupt base real address register"
+ },
+ "14": {
+ "desc": "MISC Parity error on Indirect SCOM Address register"
+ },
+ "15": {
+ "desc": "MISC Parity error on MISC Control register"
+ },
+ "16": {
+ "desc": "FIR1 Reserved, bit 16"
+ },
+ "17": {
+ "desc": "ATS Invalid TVT entry"
+ },
+ "18": {
+ "desc": "ATS TVT Address range error"
+ },
+ "19": {
+ "desc": "ATS TCE Page access error during TCE cache lookup"
+ },
+ "20": {
+ "desc": "ATS Effective Address hit multiple TCE cache entries"
+ },
+ "21": {
+ "desc": "ATS TCE Page access error during TCE table-walk"
+ },
+ "22": {
+ "desc": "ATS Timeout on TCE tree walk"
+ },
+ "23": {
+ "desc": "ATS Parity error on TCE cache directory array"
+ },
+ "24": {
+ "desc": "ATS Parity error on TCE cache data array"
+ },
+ "25": {
+ "desc": "ATS ECC UE on Effective Address array"
+ },
+ "26": {
+ "desc": "ATS ECC CE on Effective Address array"
+ },
+ "27": {
+ "desc": "ATS ECC UE on TDRmem array"
+ },
+ "28": {
+ "desc": "ATS ECC CE on TDRmem array"
+ },
+ "29": {
+ "desc": "ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk"
+ },
+ "30": {
+ "desc": "ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk"
+ },
+ "31": {
+ "desc": "ATS Parity error on TVT entry"
+ },
+ "32": {
+ "desc": "ATS Parity error on IODA Address Register"
+ },
+ "33": {
+ "desc": "ATS Parity error on ATS Control Register"
+ },
+ "34": {
+ "desc": "ATS Parity error on ATS Timeout Control register"
+ },
+ "35": {
+ "desc": "ATS Invalid IODA Table Address Register Table Select entry"
+ },
+ "36": {
+ "desc": "ATS Reserved, macro bit 19"
+ },
+ "37": {
+ "desc": "kill xlate epoch timeout."
+ },
+ "38": {
+ "desc": "XSL Reserved, macro bit 19."
+ },
+ "39": {
+ "desc": "XSL Reserved, macro bit 20."
+ },
+ "40": {
+ "desc": "XSL Reserved, macro bit 21."
+ },
+ "41": {
+ "desc": "XSL Reserved, macro bit 22."
+ },
+ "42": {
+ "desc": "XSL Reserved, macro bit 23."
+ },
+ "43": {
+ "desc": "XSL Reserved, macro bit 24."
+ },
+ "44": {
+ "desc": "XSL Reserved, macro bit 25."
+ },
+ "45": {
+ "desc": "XSL Reserved, macro bit 26."
+ },
+ "46": {
+ "desc": "XSL Reserved, macro bit 27."
+ },
+ "47": {
+ "desc": "NDL Brick6 stall"
+ },
+ "48": {
+ "desc": "NDL Brick6 nostall"
+ },
+ "49": {
+ "desc": "NDL Brick7 stall"
+ },
+ "50": {
+ "desc": "NDL Brick7 nostall"
+ },
+ "51": {
+ "desc": "NDL Brick8 stall"
+ },
+ "52": {
+ "desc": "NDL Brick8 nostall"
+ },
+ "53": {
+ "desc": "NDL Brick9 stall"
+ },
+ "54": {
+ "desc": "NDL Brick9 nostall"
+ },
+ "55": {
+ "desc": "NDL Brick10 stall"
+ },
+ "56": {
+ "desc": "NDL Brick10 nostall"
+ },
+ "57": {
+ "desc": "NDL Brick11 stall"
+ },
+ "58": {
+ "desc": "NDL Brick11 nostall"
+ },
+ "59": {
+ "desc": "AME ECC CE"
+ },
+ "60": {
+ "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0)"
+ },
+ "61": {
+ "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1)"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_fir_2.json b/chip_data/p10_10/node_pau_fir_2.json
new file mode 100644
index 0000000..35764d6
--- /dev/null
+++ b/chip_data/p10_10/node_pau_fir_2.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_FIR_2": {
+ "instances": {
+ "0": "0x10010C80",
+ "3": "0x11010C80",
+ "4": "0x12010C80",
+ "5": "0x12011480",
+ "6": "0x13010C80",
+ "7": "0x13011480"
+ }
+ },
+ "PAU_FIR_2_MASK": {
+ "instances": {
+ "0": "0x10010C83",
+ "3": "0x11010C83",
+ "4": "0x12010C83",
+ "5": "0x12011483",
+ "6": "0x13010C83",
+ "7": "0x13011483"
+ }
+ },
+ "PAU_FIR_2_ACT0": {
+ "instances": {
+ "0": "0x10010C86",
+ "3": "0x11010C86",
+ "4": "0x12010C86",
+ "5": "0x12011486",
+ "6": "0x13010C86",
+ "7": "0x13011486"
+ }
+ },
+ "PAU_FIR_2_ACT1": {
+ "instances": {
+ "0": "0x10010C87",
+ "3": "0x11010C87",
+ "4": "0x12010C87",
+ "5": "0x12011487",
+ "6": "0x13010C87",
+ "7": "0x13011487"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_2": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OTL Brick2 translation fault"
+ },
+ "1": {
+ "desc": "OTL Brick3 translation fault"
+ },
+ "2": {
+ "desc": "OTL Brick4 translation fault"
+ },
+ "3": {
+ "desc": "OTL Brick5 translation fault"
+ },
+ "4": {
+ "desc": "OTL TL credit counter overflow caused by return_tl_credits"
+ },
+ "5": {
+ "desc": "OTL RX acTag specified in a command is outside the configured specification set"
+ },
+ "6": {
+ "desc": "OTL RX acTag specified in the command points to an invalid entry"
+ },
+ "7": {
+ "desc": "OTL RX reserved opcode used"
+ },
+ "8": {
+ "desc": "OTL RX return_tl_credit command found outside slot0"
+ },
+ "9": {
+ "desc": "OTL RX bad opcode and template combination"
+ },
+ "10": {
+ "desc": "OTL RX unsupported template format"
+ },
+ "11": {
+ "desc": "OTL RX bad template x00 format"
+ },
+ "12": {
+ "desc": "OTL RX control flit overrun"
+ },
+ "13": {
+ "desc": "OTL RX unexpected data flit"
+ },
+ "14": {
+ "desc": "OTL RX DL link down"
+ },
+ "15": {
+ "desc": "OTL RX bad data received on command"
+ },
+ "16": {
+ "desc": "OTL RX bad data received on response"
+ },
+ "17": {
+ "desc": "OTL RX AP response not allowed (CAPPTag not recognized)"
+ },
+ "18": {
+ "desc": "OR of all OTL parity errors"
+ },
+ "19": {
+ "desc": "OR of all OTL ECC CE errors"
+ },
+ "20": {
+ "desc": "OR of all OTL ECC UE errors"
+ },
+ "21": {
+ "desc": "RXO OP Errors"
+ },
+ "22": {
+ "desc": "RXO Internal Errors"
+ },
+ "23": {
+ "desc": "OTL RXI fifo overrun"
+ },
+ "24": {
+ "desc": "OTL RXI control flit data run length invalid"
+ },
+ "25": {
+ "desc": "OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL"
+ },
+ "26": {
+ "desc": "OTL RXI bad data received vc2"
+ },
+ "27": {
+ "desc": "OTL RXI dcp2 fifo overrun"
+ },
+ "28": {
+ "desc": "OTL RXI vc1 fifo overrun"
+ },
+ "29": {
+ "desc": "OTL RXI vc2 fifo overrun"
+ },
+ "30": {
+ "desc": "Opcode data length not supported"
+ },
+ "31": {
+ "desc": "OTL TXI opcode error"
+ },
+ "32": {
+ "desc": "malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2)"
+ },
+ "33": {
+ "desc": "OTL Happi no bar match"
+ },
+ "34": {
+ "desc": "OTL Reserved, macro bit 30"
+ },
+ "35": {
+ "desc": "OTL Reserved, macro bit 31"
+ },
+ "36": {
+ "desc": "MMIO invalidate requested while one is in progress"
+ },
+ "37": {
+ "desc": "Unexpected ITAG returned on itag completion port 0"
+ },
+ "38": {
+ "desc": "Unexpected ITAG returned on itag completion port 1"
+ },
+ "39": {
+ "desc": "Unexpected Read PEE completion"
+ },
+ "40": {
+ "desc": "Unexpected Checkout response"
+ },
+ "41": {
+ "desc": "Translation request while SPAP is invalid"
+ },
+ "42": {
+ "desc": "Read a PEE which was not valid"
+ },
+ "43": {
+ "desc": "Bloom filter protection error"
+ },
+ "44": {
+ "desc": "Translation request to non-valid TA"
+ },
+ "45": {
+ "desc": "TA Translation request to an invalid TA"
+ },
+ "46": {
+ "desc": "correctable array error (SBE)"
+ },
+ "47": {
+ "desc": "uncorrectable array error (UE or parity)"
+ },
+ "48": {
+ "desc": "S/TLBI buffer overflow"
+ },
+ "49": {
+ "desc": "SBE correctable error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "50": {
+ "desc": "UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "51": {
+ "desc": "SUE error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "52": {
+ "desc": "PA mem_hit when bar mode is nonzero"
+ },
+ "53": {
+ "desc": "XSL Reserved, macro bit 17"
+ },
+ "54": {
+ "desc": "OTL Brick0 translation fault"
+ },
+ "55": {
+ "desc": "OTL Brick1 translation fault"
+ },
+ "56": {
+ "desc": "AME ECC UE on control information or state bit errors that are contained within AME and ATL"
+ },
+ "57": {
+ "desc": "AME ECC UE on control information or state bit errors that can affect correctness of external logic such as XSL castout"
+ },
+ "58": {
+ "desc": "AME Logic errors that are contained within AME and ATL"
+ },
+ "59": {
+ "desc": "AME Logic errors that can affect correctness of external logic such as XSL castout"
+ },
+ "60": {
+ "desc": "AME firmware-detected fatal error conditions"
+ },
+ "61": {
+ "desc": "AME Reserved"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_local_fir.json b/chip_data/p10_10/node_pau_local_fir.json
new file mode 100644
index 0000000..6c36778
--- /dev/null
+++ b/chip_data/p10_10/node_pau_local_fir.json
@@ -0,0 +1,445 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_LOCAL_FIR": {
+ "instances": {
+ "0": "0x10040100",
+ "1": "0x11040100",
+ "2": "0x12040100",
+ "3": "0x13040100"
+ }
+ },
+ "PAU_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x10040103",
+ "1": "0x11040103",
+ "2": "0x12040103",
+ "3": "0x13040103"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x10040106",
+ "1": "0x11040106",
+ "2": "0x12040106",
+ "3": "0x13040106"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x10040107",
+ "1": "0x11040107",
+ "2": "0x12040107",
+ "3": "0x13040107"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x10040109",
+ "1": "0x11040109",
+ "2": "0x12040109",
+ "3": "0x13040109"
+ }
+ },
+ "PAU_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x10040108",
+ "1": "0x11040108",
+ "2": "0x12040108",
+ "3": "0x13040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_phy_fir.json b/chip_data/p10_10/node_pau_phy_fir.json
new file mode 100644
index 0000000..ae1a8fb
--- /dev/null
+++ b/chip_data/p10_10/node_pau_phy_fir.json
@@ -0,0 +1,257 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_PHY_FIR": {
+ "instances": {
+ "0": "0x10012C00",
+ "1": "0x11012C00",
+ "2": "0x12012C00",
+ "3": "0x13012C00"
+ }
+ },
+ "PAU_PHY_FIR_MASK": {
+ "instances": {
+ "0": "0x10012C03",
+ "1": "0x11012C03",
+ "2": "0x12012C03",
+ "3": "0x13012C03"
+ }
+ },
+ "PAU_PHY_FIR_ACT0": {
+ "instances": {
+ "0": "0x10012C06",
+ "1": "0x11012C06",
+ "2": "0x12012C06",
+ "3": "0x13012C06"
+ }
+ },
+ "PAU_PHY_FIR_ACT1": {
+ "instances": {
+ "0": "0x10012C07",
+ "1": "0x11012C07",
+ "2": "0x12012C07",
+ "3": "0x13012C07"
+ }
+ },
+ "PAU_PHY_FIR_WOF": {
+ "instances": {
+ "0": "0x10012C08",
+ "1": "0x11012C08",
+ "2": "0x12012C08",
+ "3": "0x13012C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_PHY_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "1": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "2": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "3": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "4": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "5": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "6": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "7": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "8": {
+ "desc": "FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred."
+ },
+ "9": {
+ "desc": "FIR Register - A PPE internal error has occurred."
+ },
+ "10": {
+ "desc": "FIR Register - A PPE external error has occurred."
+ },
+ "11": {
+ "desc": "FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred."
+ },
+ "12": {
+ "desc": "FIR Register - A PPE Halt due to Debug has occurred."
+ },
+ "13": {
+ "desc": "FIR Register - PPE Halted."
+ },
+ "14": {
+ "desc": "FIR Register - A PPE Watchdog Timeout has occurred."
+ },
+ "15": {
+ "desc": "FIR Register - A PPE Array Scrub was missed."
+ },
+ "16": {
+ "desc": "FIR Register - A PPE Array uncorrectable error has occurred."
+ },
+ "17": {
+ "desc": "FIR Register - A PPE Array correctable error has occurred."
+ },
+ "18": {
+ "desc": "FIR Register - A PPE Code Recal Abort has occurred."
+ },
+ "19": {
+ "desc": "FIR Register - A PPE Code Fatal Error has occurred."
+ },
+ "20": {
+ "desc": "FIR Register - A PPE Code Warning has occurred."
+ },
+ "21": {
+ "desc": "FIR Register - A PPE Code DFT Error has occurred."
+ },
+ "22": {
+ "desc": "FIR Register - A PPE Code Recal Not Run has occurred."
+ },
+ "23": {
+ "desc": "FIR Register - A PPE Code Thread Locked has occurred."
+ },
+ "24": {
+ "desc": "FIR Register - A PPE Code FIR 6 has occurred."
+ },
+ "25": {
+ "desc": "FIR Register - A PPE Code FIR 7 has occurred."
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pau_ptl_fir.json b/chip_data/p10_10/node_pau_ptl_fir.json
new file mode 100644
index 0000000..5ab7326
--- /dev/null
+++ b/chip_data/p10_10/node_pau_ptl_fir.json
@@ -0,0 +1,390 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PAU_PTL_FIR": {
+ "instances": {
+ "0": "0x10011800",
+ "1": "0x11011800",
+ "2": "0x12011800",
+ "3": "0x13011800"
+ }
+ },
+ "PAU_PTL_FIR_MASK": {
+ "instances": {
+ "0": "0x10011803",
+ "1": "0x11011803",
+ "2": "0x12011803",
+ "3": "0x13011803"
+ }
+ },
+ "PAU_PTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x10011806",
+ "1": "0x11011806",
+ "2": "0x12011806",
+ "3": "0x13011806"
+ }
+ },
+ "PAU_PTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x10011807",
+ "1": "0x11011807",
+ "2": "0x12011807",
+ "3": "0x13011807"
+ }
+ },
+ "PAU_PTL_FIR_WOF": {
+ "instances": {
+ "0": "0x10011808",
+ "1": "0x11011808",
+ "2": "0x12011808",
+ "3": "0x13011808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_PTL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "fmr00 trained. Even PTL, even half."
+ },
+ "1": {
+ "desc": "fmr01 trained. Even PTL, odd half."
+ },
+ "2": {
+ "desc": "fmr02 trained. Odd PTL, even half."
+ },
+ "3": {
+ "desc": "fmr03 trained. Odd PTL, odd half."
+ },
+ "4": {
+ "desc": "dob01 ue"
+ },
+ "5": {
+ "desc": "dob01 ce"
+ },
+ "6": {
+ "desc": "dob01 sue"
+ },
+ "7": {
+ "desc": "data outbound switch internal error - even PTL.",
+ "child_node": {
+ "name": "PB_DOB01_DIB01_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "8": {
+ "desc": "dob23 ue"
+ },
+ "9": {
+ "desc": "dob23 ce"
+ },
+ "10": {
+ "desc": "dob23 sue"
+ },
+ "11": {
+ "desc": "data outbound switch internal error - odd PTL.",
+ "child_node": {
+ "name": "PB_DOB23_DIB23_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "12": {
+ "desc": "Even PTL, even framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Even PTL, outbound switch cmd/presp/cresp internal error"
+ },
+ "14": {
+ "desc": "Even PTL, odd framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "15": {
+ "desc": "Odd PTL, even framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Odd PTL, outbound switch cmd/presp/cresp internal error"
+ },
+ "17": {
+ "desc": "Odd PTL, odd framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "18": {
+ "desc": "Even PTL, even parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "19": {
+ "desc": "Even PTL, odd parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "20": {
+ "desc": "Odd PTL, even parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Odd PTL, odd parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "22": {
+ "desc": "Even PTL, even link down"
+ },
+ "23": {
+ "desc": "Even PTL, odd link down"
+ },
+ "24": {
+ "desc": "Odd PTL, even link down"
+ },
+ "25": {
+ "desc": "Odd PTL, odd link down"
+ },
+ "26": {
+ "desc": "Even PTL data inbound switch internal error",
+ "child_node": {
+ "name": "PB_DOB01_DIB01_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "27": {
+ "desc": "Odd PTL data inbound switch internal error",
+ "child_node": {
+ "name": "PB_DOB23_DIB23_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "mailbox 00 special attention"
+ },
+ "29": {
+ "desc": "mailbox 01 special attention"
+ },
+ "30": {
+ "desc": "mailbox 10 special attention"
+ },
+ "31": {
+ "desc": "mailbox 11 special attention"
+ },
+ "32": {
+ "desc": "mailbox 20 special attention"
+ },
+ "33": {
+ "desc": "mailbox 21 special attention"
+ },
+ "34": {
+ "desc": "mailbox 30 special attention"
+ },
+ "35": {
+ "desc": "mailbox 31 special attention"
+ },
+ "36": {
+ "desc": "ptl0 spare"
+ },
+ "37": {
+ "desc": "ptl1 spare"
+ },
+ "38": {
+ "desc": "ptl2 spare"
+ },
+ "39": {
+ "desc": "ptl3 spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PAU_PTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_ext_fir.json b/chip_data/p10_10/node_pb_ext_fir.json
new file mode 100644
index 0000000..6a04a6e
--- /dev/null
+++ b/chip_data/p10_10/node_pb_ext_fir.json
@@ -0,0 +1,93 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_EXT_FIR": {
+ "instances": {
+ "0": "0x030113AE"
+ }
+ },
+ "PB_EXT_FIR_MASK": {
+ "instances": {
+ "0": "0x030113B1"
+ }
+ },
+ "PB_EXT_FIR_ACT0": {
+ "instances": {
+ "0": "0x030113B4"
+ }
+ },
+ "PB_EXT_FIR_ACT1": {
+ "instances": {
+ "0": "0x030113B5"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_EXT_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "pb_x0_fir_err"
+ },
+ "1": {
+ "desc": "pb_x1_fir_err"
+ },
+ "2": {
+ "desc": "pb_x2_fir_err"
+ },
+ "3": {
+ "desc": "pb_x3_fir_err"
+ },
+ "4": {
+ "desc": "pb_x4_fir_err"
+ },
+ "5": {
+ "desc": "pb_x5_fir_err"
+ },
+ "6": {
+ "desc": "pb_x6_fir_err"
+ },
+ "7": {
+ "desc": "pb_x7_fir_err"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_en1.json b/chip_data/p10_10/node_pb_station_fir_en1.json
new file mode 100644
index 0000000..f7c9376
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_en1.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_EN1": {
+ "instances": {
+ "0": "0x03011200"
+ }
+ },
+ "PB_STATION_FIR_EN1_MASK": {
+ "instances": {
+ "0": "0x03011203"
+ }
+ },
+ "PB_STATION_FIR_EN1_ACT0": {
+ "instances": {
+ "0": "0x03011206"
+ }
+ },
+ "PB_STATION_FIR_EN1_ACT1": {
+ "instances": {
+ "0": "0x03011207"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN1": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN1",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_en2.json b/chip_data/p10_10/node_pb_station_fir_en2.json
new file mode 100644
index 0000000..b1e0c02
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_en2.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_EN2": {
+ "instances": {
+ "0": "0x03011240"
+ }
+ },
+ "PB_STATION_FIR_EN2_MASK": {
+ "instances": {
+ "0": "0x03011243"
+ }
+ },
+ "PB_STATION_FIR_EN2_ACT0": {
+ "instances": {
+ "0": "0x03011246"
+ }
+ },
+ "PB_STATION_FIR_EN2_ACT1": {
+ "instances": {
+ "0": "0x03011247"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN2": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN2",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_en3.json b/chip_data/p10_10/node_pb_station_fir_en3.json
new file mode 100644
index 0000000..52c0d2f
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_en3.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_EN3": {
+ "instances": {
+ "0": "0x03011280"
+ }
+ },
+ "PB_STATION_FIR_EN3_MASK": {
+ "instances": {
+ "0": "0x03011283"
+ }
+ },
+ "PB_STATION_FIR_EN3_ACT0": {
+ "instances": {
+ "0": "0x03011286"
+ }
+ },
+ "PB_STATION_FIR_EN3_ACT1": {
+ "instances": {
+ "0": "0x03011287"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN3": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN3",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_en4.json b/chip_data/p10_10/node_pb_station_fir_en4.json
new file mode 100644
index 0000000..dc3f87c
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_en4.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_EN4": {
+ "instances": {
+ "0": "0x030112C0"
+ }
+ },
+ "PB_STATION_FIR_EN4_MASK": {
+ "instances": {
+ "0": "0x030112C3"
+ }
+ },
+ "PB_STATION_FIR_EN4_ACT0": {
+ "instances": {
+ "0": "0x030112C6"
+ }
+ },
+ "PB_STATION_FIR_EN4_ACT1": {
+ "instances": {
+ "0": "0x030112C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN4": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN4",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_eq.json b/chip_data/p10_10/node_pb_station_fir_eq.json
new file mode 100644
index 0000000..ac36d2a
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_eq.json
@@ -0,0 +1,240 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_EQ": {
+ "instances": {
+ "0": "0x03011000",
+ "1": "0x03011040",
+ "2": "0x03011080",
+ "3": "0x030110C0",
+ "4": "0x03011100",
+ "5": "0x03011140",
+ "6": "0x03011180",
+ "7": "0x030111C0"
+ }
+ },
+ "PB_STATION_FIR_EQ_MASK": {
+ "instances": {
+ "0": "0x03011003",
+ "1": "0x03011043",
+ "2": "0x03011083",
+ "3": "0x030110C3",
+ "4": "0x03011103",
+ "5": "0x03011143",
+ "6": "0x03011183",
+ "7": "0x030111C3"
+ }
+ },
+ "PB_STATION_FIR_EQ_ACT0": {
+ "instances": {
+ "0": "0x03011006",
+ "1": "0x03011046",
+ "2": "0x03011086",
+ "3": "0x030110C6",
+ "4": "0x03011106",
+ "5": "0x03011146",
+ "6": "0x03011186",
+ "7": "0x030111C6"
+ }
+ },
+ "PB_STATION_FIR_EQ_ACT1": {
+ "instances": {
+ "0": "0x03011007",
+ "1": "0x03011047",
+ "2": "0x03011087",
+ "3": "0x030110C7",
+ "4": "0x03011107",
+ "5": "0x03011147",
+ "6": "0x03011187",
+ "7": "0x030111C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EQ": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EQ",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_es1.json b/chip_data/p10_10/node_pb_station_fir_es1.json
new file mode 100644
index 0000000..383d716
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_es1.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_ES1": {
+ "instances": {
+ "0": "0x03011300"
+ }
+ },
+ "PB_STATION_FIR_ES1_MASK": {
+ "instances": {
+ "0": "0x03011303"
+ }
+ },
+ "PB_STATION_FIR_ES1_ACT0": {
+ "instances": {
+ "0": "0x03011306"
+ }
+ },
+ "PB_STATION_FIR_ES1_ACT1": {
+ "instances": {
+ "0": "0x03011307"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES1": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES1",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_es2.json b/chip_data/p10_10/node_pb_station_fir_es2.json
new file mode 100644
index 0000000..482ec18
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_es2.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_ES2": {
+ "instances": {
+ "0": "0x03011340"
+ }
+ },
+ "PB_STATION_FIR_ES2_MASK": {
+ "instances": {
+ "0": "0x03011343"
+ }
+ },
+ "PB_STATION_FIR_ES2_ACT0": {
+ "instances": {
+ "0": "0x03011346"
+ }
+ },
+ "PB_STATION_FIR_ES2_ACT1": {
+ "instances": {
+ "0": "0x03011347"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES2": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES2",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_es3.json b/chip_data/p10_10/node_pb_station_fir_es3.json
new file mode 100644
index 0000000..be3e23d
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_es3.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_ES3": {
+ "instances": {
+ "0": "0x03011380"
+ }
+ },
+ "PB_STATION_FIR_ES3_MASK": {
+ "instances": {
+ "0": "0x03011383"
+ }
+ },
+ "PB_STATION_FIR_ES3_ACT0": {
+ "instances": {
+ "0": "0x03011386"
+ }
+ },
+ "PB_STATION_FIR_ES3_ACT1": {
+ "instances": {
+ "0": "0x03011387"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES3": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES3",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pb_station_fir_es4.json b/chip_data/p10_10/node_pb_station_fir_es4.json
new file mode 100644
index 0000000..852161b
--- /dev/null
+++ b/chip_data/p10_10/node_pb_station_fir_es4.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_STATION_FIR_ES4": {
+ "instances": {
+ "0": "0x030113C0"
+ }
+ },
+ "PB_STATION_FIR_ES4_MASK": {
+ "instances": {
+ "0": "0x030113C3"
+ }
+ },
+ "PB_STATION_FIR_ES4_ACT0": {
+ "instances": {
+ "0": "0x030113C6"
+ }
+ },
+ "PB_STATION_FIR_ES4_ACT1": {
+ "instances": {
+ "0": "0x030113C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES4": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES4",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pbaf_fir.json b/chip_data/p10_10/node_pbaf_fir.json
new file mode 100644
index 0000000..e009b2b
--- /dev/null
+++ b/chip_data/p10_10/node_pbaf_fir.json
@@ -0,0 +1,228 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PBAF_FIR": {
+ "instances": {
+ "0": "0x03011DC0"
+ }
+ },
+ "PBAF_FIR_MASK": {
+ "instances": {
+ "0": "0x03011DC3"
+ }
+ },
+ "PBAF_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011DC6"
+ }
+ },
+ "PBAF_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011DC7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PBAF_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PB CRESP Addr Error Received for Forwarded Read Request"
+ },
+ "1": {
+ "desc": "PB Read Data Timeout for Forwarded Request"
+ },
+ "2": {
+ "desc": "PB Read Data SUE Error for Forwarded Request"
+ },
+ "3": {
+ "desc": "PB Read Data UE Error for Forwarded Request"
+ },
+ "4": {
+ "desc": "PB Read Data CE Error for Forwarded Request"
+ },
+ "5": {
+ "desc": "PB Unexpected CRESP"
+ },
+ "6": {
+ "desc": "PB Unexpected Data"
+ },
+ "7": {
+ "desc": "PB Tag parity Error Detected"
+ },
+ "8": {
+ "desc": "PB CRESP Addr Error Received for Forwarded Write Request"
+ },
+ "9": {
+ "desc": "PB Invalid CRESP"
+ },
+ "10": {
+ "desc": "PB CRESP ACK Dead response received for Forwarded Read request"
+ },
+ "11": {
+ "desc": "PB OPERATIONAL Timeout detected"
+ },
+ "12": {
+ "desc": "BCUE PowerBus Link Dead"
+ },
+ "13": {
+ "desc": "PB CRESP Addr Error Received for BCUE Write Request"
+ },
+ "14": {
+ "desc": "BCDE PowerBus Link Dead"
+ },
+ "15": {
+ "desc": "PB CRESP Addr Error Received for BCDE Read Request"
+ },
+ "16": {
+ "desc": "PB Read Data Timeout for BCDE Request"
+ },
+ "17": {
+ "desc": "PB Read Data SUE Error for BCDE Request"
+ },
+ "18": {
+ "desc": "PB Read Data UE Error for BCDE Request"
+ },
+ "19": {
+ "desc": "PB Read Data CE Error for BCDE Request"
+ },
+ "20": {
+ "desc": "Internal Logic Error"
+ },
+ "21": {
+ "desc": "Byte count is less than full cache line"
+ },
+ "22": {
+ "desc": "PBAXRCV Low data before High Data"
+ },
+ "23": {
+ "desc": "PBAXRCV Low data timeout"
+ },
+ "24": {
+ "desc": "PBAXRCV Reservation data timeout"
+ },
+ "25": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "26": {
+ "desc": "PBAXSND engine retry threshold reached sending Phase 1"
+ },
+ "27": {
+ "desc": "PBAXSND engine retry threshold reached sending Phase 2"
+ },
+ "28": {
+ "desc": "PBAXSND Reservation Timeout"
+ },
+ "29": {
+ "desc": "PB CRESP ACK Dead response received"
+ },
+ "30": {
+ "desc": "PBAXIRCV Low data before High Data"
+ },
+ "31": {
+ "desc": "PBAXIRCV Low data timeout"
+ },
+ "32": {
+ "desc": "PBAXIRCV Reservation data timeout"
+ },
+ "33": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "34": {
+ "desc": "PBAXISND engine retry threshold reached sending Phase 1"
+ },
+ "35": {
+ "desc": "PBAXISND engine retry threshold reached sending Phase 2"
+ },
+ "36": {
+ "desc": "PBAXISND Reservation Timeout"
+ },
+ "37": {
+ "desc": "spare"
+ },
+ "38": {
+ "desc": "spare"
+ },
+ "39": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PBAF_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pbao_fir.json b/chip_data/p10_10/node_pbao_fir.json
new file mode 100644
index 0000000..95261f5
--- /dev/null
+++ b/chip_data/p10_10/node_pbao_fir.json
@@ -0,0 +1,168 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PBAO_FIR": {
+ "instances": {
+ "0": "0x01010CC0"
+ }
+ },
+ "PBAO_FIR_MASK": {
+ "instances": {
+ "0": "0x01010CC3"
+ }
+ },
+ "PBAO_FIR_ACT0": {
+ "instances": {
+ "0": "0x01010CC6"
+ }
+ },
+ "PBAO_FIR_ACT1": {
+ "instances": {
+ "0": "0x01010CC7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PBAO_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OCI Address Parity Error Det"
+ },
+ "1": {
+ "desc": "PBA OCI Slave Initialization Error"
+ },
+ "2": {
+ "desc": "OCI Write Data Parity Error Detected"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "BCUE Setup Error"
+ },
+ "5": {
+ "desc": "BCUE Read Data Parity Error OR MRDERR Asserted"
+ },
+ "6": {
+ "desc": "BCDE Setup Error"
+ },
+ "7": {
+ "desc": "BCDE Write Data error indicated by OCI Slave"
+ },
+ "8": {
+ "desc": "Internal Logic Error"
+ },
+ "9": {
+ "desc": "Illegal access to OCI Register"
+ },
+ "10": {
+ "desc": "Push Write Error"
+ },
+ "11": {
+ "desc": "Push Write Error"
+ },
+ "12": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "13": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "14": {
+ "desc": "PBAXSND Reservation Error"
+ },
+ "15": {
+ "desc": "PBAXISND Reservation Error"
+ },
+ "16": {
+ "desc": "htm fifo interface fequency variation error"
+ },
+ "17": {
+ "desc": "Invalide PB topology translate table entry"
+ },
+ "18": {
+ "desc": "spare"
+ },
+ "19": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PBAO_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pci_etu_fir.json b/chip_data/p10_10/node_pci_etu_fir.json
new file mode 100644
index 0000000..449a9f9
--- /dev/null
+++ b/chip_data/p10_10/node_pci_etu_fir.json
@@ -0,0 +1,322 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PCI_ETU_FIR": {
+ "instances": {
+ "0": "0x08010908",
+ "1": "0x08010948",
+ "2": "0x08010988",
+ "3": "0x09010908",
+ "4": "0x09010948",
+ "5": "0x09010988"
+ }
+ },
+ "PCI_ETU_FIR_MASK": {
+ "instances": {
+ "0": "0x0801090B",
+ "1": "0x0801094B",
+ "2": "0x0801098B",
+ "3": "0x0901090B",
+ "4": "0x0901094B",
+ "5": "0x0901098B"
+ }
+ },
+ "PCI_ETU_FIR_ACT0": {
+ "instances": {
+ "0": "0x0801090E",
+ "1": "0x0801094E",
+ "2": "0x0801098E",
+ "3": "0x0901090E",
+ "4": "0x0901094E",
+ "5": "0x0901098E"
+ }
+ },
+ "PCI_ETU_FIR_ACT1": {
+ "instances": {
+ "0": "0x0801090F",
+ "1": "0x0801094F",
+ "2": "0x0801098F",
+ "3": "0x0901090F",
+ "4": "0x0901094F",
+ "5": "0x0901098F"
+ }
+ },
+ "PCI_ETU_FIR_WOF": {
+ "instances": {
+ "0": "0x08010910",
+ "1": "0x08010950",
+ "2": "0x08010990",
+ "3": "0x09010910",
+ "4": "0x09010950",
+ "5": "0x09010990"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_ETU_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "AIB_COMMAND_INVALID"
+ },
+ "1": {
+ "desc": "AIB_ADDRESS_INVALID"
+ },
+ "2": {
+ "desc": "AIB_ACCESS_ERROR"
+ },
+ "3": {
+ "desc": "PAPR_OUTBOUND_INJECT_ERROR"
+ },
+ "4": {
+ "desc": "AIB_FATAL_CLASS_ERROR"
+ },
+ "5": {
+ "desc": "AIB_INF_CLASS_ERROR"
+ },
+ "6": {
+ "desc": "spare"
+ },
+ "7": {
+ "desc": "PE_STOP_STATE_SIGNALED"
+ },
+ "8": {
+ "desc": "OUT_COMMON_ARRAY_FATAL_ERROR"
+ },
+ "9": {
+ "desc": "OUT_COMMON_LATCH_FATAL_ERROR"
+ },
+ "10": {
+ "desc": "OUT_COMMON_LOGIC_FATAL_ERROR"
+ },
+ "11": {
+ "desc": "BLIF_OUT_INTERFACE_PARITY_ERROR"
+ },
+ "12": {
+ "desc": "CFG_WRITE_CA_OR_UR_RESPONSE"
+ },
+ "13": {
+ "desc": "MMIO_REQUEST_TIMEOUT"
+ },
+ "14": {
+ "desc": "OUT_RRB_SOURCED_ERROR"
+ },
+ "15": {
+ "desc": "CFG_LOGIC_SIGNALED_ERROR"
+ },
+ "16": {
+ "desc": "RSB_REG_REQUEST_ADDRESS_ERROR"
+ },
+ "17": {
+ "desc": "RSB_FDA_FATAL_ERROR"
+ },
+ "18": {
+ "desc": "RSB_FDA_INF_ERROR"
+ },
+ "19": {
+ "desc": "RSB_FDB_FATAL_ERROR"
+ },
+ "20": {
+ "desc": "RSB_FDB_INF_ERROR"
+ },
+ "21": {
+ "desc": "RSB_ERR_FATAL_ERROR"
+ },
+ "22": {
+ "desc": "RSB_ERR_INF_ERROR"
+ },
+ "23": {
+ "desc": "RSB_DBG_FATAL_ERROR"
+ },
+ "24": {
+ "desc": "RSB_DBG_INF_ERROR"
+ },
+ "25": {
+ "desc": "PCIE_REQUEST_ACCESS_ERROR"
+ },
+ "26": {
+ "desc": "RSB_BUS_LOGIC_ERROR"
+ },
+ "27": {
+ "desc": "RSB_UVI_FATAL_ERROR"
+ },
+ "28": {
+ "desc": "RSB_UVI_INF_ERROR"
+ },
+ "29": {
+ "desc": "SCOM_FATAL_ERROR"
+ },
+ "30": {
+ "desc": "SCOM_INF_ERROR"
+ },
+ "31": {
+ "desc": "PCIE_MACRO_ERROR_ACTIVE_STATUS"
+ },
+ "32": {
+ "desc": "ARB_IODA_FATAL_ERROR"
+ },
+ "33": {
+ "desc": "ARB_MSI_PE_MATCH_ERROR"
+ },
+ "34": {
+ "desc": "ARB_MSI_ADDRESS_ERROR"
+ },
+ "35": {
+ "desc": "ARB_TVT_ERROR"
+ },
+ "36": {
+ "desc": "ARB_RCVD_FATAL_ERROR_MSG"
+ },
+ "37": {
+ "desc": "ARB_RCVD_NONFATAL_ERROR_MSG"
+ },
+ "38": {
+ "desc": "ARB_RCVD_CORRECTIBLE_ERROR_MSG"
+ },
+ "39": {
+ "desc": "PAPR_INBOUND_INJECT_ERROR"
+ },
+ "40": {
+ "desc": "ARB_COMMON_FATAL_ERROR"
+ },
+ "41": {
+ "desc": "ARB_TABLE_BAR_DISABLED_ERROR"
+ },
+ "42": {
+ "desc": "ARB_BLIF_COMPLETION_ERROR"
+ },
+ "43": {
+ "desc": "ARB_PCT_TIMEOUT_ERROR"
+ },
+ "44": {
+ "desc": "ARB_ECC_CORRECTABLE_ERROR"
+ },
+ "45": {
+ "desc": "ARB_ECC_UNCORRECTABLE_ERROR"
+ },
+ "46": {
+ "desc": "ARB_TLP_POISON_SIGNALED"
+ },
+ "47": {
+ "desc": "ARB_RTT_PENUM_INVALID_ERROR"
+ },
+ "48": {
+ "desc": "MRG_COMMON_FATAL_ERROR"
+ },
+ "49": {
+ "desc": "MRG_TABLE_BAR_DISABLED_ERROR"
+ },
+ "50": {
+ "desc": "MRG_ECC_CORRECTABLE_ERROR"
+ },
+ "51": {
+ "desc": "MRG_ECC_UNCORRECTABLE_ERROR"
+ },
+ "52": {
+ "desc": "MRG_AIB2_TX_TIMEOUT_ERROR"
+ },
+ "53": {
+ "desc": "MRG_MRT_ERROR"
+ },
+ "54": {
+ "desc": "spare"
+ },
+ "55": {
+ "desc": "spare"
+ },
+ "56": {
+ "desc": "TCE_IODA_PAGE_ACCESS_ERROR"
+ },
+ "57": {
+ "desc": "TCE_REQUEST_TIMEOUT_ERROR"
+ },
+ "58": {
+ "desc": "TCE_UNEXPECTED_RESPONSE_ERROR"
+ },
+ "59": {
+ "desc": "TCE_COMMON_FATAL_ERROR"
+ },
+ "60": {
+ "desc": "TCE_ECC_CORRECTABLE_ERROR"
+ },
+ "61": {
+ "desc": "TCE_ECC_UNCORRECTABLE_ERROR"
+ },
+ "62": {
+ "desc": "spare"
+ },
+ "63": {
+ "desc": "FIR_INTERNAL_PARITY_ERROR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pci_fir.json b/chip_data/p10_10/node_pci_fir.json
new file mode 100644
index 0000000..a0eb5a6
--- /dev/null
+++ b/chip_data/p10_10/node_pci_fir.json
@@ -0,0 +1,161 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PCI_FIR": {
+ "instances": {
+ "0": "0x08010840",
+ "1": "0x08010880",
+ "2": "0x080108C0",
+ "3": "0x09010840",
+ "4": "0x09010880",
+ "5": "0x090108C0"
+ }
+ },
+ "PCI_FIR_MASK": {
+ "instances": {
+ "0": "0x08010843",
+ "1": "0x08010883",
+ "2": "0x080108C3",
+ "3": "0x09010843",
+ "4": "0x09010883",
+ "5": "0x090108C3"
+ }
+ },
+ "PCI_FIR_ACT0": {
+ "instances": {
+ "0": "0x08010846",
+ "1": "0x08010886",
+ "2": "0x080108C6",
+ "3": "0x09010846",
+ "4": "0x09010886",
+ "5": "0x090108C6"
+ }
+ },
+ "PCI_FIR_ACT1": {
+ "instances": {
+ "0": "0x08010847",
+ "1": "0x08010887",
+ "2": "0x080108C7",
+ "3": "0x09010847",
+ "4": "0x09010887",
+ "5": "0x090108C7"
+ }
+ },
+ "PCI_FIR_WOF": {
+ "instances": {
+ "0": "0x08010848",
+ "1": "0x08010888",
+ "2": "0x080108C8",
+ "3": "0x09010848",
+ "4": "0x09010888",
+ "5": "0x090108C8"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "register parity error"
+ },
+ "1": {
+ "desc": "hardware error"
+ },
+ "2": {
+ "desc": "AIB interface error"
+ },
+ "3": {
+ "desc": "ETU reset error"
+ },
+ "4": {
+ "desc": "PEC SCOM error"
+ },
+ "5": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PCI_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pci_iop_fir.json b/chip_data/p10_10/node_pci_iop_fir.json
new file mode 100644
index 0000000..3d87a9c
--- /dev/null
+++ b/chip_data/p10_10/node_pci_iop_fir.json
@@ -0,0 +1,176 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PCI_IOP_FIR": {
+ "instances": {
+ "0": "0x08011100",
+ "1": "0x08011500",
+ "2": "0x09011100",
+ "3": "0x09011500"
+ }
+ },
+ "PCI_IOP_FIR_MASK": {
+ "instances": {
+ "0": "0x08011103",
+ "1": "0x08011503",
+ "2": "0x09011103",
+ "3": "0x09011503"
+ }
+ },
+ "PCI_IOP_FIR_ACT0": {
+ "instances": {
+ "0": "0x08011106",
+ "1": "0x08011506",
+ "2": "0x09011106",
+ "3": "0x09011506"
+ }
+ },
+ "PCI_IOP_FIR_ACT1": {
+ "instances": {
+ "0": "0x08011107",
+ "1": "0x08011507",
+ "2": "0x09011107",
+ "3": "0x09011507"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_IOP_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Correctable error in PH0 arrays"
+ },
+ "1": {
+ "desc": "Uncorrectable error in PH0 arrays"
+ },
+ "2": {
+ "desc": "Correctable error in PH1 arrays"
+ },
+ "3": {
+ "desc": "Uncorrectable error in PH1 arrays"
+ },
+ "4": {
+ "desc": "Correctable error from SCOM in WRAP0"
+ },
+ "5": {
+ "desc": "Uncorrectable error from SCOM in WRAP0"
+ },
+ "6": {
+ "desc": "Correctable error from SCOM in WRAP1"
+ },
+ "7": {
+ "desc": "Uncorrectable error from SCOM in WRAP1"
+ },
+ "8": {
+ "desc": "Correctable error from SCRUB in WRAP0"
+ },
+ "9": {
+ "desc": "Uncorrectable error from SCRUB in WRAP0"
+ },
+ "10": {
+ "desc": "Correctable error from SCRUB in WRAP1"
+ },
+ "11": {
+ "desc": "Uncorrectable error from SCRUB in WRAP1"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pci_local_fir.json b/chip_data/p10_10/node_pci_local_fir.json
new file mode 100644
index 0000000..b2b62db
--- /dev/null
+++ b/chip_data/p10_10/node_pci_local_fir.json
@@ -0,0 +1,433 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PCI_LOCAL_FIR": {
+ "instances": {
+ "0": "0x08040100",
+ "1": "0x09040100"
+ }
+ },
+ "PCI_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x08040103",
+ "1": "0x09040103"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x08040106",
+ "1": "0x09040106"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x08040107",
+ "1": "0x09040107"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x08040109",
+ "1": "0x09040109"
+ }
+ },
+ "PCI_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x08040108",
+ "1": "0x09040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_LOCAL_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_pci_nest_fir.json b/chip_data/p10_10/node_pci_nest_fir.json
new file mode 100644
index 0000000..ba733fd
--- /dev/null
+++ b/chip_data/p10_10/node_pci_nest_fir.json
@@ -0,0 +1,227 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PCI_NEST_FIR": {
+ "instances": {
+ "0": "0x03011840",
+ "1": "0x03011880",
+ "2": "0x030118C0",
+ "3": "0x02011840",
+ "4": "0x02011880",
+ "5": "0x020118C0"
+ }
+ },
+ "PCI_NEST_FIR_MASK": {
+ "instances": {
+ "0": "0x03011843",
+ "1": "0x03011883",
+ "2": "0x030118C3",
+ "3": "0x02011843",
+ "4": "0x02011883",
+ "5": "0x020118C3"
+ }
+ },
+ "PCI_NEST_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011846",
+ "1": "0x03011886",
+ "2": "0x030118C6",
+ "3": "0x02011846",
+ "4": "0x02011886",
+ "5": "0x020118C6"
+ }
+ },
+ "PCI_NEST_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011847",
+ "1": "0x03011887",
+ "2": "0x030118C7",
+ "3": "0x02011847",
+ "4": "0x02011887",
+ "5": "0x020118C7"
+ }
+ },
+ "PCI_NEST_FIR_WOF": {
+ "instances": {
+ "0": "0x03011848",
+ "1": "0x03011888",
+ "2": "0x030118C8",
+ "3": "0x02011848",
+ "4": "0x02011888",
+ "5": "0x020118C8"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_NEST_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "BAR Parity Error"
+ },
+ "1": {
+ "desc": "Non-BAR Parity Error"
+ },
+ "2": {
+ "desc": "Power Bus to PEC CE"
+ },
+ "3": {
+ "desc": "Power Bus to PEC UE"
+ },
+ "4": {
+ "desc": "Power Bus to PEC SUE"
+ },
+ "5": {
+ "desc": "Array CE"
+ },
+ "6": {
+ "desc": "Array UE"
+ },
+ "7": {
+ "desc": "Array SUE"
+ },
+ "8": {
+ "desc": "Register Array Parity Error"
+ },
+ "9": {
+ "desc": "Power Bus Interface Parity Error"
+ },
+ "10": {
+ "desc": "Power Bus Data Hang"
+ },
+ "11": {
+ "desc": "Power Bus Hang Error"
+ },
+ "12": {
+ "desc": "RD ARE Error"
+ },
+ "13": {
+ "desc": "Non-Rd ARE Error"
+ },
+ "14": {
+ "desc": "PCI Hang Error"
+ },
+ "15": {
+ "desc": "PCI Clock Error"
+ },
+ "16": {
+ "desc": "AIB Fence"
+ },
+ "17": {
+ "desc": "Hardware Error"
+ },
+ "18": {
+ "desc": "Unsolicited Power Bus Data"
+ },
+ "19": {
+ "desc": "Unexpected Combined Response"
+ },
+ "20": {
+ "desc": "Invalid Combined Response"
+ },
+ "21": {
+ "desc": "Power Bus Unsupported Size"
+ },
+ "22": {
+ "desc": "Power Bus Unsupported Command"
+ },
+ "23": {
+ "desc": "reserved"
+ },
+ "24": {
+ "desc": "reserved"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "Software Defined"
+ },
+ "27": {
+ "desc": "PEC SCOM Engine Error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PCI_NEST_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_psihb_fir.json b/chip_data/p10_10/node_psihb_fir.json
new file mode 100644
index 0000000..fd88238
--- /dev/null
+++ b/chip_data/p10_10/node_psihb_fir.json
@@ -0,0 +1,184 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PSIHB_FIR": {
+ "instances": {
+ "0": "0x03011D00"
+ }
+ },
+ "PSIHB_FIR_MASK": {
+ "instances": {
+ "0": "0x03011D03"
+ }
+ },
+ "PSIHB_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011D06"
+ }
+ },
+ "PSIHB_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011D07"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PSIHB_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CE from PowerBus data"
+ },
+ "1": {
+ "desc": "UE from PowerBus data"
+ },
+ "2": {
+ "desc": "SUE from PowerBus data"
+ },
+ "3": {
+ "desc": "Interrupt Condition present in PSIHB"
+ },
+ "4": {
+ "desc": "Interrupt from FSP is being processed"
+ },
+ "5": {
+ "desc": "CE from PSILL data"
+ },
+ "6": {
+ "desc": "UE from PSILL data"
+ },
+ "7": {
+ "desc": "Error bit set, ignores the interrupt mask"
+ },
+ "8": {
+ "desc": "Invalid TType Hit on PHB or FSP bar"
+ },
+ "9": {
+ "desc": "Invalid CResp returned to command issued by PSIHB"
+ },
+ "10": {
+ "desc": "PowerBus time out waiting for data grant"
+ },
+ "11": {
+ "desc": "PB parity error"
+ },
+ "12": {
+ "desc": "FSP tried access to trusted space"
+ },
+ "13": {
+ "desc": "Unexpected PB CRESP or DATA"
+ },
+ "14": {
+ "desc": "Interrupt register change while interrupt still pending"
+ },
+ "15": {
+ "desc": "PSI Interrupt address Error"
+ },
+ "16": {
+ "desc": "OCC Interrupt address Error"
+ },
+ "17": {
+ "desc": "FSI Interrupt address Error"
+ },
+ "18": {
+ "desc": "LPC Interrupt address Error"
+ },
+ "19": {
+ "desc": "LOCAL ERROR Interrupt address Error"
+ },
+ "20": {
+ "desc": "HOST ERROR Interrupt address Error"
+ },
+ "21": {
+ "desc": "PSI global error bit 0"
+ },
+ "22": {
+ "desc": "PSI global error bit 1"
+ },
+ "23": {
+ "desc": "Upstream error"
+ },
+ "24": {
+ "desc": "spare"
+ },
+ "25": {
+ "desc": "spare"
+ },
+ "26": {
+ "desc": "spare"
+ },
+ "27": {
+ "desc": "fir parity Error"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_tp_local_fir.json b/chip_data/p10_10/node_tp_local_fir.json
new file mode 100644
index 0000000..0baa7cc
--- /dev/null
+++ b/chip_data/p10_10/node_tp_local_fir.json
@@ -0,0 +1,447 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "TP_LOCAL_FIR": {
+ "instances": {
+ "0": "0x01040100"
+ }
+ },
+ "TP_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x01040103"
+ }
+ },
+ "TP_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x01040106"
+ }
+ },
+ "TP_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x01040107"
+ }
+ },
+ "TP_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x01040109"
+ }
+ },
+ "TP_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x01040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TP_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "ITR - FMU error"
+ },
+ "22": {
+ "desc": "ITR - PCB error"
+ },
+ "23": {
+ "desc": "PCB Master - timeout"
+ },
+ "24": {
+ "desc": "I2CM - Parity errors"
+ },
+ "25": {
+ "desc": "TOD - any error",
+ "child_node": {
+ "name": "TOD_ERROR"
+ }
+ },
+ "26": {
+ "desc": "TOD - access error PIB"
+ },
+ "27": {
+ "desc": "TOD - Error reported from PHYP"
+ },
+ "28": {
+ "desc": "PCB slave error",
+ "child_node": {
+ "name": "PLL_UNLOCK"
+ }
+ },
+ "29": {
+ "desc": "SBE - PPE int hardware error"
+ },
+ "30": {
+ "desc": "SBE - PPE ext hardware error"
+ },
+ "31": {
+ "desc": "SBE - PPE code error"
+ },
+ "32": {
+ "desc": "SBE - PPE debug code breakpoint"
+ },
+ "33": {
+ "desc": "SBE - PPE in halted state"
+ },
+ "34": {
+ "desc": "SBE - PPE watchdog timeout"
+ },
+ "35": {
+ "desc": "SBE - unused"
+ },
+ "36": {
+ "desc": "SBE - unused"
+ },
+ "37": {
+ "desc": "SBE - PPE triggers DBG"
+ },
+ "38": {
+ "desc": "OTP - SCOM access errors and single ecc correctable"
+ },
+ "39": {
+ "desc": "TPIO External Trigger"
+ },
+ "40": {
+ "desc": "PCB Master - Multicast group member count underrun (MC misconfig)"
+ },
+ "41": {
+ "desc": "PCB Master - Parity ERR"
+ },
+ "42": {
+ "desc": "RCS OSC error on clk A"
+ },
+ "43": {
+ "desc": "RCS OSC error on clk B"
+ },
+ "44": {
+ "desc": "RCS - Up/down counter A unlock"
+ },
+ "45": {
+ "desc": "RCS - Up/down counter B unlock"
+ },
+ "46": {
+ "desc": "PIBMEM"
+ },
+ "47": {
+ "desc": "PIBMEM"
+ },
+ "48": {
+ "desc": "OTP - ECC UE or CE count overflow"
+ },
+ "49": {
+ "desc": "Nest DPLL: DCO empty"
+ },
+ "50": {
+ "desc": "Nest DPLL: DCO full"
+ },
+ "51": {
+ "desc": "Nest DPLL: internal error"
+ },
+ "52": {
+ "desc": "PAU DPLL: DCO empty"
+ },
+ "53": {
+ "desc": "PAU DPLL: DCO full"
+ },
+ "54": {
+ "desc": "PAU DPLL: internal error"
+ },
+ "55": {
+ "desc": "SPI Master 0 Err"
+ },
+ "56": {
+ "desc": "SPI Master 1 Err"
+ },
+ "57": {
+ "desc": "SPI Master 2 Err"
+ },
+ "58": {
+ "desc": "SPI Master 3 Err"
+ },
+ "59": {
+ "desc": "SPI Master 4 Err"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "TOD_ERROR",
+ "group_inst": {
+ "0": 0
+ }
+ },
+ {
+ "group_name": "RCS_PLL",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_10/node_vas_fir.json b/chip_data/p10_10/node_vas_fir.json
new file mode 100644
index 0000000..f2d3234
--- /dev/null
+++ b/chip_data/p10_10/node_vas_fir.json
@@ -0,0 +1,289 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "VAS_FIR": {
+ "instances": {
+ "0": "0x02011400"
+ }
+ },
+ "VAS_FIR_MASK": {
+ "instances": {
+ "0": "0x02011403"
+ }
+ },
+ "VAS_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011406"
+ }
+ },
+ "VAS_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011407"
+ }
+ },
+ "VAS_FIR_WOF": {
+ "instances": {
+ "0": "0x02011408"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "VAS_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Hardware error detected in Egress logic"
+ },
+ "1": {
+ "desc": "Hardware error detected in Ingress logic"
+ },
+ "2": {
+ "desc": "Hardware error detected in CQ logic"
+ },
+ "3": {
+ "desc": "Hardware error detected in WC logic"
+ },
+ "4": {
+ "desc": "Hardware error detected in RG logic"
+ },
+ "5": {
+ "desc": "PowerBus parity error detected on CQ logic interface"
+ },
+ "6": {
+ "desc": "CQ logic detected PowerBus address error on CRESP from a read operation"
+ },
+ "7": {
+ "desc": "CQ logic detected PowerBus address error on CRESP from a write operation"
+ },
+ "8": {
+ "desc": "Correctable ECC error detected in Egress logic"
+ },
+ "9": {
+ "desc": "Correctable ECC error detected in Ingress logic"
+ },
+ "10": {
+ "desc": "Correctable ECC error detected in CQ logic"
+ },
+ "11": {
+ "desc": "Correctable ECC error detected in WC logic"
+ },
+ "12": {
+ "desc": "Correctable ECC error detected in RG logic"
+ },
+ "13": {
+ "desc": "ECC Correctable Error detected on CQ outbound PowerBus interface"
+ },
+ "14": {
+ "desc": "ECC Uncorrectable Error detected on CQ outbound PowerBus interface"
+ },
+ "15": {
+ "desc": "PowerBus state machine hang detected in CQ logic"
+ },
+ "16": {
+ "desc": "Uncorrectable ECC error detected in Egress logic"
+ },
+ "17": {
+ "desc": "Uncorrectable ECC error detected in Ingress logic"
+ },
+ "18": {
+ "desc": "Uncorrectable ECC error detected in CQ logic"
+ },
+ "19": {
+ "desc": "Uncorrectable ECC error detected in WC logic"
+ },
+ "20": {
+ "desc": "Uncorrectable ECC error detected in RG logic"
+ },
+ "21": {
+ "desc": "Parity error detected in Ingress logic"
+ },
+ "22": {
+ "desc": "Software cast error detected in Ingress logic"
+ },
+ "23": {
+ "desc": "reserved"
+ },
+ "24": {
+ "desc": "ECC sue error detected in Egress logic"
+ },
+ "25": {
+ "desc": "ECC sue error detected in Ingress logic"
+ },
+ "26": {
+ "desc": "ECC sue error detected in CQ logic"
+ },
+ "27": {
+ "desc": "ECC sue error detected in WC logic"
+ },
+ "28": {
+ "desc": "ECC sue error detected in RG logic"
+ },
+ "29": {
+ "desc": "PowerBus link error detected on read operation in CQ logic"
+ },
+ "30": {
+ "desc": "PowerBus link error detected on write operation in CQ logic"
+ },
+ "31": {
+ "desc": "PowerBus link abort operation received in CQ logic"
+ },
+ "32": {
+ "desc": "Address error detected on hypervisor MMIO read"
+ },
+ "33": {
+ "desc": "Address error detected on OS MMIO read"
+ },
+ "34": {
+ "desc": "Address error detected on hypervisor MMIO write"
+ },
+ "35": {
+ "desc": "Address error detected on OS MMIO write"
+ },
+ "36": {
+ "desc": "non-8-Byte MMIO detected by hypervisor"
+ },
+ "37": {
+ "desc": "non-8-Byte MMIO detected by user or OS"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "ASB_Notify sent but not claimed and interrupts were disabled in window context"
+ },
+ "43": {
+ "desc": "reserved"
+ },
+ "44": {
+ "desc": "VAS rejected a PB paste command"
+ },
+ "45": {
+ "desc": "VAS hung waiting for data from PowerBus"
+ },
+ "46": {
+ "desc": "Incoming PowerBus parity error"
+ },
+ "47": {
+ "desc": "HW error from SCOM Satellite 1"
+ },
+ "48": {
+ "desc": "NX Local Checkstop"
+ },
+ "49": {
+ "desc": "SCOM MMIO address offset error"
+ },
+ "50": {
+ "desc": "TopoID Error Bit"
+ },
+ "51": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/pau_pb0123_pr_err.json b/chip_data/p10_10/pau_pb0123_pr_err.json
new file mode 100644
index 0000000..b635133
--- /dev/null
+++ b/chip_data/p10_10/pau_pb0123_pr_err.json
@@ -0,0 +1,215 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_PR0123_ERR": {
+ "instances": {
+ "0": "0x10011829",
+ "1": "0x11011829",
+ "2": "0x12011829",
+ "3": "0x13011829"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_PR0123_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "prs0_address_pty"
+ },
+ "1": {
+ "desc": "prs0_atag_pty"
+ },
+ "2": {
+ "desc": "prs0_cc0_crediterr"
+ },
+ "3": {
+ "desc": "prs0_cc1_crediterr"
+ },
+ "4": {
+ "desc": "prs0_cc2_crediterr"
+ },
+ "5": {
+ "desc": "prs0_cc3_crediterr"
+ },
+ "6": {
+ "desc": "prs0_control_error"
+ },
+ "7": {
+ "desc": "prs0_data_pty_err"
+ },
+ "8": {
+ "desc": "prs0_rtag_misc_pty"
+ },
+ "9": {
+ "desc": "prs0_rtag_pty"
+ },
+ "10": {
+ "desc": "prs0_ttag_pty"
+ },
+ "11": {
+ "desc": "prs0_vc0_crediterr"
+ },
+ "12": {
+ "desc": "prs0_vc1_crediterr"
+ },
+ "13": {
+ "desc": "prs0_link_down"
+ },
+ "16": {
+ "desc": "prs1_address_pty"
+ },
+ "17": {
+ "desc": "prs1_atag_pty"
+ },
+ "18": {
+ "desc": "prs1_cc0_crediterr"
+ },
+ "19": {
+ "desc": "prs1_cc1_crediterr"
+ },
+ "20": {
+ "desc": "prs1_cc2_crediterr"
+ },
+ "21": {
+ "desc": "prs1_cc3_crediterr"
+ },
+ "22": {
+ "desc": "prs1_control_error"
+ },
+ "23": {
+ "desc": "prs1_data_pty_err"
+ },
+ "24": {
+ "desc": "prs1_rtag_misc_pty"
+ },
+ "25": {
+ "desc": "prs1_rtag_pty"
+ },
+ "26": {
+ "desc": "prs1_ttag_pty"
+ },
+ "27": {
+ "desc": "prs1_vc0_crediterr"
+ },
+ "28": {
+ "desc": "prs1_vc1_crediterr"
+ },
+ "29": {
+ "desc": "prs1_link_down"
+ },
+ "32": {
+ "desc": "prs2_address_pty"
+ },
+ "33": {
+ "desc": "prs2_atag_pty"
+ },
+ "34": {
+ "desc": "prs2_cc0_crediterr"
+ },
+ "35": {
+ "desc": "prs2_cc1_crediterr"
+ },
+ "36": {
+ "desc": "prs2_cc2_crediterr"
+ },
+ "37": {
+ "desc": "prs2_cc3_crediterr"
+ },
+ "38": {
+ "desc": "prs2_control_error"
+ },
+ "39": {
+ "desc": "prs2_data_pty_err"
+ },
+ "40": {
+ "desc": "prs2_rtag_misc_pty"
+ },
+ "41": {
+ "desc": "prs2_rtag_pty"
+ },
+ "42": {
+ "desc": "prs2_ttag_pty"
+ },
+ "43": {
+ "desc": "prs2_vc0_crediterr"
+ },
+ "44": {
+ "desc": "prs2_vc1_crediterr"
+ },
+ "45": {
+ "desc": "prs2_link_down"
+ },
+ "48": {
+ "desc": "prs3_address_pty"
+ },
+ "49": {
+ "desc": "prs3_atag_pty"
+ },
+ "50": {
+ "desc": "prs3_cc0_crediterr"
+ },
+ "51": {
+ "desc": "prs3_cc1_crediterr"
+ },
+ "52": {
+ "desc": "prs3_cc2_crediterr"
+ },
+ "53": {
+ "desc": "prs3_cc3_crediterr"
+ },
+ "54": {
+ "desc": "prs3_control_error"
+ },
+ "55": {
+ "desc": "prs3_data_pty_err"
+ },
+ "56": {
+ "desc": "prs3_rtag_misc_pty"
+ },
+ "57": {
+ "desc": "prs3_rtag_pty"
+ },
+ "58": {
+ "desc": "prs3_ttag_pty"
+ },
+ "59": {
+ "desc": "prs3_vc0_crediterr"
+ },
+ "60": {
+ "desc": "prs3_vc1_crediterr"
+ },
+ "61": {
+ "desc": "prs3_link_down"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/pau_pb_dob01_dib01_int_err.json b/chip_data/p10_10/pau_pb_dob01_dib01_int_err.json
new file mode 100644
index 0000000..d031220
--- /dev/null
+++ b/chip_data/p10_10/pau_pb_dob01_dib01_int_err.json
@@ -0,0 +1,203 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_DOB01_DIB01_INT_ERR": {
+ "instances": {
+ "0": "0x10011828",
+ "1": "0x11011828",
+ "2": "0x12011828",
+ "3": "0x13011828"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_DOB01_DIB01_INT_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "dob01_rtag_pbiterr"
+ },
+ "1": {
+ "desc": "dob01_rtag_perr"
+ },
+ "2": {
+ "desc": "dob01_misc_perr"
+ },
+ "3": {
+ "desc": "dob01_f0vc0_evenperr"
+ },
+ "4": {
+ "desc": "dob01_f0vc0_oddperr"
+ },
+ "5": {
+ "desc": "dob01_f0vc1_evenperr"
+ },
+ "6": {
+ "desc": "dob01_f0vc1_oddperr"
+ },
+ "7": {
+ "desc": "dob01_f1vc0_evenperr"
+ },
+ "8": {
+ "desc": "dob01_f1vc0_oddperr"
+ },
+ "9": {
+ "desc": "dob01_f1vc1_evenperr"
+ },
+ "10": {
+ "desc": "dob01_f1vc1_oddperr"
+ },
+ "11": {
+ "desc": "dob01_f0_underflow"
+ },
+ "12": {
+ "desc": "dob01_f0_overflow"
+ },
+ "13": {
+ "desc": "dob01_f1_underflow"
+ },
+ "14": {
+ "desc": "dob01_f1_overflow"
+ },
+ "15": {
+ "desc": "dob01_vc0_underflow"
+ },
+ "16": {
+ "desc": "dob01_vc0_overflow"
+ },
+ "17": {
+ "desc": "dob01_vc1_underflow"
+ },
+ "18": {
+ "desc": "dob01_vc1_overflow"
+ },
+ "19": {
+ "desc": "dob01_f0vc0_underflow"
+ },
+ "20": {
+ "desc": "dob01_f0vc0_overflow"
+ },
+ "21": {
+ "desc": "dob01_f0vc1_underflow"
+ },
+ "22": {
+ "desc": "dob01_f0vc1_overflow"
+ },
+ "23": {
+ "desc": "dob01_f1vc0_underflow"
+ },
+ "24": {
+ "desc": "dob01_f1vc0_overflow"
+ },
+ "25": {
+ "desc": "dob01_f1vc1_underflow"
+ },
+ "26": {
+ "desc": "dob01_f1vc1_overflow"
+ },
+ "27": {
+ "desc": "dob01_vc0_prefetch_overflow"
+ },
+ "28": {
+ "desc": "dob01_vc1_prefetch_overflow"
+ },
+ "29": {
+ "desc": "dib01_evn0_underflow"
+ },
+ "30": {
+ "desc": "dib01_evn0_overflow"
+ },
+ "31": {
+ "desc": "dib01_evn1_underflow"
+ },
+ "32": {
+ "desc": "dib01_evn1_overflow"
+ },
+ "33": {
+ "desc": "dib01_rtag_pbiterr"
+ },
+ "34": {
+ "desc": "dib01_rtag_perr"
+ },
+ "35": {
+ "desc": "dib01_misc_perr"
+ },
+ "36": {
+ "desc": "dib01_odd0_underflow"
+ },
+ "37": {
+ "desc": "dib01_odd0_overflow"
+ },
+ "38": {
+ "desc": "dib01_odd1_underflow"
+ },
+ "39": {
+ "desc": "dib01_odd1_overflow"
+ },
+ "40": {
+ "desc": "dib01_rtag_underflow"
+ },
+ "41": {
+ "desc": "dib01_rtag_overflow"
+ },
+ "42": {
+ "desc": "dib01_data_underflow"
+ },
+ "43": {
+ "desc": "dib01_data_overflow"
+ },
+ "44": {
+ "desc": "dib01_vc0_underflow"
+ },
+ "45": {
+ "desc": "dib01_vc0_overflow"
+ },
+ "46": {
+ "desc": "dib01_vc1_underflow"
+ },
+ "47": {
+ "desc": "dib01_vc1_overflow"
+ },
+ "48": {
+ "desc": "dib01_f0vc0_over_underflow"
+ },
+ "49": {
+ "desc": "dib01_f0vc1_over_underflow"
+ },
+ "50": {
+ "desc": "dib01_f1vc0_over_underflow"
+ },
+ "51": {
+ "desc": "dib01_f1vc1_over_underflow"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/pau_pb_dob23_dib23_int_err.json b/chip_data/p10_10/pau_pb_dob23_dib23_int_err.json
new file mode 100644
index 0000000..d4eb2ff
--- /dev/null
+++ b/chip_data/p10_10/pau_pb_dob23_dib23_int_err.json
@@ -0,0 +1,203 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_DOB23_DIB23_INT_ERR": {
+ "instances": {
+ "0": "0x1001182A",
+ "1": "0x1101182A",
+ "2": "0x1201182A",
+ "3": "0x1301182A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_DOB23_DIB23_INT_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "dob23_rtag_pbiterr"
+ },
+ "1": {
+ "desc": "dob23_rtag_perr"
+ },
+ "2": {
+ "desc": "dob23_misc_perr"
+ },
+ "3": {
+ "desc": "dob23_f0vc0_evenperr"
+ },
+ "4": {
+ "desc": "dob23_f0vc0_oddperr"
+ },
+ "5": {
+ "desc": "dob23_f0vc1_evenperr"
+ },
+ "6": {
+ "desc": "dob23_f0vc1_oddperr"
+ },
+ "7": {
+ "desc": "dob23_f1vc0_evenperr"
+ },
+ "8": {
+ "desc": "dob23_f1vc0_oddperr"
+ },
+ "9": {
+ "desc": "dob23_f1vc1_evenperr"
+ },
+ "10": {
+ "desc": "dob23_f1vc1_oddperr"
+ },
+ "11": {
+ "desc": "dob23_f0_underflow"
+ },
+ "12": {
+ "desc": "dob23_f0_overflow"
+ },
+ "13": {
+ "desc": "dob23_f1_underflow"
+ },
+ "14": {
+ "desc": "dob23_f1_overflow"
+ },
+ "15": {
+ "desc": "dob23_vc0_underflow"
+ },
+ "16": {
+ "desc": "dob23_vc0_overflow"
+ },
+ "17": {
+ "desc": "dob23_vc1_underflow"
+ },
+ "18": {
+ "desc": "dob23_vc1_overflow"
+ },
+ "19": {
+ "desc": "dob23_f0vc0_underflow"
+ },
+ "20": {
+ "desc": "dob23_f0vc0_overflow"
+ },
+ "21": {
+ "desc": "dob23_f0vc1_underflow"
+ },
+ "22": {
+ "desc": "dob23_f0vc1_overflow"
+ },
+ "23": {
+ "desc": "dob23_f1vc0_underflow"
+ },
+ "24": {
+ "desc": "dob23_f1vc0_overflow"
+ },
+ "25": {
+ "desc": "dob23_f1vc1_underflow"
+ },
+ "26": {
+ "desc": "dob23_f1vc1_overflow"
+ },
+ "27": {
+ "desc": "dob23_vc0_prefetch_overflow"
+ },
+ "28": {
+ "desc": "dob23_vc1_prefetch_overflow"
+ },
+ "29": {
+ "desc": "dib23_evn0_underflow"
+ },
+ "30": {
+ "desc": "dib23_evn0_overflow"
+ },
+ "31": {
+ "desc": "dib23_evn1_underflow"
+ },
+ "32": {
+ "desc": "dib23_evn1_overflow"
+ },
+ "33": {
+ "desc": "dib23_rtag_pbiterr"
+ },
+ "34": {
+ "desc": "dib23_rtag_perr"
+ },
+ "35": {
+ "desc": "dib23_misc_perr"
+ },
+ "36": {
+ "desc": "dib23_odd0_underflow"
+ },
+ "37": {
+ "desc": "dib23_odd0_overflow"
+ },
+ "38": {
+ "desc": "dib23_odd1_underflow"
+ },
+ "39": {
+ "desc": "dib23_odd1_overflow"
+ },
+ "40": {
+ "desc": "dib23_rtag_underflow"
+ },
+ "41": {
+ "desc": "dib23_rtag_overflow"
+ },
+ "42": {
+ "desc": "dib23_data_underflow"
+ },
+ "43": {
+ "desc": "dib23_data_overflow"
+ },
+ "44": {
+ "desc": "dib23_vc0_underflow"
+ },
+ "45": {
+ "desc": "dib23_vc0_overflow"
+ },
+ "46": {
+ "desc": "dib23_vc1_underflow"
+ },
+ "47": {
+ "desc": "dib23_vc1_overflow"
+ },
+ "48": {
+ "desc": "dib23_f0vc0_over_underflow"
+ },
+ "49": {
+ "desc": "dib23_f0vc1_over_underflow"
+ },
+ "50": {
+ "desc": "dib23_f1vc0_over_underflow"
+ },
+ "51": {
+ "desc": "dib23_f1vc1_over_underflow"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/pau_pb_fm0123_err.json b/chip_data/p10_10/pau_pb_fm0123_err.json
new file mode 100644
index 0000000..3adbe72
--- /dev/null
+++ b/chip_data/p10_10/pau_pb_fm0123_err.json
@@ -0,0 +1,239 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PB_FM0123_ERR": {
+ "instances": {
+ "0": "0x10011827",
+ "1": "0x11011827",
+ "2": "0x12011827",
+ "3": "0x13011827"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_FM0123_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "fmr0_control_error"
+ },
+ "1": {
+ "desc": "fmr0_addr_perr"
+ },
+ "2": {
+ "desc": "fmr0_cc0_crediterr"
+ },
+ "3": {
+ "desc": "fmr0_cc1_crediterr"
+ },
+ "4": {
+ "desc": "fmr0_cc2_crediterr"
+ },
+ "5": {
+ "desc": "fmr0_cc3_crediterr"
+ },
+ "6": {
+ "desc": "fmr0_dat_hi_perr"
+ },
+ "7": {
+ "desc": "fmr0_dat_lo_perr"
+ },
+ "8": {
+ "desc": "fmr0_frame_crediterr"
+ },
+ "9": {
+ "desc": "fmr0_internal_err"
+ },
+ "10": {
+ "desc": "fmr0_prsp_ptyerr"
+ },
+ "11": {
+ "desc": "fmr0_ttag_perr"
+ },
+ "12": {
+ "desc": "fmr0_vc0_crediterr"
+ },
+ "13": {
+ "desc": "fmr0_vc1_crediterr"
+ },
+ "14": {
+ "desc": "fmr0_rtag_ptyerr"
+ },
+ "15": {
+ "desc": "fmr0_rtag_misc_pty"
+ },
+ "16": {
+ "desc": "fmr1_control_error"
+ },
+ "17": {
+ "desc": "fmr1_addr_perr"
+ },
+ "18": {
+ "desc": "fmr1_cc0_crediterr"
+ },
+ "19": {
+ "desc": "fmr1_cc1_crediterr"
+ },
+ "20": {
+ "desc": "fmr1_cc2_crediterr"
+ },
+ "21": {
+ "desc": "fmr1_cc3_crediterr"
+ },
+ "22": {
+ "desc": "fmr1_dat_hi_perr"
+ },
+ "23": {
+ "desc": "fmr1_dat_lo_perr"
+ },
+ "24": {
+ "desc": "fmr1_frame_crediterr"
+ },
+ "25": {
+ "desc": "fmr1_internal_err"
+ },
+ "26": {
+ "desc": "fmr1_prsp_ptyerr"
+ },
+ "27": {
+ "desc": "fmr1_ttag_perr"
+ },
+ "28": {
+ "desc": "fmr1_vc0_crediterr"
+ },
+ "29": {
+ "desc": "fmr1_vc1_crediterr"
+ },
+ "30": {
+ "desc": "fmr1_rtag_ptyerr"
+ },
+ "31": {
+ "desc": "fmr1_rtag_misc_pty"
+ },
+ "32": {
+ "desc": "fmr2_control_error"
+ },
+ "33": {
+ "desc": "fmr2_addr_perr"
+ },
+ "34": {
+ "desc": "fmr2_cc0_crediterr"
+ },
+ "35": {
+ "desc": "fmr2_cc1_crediterr"
+ },
+ "36": {
+ "desc": "fmr2_cc2_crediterr"
+ },
+ "37": {
+ "desc": "fmr2_cc3_crediterr"
+ },
+ "38": {
+ "desc": "fmr2_dat_hi_perr"
+ },
+ "39": {
+ "desc": "fmr2_dat_lo_perr"
+ },
+ "40": {
+ "desc": "fmr2_frame_crediterr"
+ },
+ "41": {
+ "desc": "fmr2_internal_err"
+ },
+ "42": {
+ "desc": "fmr2_prsp_ptyerr"
+ },
+ "43": {
+ "desc": "fmr2_ttag_perr"
+ },
+ "44": {
+ "desc": "fmr2_vc0_crediterr"
+ },
+ "45": {
+ "desc": "fmr2_vc1_crediterr"
+ },
+ "46": {
+ "desc": "fmr2_rtag_ptyerr"
+ },
+ "47": {
+ "desc": "fmr2_rtag_misc_pty"
+ },
+ "48": {
+ "desc": "fmr3_control_error"
+ },
+ "49": {
+ "desc": "fmr3_addr_perr"
+ },
+ "50": {
+ "desc": "fmr3_cc0_crediterr"
+ },
+ "51": {
+ "desc": "fmr3_cc1_crediterr"
+ },
+ "52": {
+ "desc": "fmr3_cc2_crediterr"
+ },
+ "53": {
+ "desc": "fmr3_cc3_crediterr"
+ },
+ "54": {
+ "desc": "fmr3_dat_hi_perr"
+ },
+ "55": {
+ "desc": "fmr3_dat_lo_perr"
+ },
+ "56": {
+ "desc": "fmr3_frame_crediterr"
+ },
+ "57": {
+ "desc": "fmr3_internal_err"
+ },
+ "58": {
+ "desc": "fmr3_prsp_ptyerr"
+ },
+ "59": {
+ "desc": "fmr3_ttag_perr"
+ },
+ "60": {
+ "desc": "fmr3_vc0_crediterr"
+ },
+ "61": {
+ "desc": "fmr3_vc1_crediterr"
+ },
+ "62": {
+ "desc": "fmr3_rtag_ptyerr"
+ },
+ "63": {
+ "desc": "fmr3_rtag_misc_pty"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_10/rcs_pll.json b/chip_data/p10_10/rcs_pll.json
new file mode 100644
index 0000000..0c22df2
--- /dev/null
+++ b/chip_data/p10_10/rcs_pll.json
@@ -0,0 +1,1452 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "ROOT_CTRL0": {
+ "instances": {
+ "0": "0x00050010"
+ }
+ },
+ "ROOT_CTRL3": {
+ "instances": {
+ "0": "0x00050013"
+ }
+ },
+ "ROOT_CTRL4": {
+ "instances": {
+ "0": "0x00050014"
+ }
+ },
+ "ROOT_CTRL5": {
+ "instances": {
+ "0": "0x00050015"
+ }
+ },
+ "ROOT_CTRL6": {
+ "instances": {
+ "0": "0x00050016"
+ }
+ },
+ "RCS_SENSE_1": {
+ "instances": {
+ "0": "0x0005001D"
+ }
+ },
+ "RCS_SENSE_2": {
+ "instances": {
+ "0": "0x0005001E"
+ }
+ },
+ "BC_OR_PCBSLV_ERROR": {
+ "instances": {
+ "0": "0x470F001F"
+ }
+ },
+ "PCBSLV_CONFIG": {
+ "instances": {
+ "1": "0x010F001E",
+ "2": "0x020F001E",
+ "3": "0x030F001E",
+ "8": "0x080F001E",
+ "9": "0x090F001E",
+ "12": "0x0C0F001E",
+ "13": "0x0D0F001E",
+ "14": "0x0E0F001E",
+ "15": "0x0F0F001E",
+ "16": "0x100F001E",
+ "17": "0x110F001E",
+ "18": "0x120F001E",
+ "19": "0x130F001E",
+ "24": "0x180F001E",
+ "25": "0x190F001E",
+ "26": "0x1A0F001E",
+ "27": "0x1B0F001E",
+ "28": "0x1C0F001E",
+ "29": "0x1D0F001E",
+ "30": "0x1E0F001E",
+ "31": "0x1F0F001E",
+ "32": "0x200F001E",
+ "33": "0x210F001E",
+ "34": "0x220F001E",
+ "35": "0x230F001E",
+ "36": "0x240F001E",
+ "37": "0x250F001E",
+ "38": "0x260F001E",
+ "39": "0x270F001E"
+ }
+ },
+ "PCBSLV_ERROR": {
+ "instances": {
+ "1": "0x010F001F",
+ "2": "0x020F001F",
+ "3": "0x030F001F",
+ "8": "0x080F001F",
+ "9": "0x090F001F",
+ "12": "0x0C0F001F",
+ "13": "0x0D0F001F",
+ "14": "0x0E0F001F",
+ "15": "0x0F0F001F",
+ "16": "0x100F001F",
+ "17": "0x110F001F",
+ "18": "0x120F001F",
+ "19": "0x130F001F",
+ "24": "0x180F001F",
+ "25": "0x190F001F",
+ "26": "0x1A0F001F",
+ "27": "0x1B0F001F",
+ "28": "0x1C0F001F",
+ "29": "0x1D0F001F",
+ "30": "0x1E0F001F",
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+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ROOT_CTRL6",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RCS_SENSE_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RCS_SENSE_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 8
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 9
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 12
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 13
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 14
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 15
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 16
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 17
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 18
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 19
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 24
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 25
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 26
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 27
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 28
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 29
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 30
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 31
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 32
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 33
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 34
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 35
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 36
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 37
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 38
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 39
+ }
+ },
+ {
+ "reg_name": "BC_OR_PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 8
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 9
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 12
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 13
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 14
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 15
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 16
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 17
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 18
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 19
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 24
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 25
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 26
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 27
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 28
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 29
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 30
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 31
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 32
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 33
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 34
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 35
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 36
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 37
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 38
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 39
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_10/regs_eq.json b/chip_data/p10_10/regs_eq.json
new file mode 100644
index 0000000..8c00188
--- /dev/null
+++ b/chip_data/p10_10/regs_eq.json
@@ -0,0 +1,2279 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "PC_FIR_HOLD_OUT": {
+ "instances": {
+ "0": "0x20028451",
+ "1": "0x20024451",
+ "2": "0x20022451",
+ "3": "0x20021451",
+ "4": "0x21028451",
+ "5": "0x21024451",
+ "6": "0x21022451",
+ "7": "0x21021451",
+ "8": "0x22028451",
+ "9": "0x22024451",
+ "10": "0x22022451",
+ "11": "0x22021451",
+ "12": "0x23028451",
+ "13": "0x23024451",
+ "14": "0x23022451",
+ "15": "0x23021451",
+ "16": "0x24028451",
+ "17": "0x24024451",
+ "18": "0x24022451",
+ "19": "0x24021451",
+ "20": "0x25028451",
+ "21": "0x25024451",
+ "22": "0x25022451",
+ "23": "0x25021451",
+ "24": "0x26028451",
+ "25": "0x26024451",
+ "26": "0x26022451",
+ "27": "0x26021451",
+ "28": "0x27028451",
+ "29": "0x27024451",
+ "30": "0x27022451",
+ "31": "0x27021451"
+ }
+ },
+ "THRCTL_HOLD_OUT": {
+ "instances": {
+ "0": "0x20028455",
+ "1": "0x20024455",
+ "2": "0x20022455",
+ "3": "0x20021455",
+ "4": "0x21028455",
+ "5": "0x21024455",
+ "6": "0x21022455",
+ "7": "0x21021455",
+ "8": "0x22028455",
+ "9": "0x22024455",
+ "10": "0x22022455",
+ "11": "0x22021455",
+ "12": "0x23028455",
+ "13": "0x23024455",
+ "14": "0x23022455",
+ "15": "0x23021455",
+ "16": "0x24028455",
+ "17": "0x24024455",
+ "18": "0x24022455",
+ "19": "0x24021455",
+ "20": "0x25028455",
+ "21": "0x25024455",
+ "22": "0x25022455",
+ "23": "0x25021455",
+ "24": "0x26028455",
+ "25": "0x26024455",
+ "26": "0x26022455",
+ "27": "0x26021455",
+ "28": "0x27028455",
+ "29": "0x27024455",
+ "30": "0x27022455",
+ "31": "0x27021455"
+ }
+ },
+ "VSU_HOLD_OUT": {
+ "instances": {
+ "0": "0x200284B6",
+ "1": "0x200244B6",
+ "2": "0x200224B6",
+ "3": "0x200214B6",
+ "4": "0x210284B6",
+ "5": "0x210244B6",
+ "6": "0x210224B6",
+ "7": "0x210214B6",
+ "8": "0x220284B6",
+ "9": "0x220244B6",
+ "10": "0x220224B6",
+ "11": "0x220214B6",
+ "12": "0x230284B6",
+ "13": "0x230244B6",
+ "14": "0x230224B6",
+ "15": "0x230214B6",
+ "16": "0x240284B6",
+ "17": "0x240244B6",
+ "18": "0x240224B6",
+ "19": "0x240214B6",
+ "20": "0x250284B6",
+ "21": "0x250244B6",
+ "22": "0x250224B6",
+ "23": "0x250214B6",
+ "24": "0x260284B6",
+ "25": "0x260244B6",
+ "26": "0x260224B6",
+ "27": "0x260214B6",
+ "28": "0x270284B6",
+ "29": "0x270244B6",
+ "30": "0x270224B6",
+ "31": "0x270214B6"
+ }
+ },
+ "TFAC_HOLD_OUT": {
+ "instances": {
+ "0": "0x200284B7",
+ "1": "0x200244B7",
+ "2": "0x200224B7",
+ "3": "0x200214B7",
+ "4": "0x210284B7",
+ "5": "0x210244B7",
+ "6": "0x210224B7",
+ "7": "0x210214B7",
+ "8": "0x220284B7",
+ "9": "0x220244B7",
+ "10": "0x220224B7",
+ "11": "0x220214B7",
+ "12": "0x230284B7",
+ "13": "0x230244B7",
+ "14": "0x230224B7",
+ "15": "0x230214B7",
+ "16": "0x240284B7",
+ "17": "0x240244B7",
+ "18": "0x240224B7",
+ "19": "0x240214B7",
+ "20": "0x250284B7",
+ "21": "0x250244B7",
+ "22": "0x250224B7",
+ "23": "0x250214B7",
+ "24": "0x260284B7",
+ "25": "0x260244B7",
+ "26": "0x260224B7",
+ "27": "0x260214B7",
+ "28": "0x270284B7",
+ "29": "0x270244B7",
+ "30": "0x270224B7",
+ "31": "0x270214B7"
+ }
+ },
+ "IFU_HOLD_OUT0": {
+ "instances": {
+ "0": "0x20028600",
+ "1": "0x20024600",
+ "2": "0x20022600",
+ "3": "0x20021600",
+ "4": "0x21028600",
+ "5": "0x21024600",
+ "6": "0x21022600",
+ "7": "0x21021600",
+ "8": "0x22028600",
+ "9": "0x22024600",
+ "10": "0x22022600",
+ "11": "0x22021600",
+ "12": "0x23028600",
+ "13": "0x23024600",
+ "14": "0x23022600",
+ "15": "0x23021600",
+ "16": "0x24028600",
+ "17": "0x24024600",
+ "18": "0x24022600",
+ "19": "0x24021600",
+ "20": "0x25028600",
+ "21": "0x25024600",
+ "22": "0x25022600",
+ "23": "0x25021600",
+ "24": "0x26028600",
+ "25": "0x26024600",
+ "26": "0x26022600",
+ "27": "0x26021600",
+ "28": "0x27028600",
+ "29": "0x27024600",
+ "30": "0x27022600",
+ "31": "0x27021600"
+ }
+ },
+ "IFU_HOLD_OUT1": {
+ "instances": {
+ "0": "0x20028601",
+ "1": "0x20024601",
+ "2": "0x20022601",
+ "3": "0x20021601",
+ "4": "0x21028601",
+ "5": "0x21024601",
+ "6": "0x21022601",
+ "7": "0x21021601",
+ "8": "0x22028601",
+ "9": "0x22024601",
+ "10": "0x22022601",
+ "11": "0x22021601",
+ "12": "0x23028601",
+ "13": "0x23024601",
+ "14": "0x23022601",
+ "15": "0x23021601",
+ "16": "0x24028601",
+ "17": "0x24024601",
+ "18": "0x24022601",
+ "19": "0x24021601",
+ "20": "0x25028601",
+ "21": "0x25024601",
+ "22": "0x25022601",
+ "23": "0x25021601",
+ "24": "0x26028601",
+ "25": "0x26024601",
+ "26": "0x26022601",
+ "27": "0x26021601",
+ "28": "0x27028601",
+ "29": "0x27024601",
+ "30": "0x27022601",
+ "31": "0x27021601"
+ }
+ },
+ "IFU_HOLD_OUT2": {
+ "instances": {
+ "0": "0x20028602",
+ "1": "0x20024602",
+ "2": "0x20022602",
+ "3": "0x20021602",
+ "4": "0x21028602",
+ "5": "0x21024602",
+ "6": "0x21022602",
+ "7": "0x21021602",
+ "8": "0x22028602",
+ "9": "0x22024602",
+ "10": "0x22022602",
+ "11": "0x22021602",
+ "12": "0x23028602",
+ "13": "0x23024602",
+ "14": "0x23022602",
+ "15": "0x23021602",
+ "16": "0x24028602",
+ "17": "0x24024602",
+ "18": "0x24022602",
+ "19": "0x24021602",
+ "20": "0x25028602",
+ "21": "0x25024602",
+ "22": "0x25022602",
+ "23": "0x25021602",
+ "24": "0x26028602",
+ "25": "0x26024602",
+ "26": "0x26022602",
+ "27": "0x26021602",
+ "28": "0x27028602",
+ "29": "0x27024602",
+ "30": "0x27022602",
+ "31": "0x27021602"
+ }
+ },
+ "IFU_HOLD_OUT3": {
+ "instances": {
+ "0": "0x20028603",
+ "1": "0x20024603",
+ "2": "0x20022603",
+ "3": "0x20021603",
+ "4": "0x21028603",
+ "5": "0x21024603",
+ "6": "0x21022603",
+ "7": "0x21021603",
+ "8": "0x22028603",
+ "9": "0x22024603",
+ "10": "0x22022603",
+ "11": "0x22021603",
+ "12": "0x23028603",
+ "13": "0x23024603",
+ "14": "0x23022603",
+ "15": "0x23021603",
+ "16": "0x24028603",
+ "17": "0x24024603",
+ "18": "0x24022603",
+ "19": "0x24021603",
+ "20": "0x25028603",
+ "21": "0x25024603",
+ "22": "0x25022603",
+ "23": "0x25021603",
+ "24": "0x26028603",
+ "25": "0x26024603",
+ "26": "0x26022603",
+ "27": "0x26021603",
+ "28": "0x27028603",
+ "29": "0x27024603",
+ "30": "0x27022603",
+ "31": "0x27021603"
+ }
+ },
+ "ISU_HOLD_OUT0": {
+ "instances": {
+ "0": "0x20028640",
+ "1": "0x20024640",
+ "2": "0x20022640",
+ "3": "0x20021640",
+ "4": "0x21028640",
+ "5": "0x21024640",
+ "6": "0x21022640",
+ "7": "0x21021640",
+ "8": "0x22028640",
+ "9": "0x22024640",
+ "10": "0x22022640",
+ "11": "0x22021640",
+ "12": "0x23028640",
+ "13": "0x23024640",
+ "14": "0x23022640",
+ "15": "0x23021640",
+ "16": "0x24028640",
+ "17": "0x24024640",
+ "18": "0x24022640",
+ "19": "0x24021640",
+ "20": "0x25028640",
+ "21": "0x25024640",
+ "22": "0x25022640",
+ "23": "0x25021640",
+ "24": "0x26028640",
+ "25": "0x26024640",
+ "26": "0x26022640",
+ "27": "0x26021640",
+ "28": "0x27028640",
+ "29": "0x27024640",
+ "30": "0x27022640",
+ "31": "0x27021640"
+ }
+ },
+ "ISU_HOLD_OUT1": {
+ "instances": {
+ "0": "0x20028641",
+ "1": "0x20024641",
+ "2": "0x20022641",
+ "3": "0x20021641",
+ "4": "0x21028641",
+ "5": "0x21024641",
+ "6": "0x21022641",
+ "7": "0x21021641",
+ "8": "0x22028641",
+ "9": "0x22024641",
+ "10": "0x22022641",
+ "11": "0x22021641",
+ "12": "0x23028641",
+ "13": "0x23024641",
+ "14": "0x23022641",
+ "15": "0x23021641",
+ "16": "0x24028641",
+ "17": "0x24024641",
+ "18": "0x24022641",
+ "19": "0x24021641",
+ "20": "0x25028641",
+ "21": "0x25024641",
+ "22": "0x25022641",
+ "23": "0x25021641",
+ "24": "0x26028641",
+ "25": "0x26024641",
+ "26": "0x26022641",
+ "27": "0x26021641",
+ "28": "0x27028641",
+ "29": "0x27024641",
+ "30": "0x27022641",
+ "31": "0x27021641"
+ }
+ },
+ "ISU_HOLD_OUT2": {
+ "instances": {
+ "0": "0x20028642",
+ "1": "0x20024642",
+ "2": "0x20022642",
+ "3": "0x20021642",
+ "4": "0x21028642",
+ "5": "0x21024642",
+ "6": "0x21022642",
+ "7": "0x21021642",
+ "8": "0x22028642",
+ "9": "0x22024642",
+ "10": "0x22022642",
+ "11": "0x22021642",
+ "12": "0x23028642",
+ "13": "0x23024642",
+ "14": "0x23022642",
+ "15": "0x23021642",
+ "16": "0x24028642",
+ "17": "0x24024642",
+ "18": "0x24022642",
+ "19": "0x24021642",
+ "20": "0x25028642",
+ "21": "0x25024642",
+ "22": "0x25022642",
+ "23": "0x25021642",
+ "24": "0x26028642",
+ "25": "0x26024642",
+ "26": "0x26022642",
+ "27": "0x26021642",
+ "28": "0x27028642",
+ "29": "0x27024642",
+ "30": "0x27022642",
+ "31": "0x27021642"
+ }
+ },
+ "ISU_HOLD_OUT3": {
+ "instances": {
+ "0": "0x20028643",
+ "1": "0x20024643",
+ "2": "0x20022643",
+ "3": "0x20021643",
+ "4": "0x21028643",
+ "5": "0x21024643",
+ "6": "0x21022643",
+ "7": "0x21021643",
+ "8": "0x22028643",
+ "9": "0x22024643",
+ "10": "0x22022643",
+ "11": "0x22021643",
+ "12": "0x23028643",
+ "13": "0x23024643",
+ "14": "0x23022643",
+ "15": "0x23021643",
+ "16": "0x24028643",
+ "17": "0x24024643",
+ "18": "0x24022643",
+ "19": "0x24021643",
+ "20": "0x25028643",
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+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG13",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_L2_FIR": [
+ {
+ "reg_name": "L2_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "L2_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_L3_FIR": [
+ {
+ "reg_name": "L3_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "L3_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_NCU_FIR": [
+ {
+ "reg_name": "NCU_ERR_RPT_REG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_10/regs_mc.json b/chip_data/p10_10/regs_mc.json
new file mode 100644
index 0000000..bda44bd
--- /dev/null
+++ b/chip_data/p10_10/regs_mc.json
@@ -0,0 +1,883 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "MC_OMI_DL_CONFIG0": {
+ "instances": {
+ "0": "0x0C011410",
+ "1": "0x0C011420",
+ "2": "0x0C011810",
+ "3": "0x0C011820",
+ "4": "0x0D011410",
+ "5": "0x0D011420",
+ "6": "0x0D011810",
+ "7": "0x0D011820",
+ "8": "0x0E011410",
+ "9": "0x0E011420",
+ "10": "0x0E011810",
+ "11": "0x0E011820",
+ "12": "0x0F011410",
+ "13": "0x0F011420",
+ "14": "0x0F011810",
+ "15": "0x0F011820"
+ }
+ },
+ "MC_OMI_DL_CONFIG1": {
+ "instances": {
+ "0": "0x0C011411",
+ "1": "0x0C011421",
+ "2": "0x0C011811",
+ "3": "0x0C011821",
+ "4": "0x0D011411",
+ "5": "0x0D011421",
+ "6": "0x0D011811",
+ "7": "0x0D011821",
+ "8": "0x0E011411",
+ "9": "0x0E011421",
+ "10": "0x0E011811",
+ "11": "0x0E011821",
+ "12": "0x0F011411",
+ "13": "0x0F011421",
+ "14": "0x0F011811",
+ "15": "0x0F011821"
+ }
+ },
+ "MC_OMI_DL_ERR_MASK": {
+ "instances": {
+ "0": "0x0C011412",
+ "1": "0x0C011422",
+ "2": "0x0C011812",
+ "3": "0x0C011822",
+ "4": "0x0D011412",
+ "5": "0x0D011422",
+ "6": "0x0D011812",
+ "7": "0x0D011822",
+ "8": "0x0E011412",
+ "9": "0x0E011422",
+ "10": "0x0E011812",
+ "11": "0x0E011822",
+ "12": "0x0F011412",
+ "13": "0x0F011422",
+ "14": "0x0F011812",
+ "15": "0x0F011822"
+ }
+ },
+ "MC_OMI_DL_ERR_RPT": {
+ "instances": {
+ "0": "0x0C011413",
+ "1": "0x0C011423",
+ "2": "0x0C011813",
+ "3": "0x0C011823",
+ "4": "0x0D011413",
+ "5": "0x0D011423",
+ "6": "0x0D011813",
+ "7": "0x0D011823",
+ "8": "0x0E011413",
+ "9": "0x0E011423",
+ "10": "0x0E011813",
+ "11": "0x0E011823",
+ "12": "0x0F011413",
+ "13": "0x0F011423",
+ "14": "0x0F011813",
+ "15": "0x0F011823"
+ }
+ },
+ "MC_OMI_DL_ERR_CAPTURE": {
+ "instances": {
+ "0": "0x0C011414",
+ "1": "0x0C011424",
+ "2": "0x0C011814",
+ "3": "0x0C011824",
+ "4": "0x0D011414",
+ "5": "0x0D011424",
+ "6": "0x0D011814",
+ "7": "0x0D011824",
+ "8": "0x0E011414",
+ "9": "0x0E011424",
+ "10": "0x0E011814",
+ "11": "0x0E011824",
+ "12": "0x0F011414",
+ "13": "0x0F011424",
+ "14": "0x0F011814",
+ "15": "0x0F011824"
+ }
+ },
+ "MC_OMI_DL_EDPL_MAX_COUNT": {
+ "instances": {
+ "0": "0x0C011415",
+ "1": "0x0C011425",
+ "2": "0x0C011815",
+ "3": "0x0C011825",
+ "4": "0x0D011415",
+ "5": "0x0D011425",
+ "6": "0x0D011815",
+ "7": "0x0D011825",
+ "8": "0x0E011415",
+ "9": "0x0E011425",
+ "10": "0x0E011815",
+ "11": "0x0E011825",
+ "12": "0x0F011415",
+ "13": "0x0F011425",
+ "14": "0x0F011815",
+ "15": "0x0F011825"
+ }
+ },
+ "MC_OMI_DL_STATUS": {
+ "instances": {
+ "0": "0x0C011416",
+ "1": "0x0C011426",
+ "2": "0x0C011816",
+ "3": "0x0C011826",
+ "4": "0x0D011416",
+ "5": "0x0D011426",
+ "6": "0x0D011816",
+ "7": "0x0D011826",
+ "8": "0x0E011416",
+ "9": "0x0E011426",
+ "10": "0x0E011816",
+ "11": "0x0E011826",
+ "12": "0x0F011416",
+ "13": "0x0F011426",
+ "14": "0x0F011816",
+ "15": "0x0F011826"
+ }
+ },
+ "MC_OMI_DL_TRAINING_STATUS": {
+ "instances": {
+ "0": "0x0C011417",
+ "1": "0x0C011427",
+ "2": "0x0C011817",
+ "3": "0x0C011827",
+ "4": "0x0D011417",
+ "5": "0x0D011427",
+ "6": "0x0D011817",
+ "7": "0x0D011827",
+ "8": "0x0E011417",
+ "9": "0x0E011427",
+ "10": "0x0E011817",
+ "11": "0x0E011827",
+ "12": "0x0F011417",
+ "13": "0x0F011427",
+ "14": "0x0F011817",
+ "15": "0x0F011827"
+ }
+ },
+ "MC_OMI_DL_DLX_CONFIG": {
+ "instances": {
+ "0": "0x0C011418",
+ "1": "0x0C011428",
+ "2": "0x0C011818",
+ "3": "0x0C011828",
+ "4": "0x0D011418",
+ "5": "0x0D011428",
+ "6": "0x0D011818",
+ "7": "0x0D011828",
+ "8": "0x0E011418",
+ "9": "0x0E011428",
+ "10": "0x0E011818",
+ "11": "0x0E011828",
+ "12": "0x0F011418",
+ "13": "0x0F011428",
+ "14": "0x0F011818",
+ "15": "0x0F011828"
+ }
+ },
+ "MC_OMI_DL_DLX_INFO": {
+ "instances": {
+ "0": "0x0C011419",
+ "1": "0x0C011429",
+ "2": "0x0C011819",
+ "3": "0x0C011829",
+ "4": "0x0D011419",
+ "5": "0x0D011429",
+ "6": "0x0D011819",
+ "7": "0x0D011829",
+ "8": "0x0E011419",
+ "9": "0x0E011429",
+ "10": "0x0E011819",
+ "11": "0x0E011829",
+ "12": "0x0F011419",
+ "13": "0x0F011429",
+ "14": "0x0F011819",
+ "15": "0x0F011829"
+ }
+ },
+ "MC_OMI_DL_ERR_ACTION": {
+ "instances": {
+ "0": "0x0C01141D",
+ "1": "0x0C01142D",
+ "2": "0x0C01181D",
+ "3": "0x0C01182D",
+ "4": "0x0D01141D",
+ "5": "0x0D01142D",
+ "6": "0x0D01181D",
+ "7": "0x0D01182D",
+ "8": "0x0E01141D",
+ "9": "0x0E01142D",
+ "10": "0x0E01181D",
+ "11": "0x0E01182D",
+ "12": "0x0F01141D",
+ "13": "0x0F01142D",
+ "14": "0x0F01181D",
+ "15": "0x0F01182D"
+ }
+ },
+ "MC_OMI_DL_DEBUG_AID": {
+ "instances": {
+ "0": "0x0C01141E",
+ "1": "0x0C01142E",
+ "2": "0x0C01181E",
+ "3": "0x0C01182E",
+ "4": "0x0D01141E",
+ "5": "0x0D01142E",
+ "6": "0x0D01181E",
+ "7": "0x0D01182E",
+ "8": "0x0E01141E",
+ "9": "0x0E01142E",
+ "10": "0x0E01181E",
+ "11": "0x0E01182E",
+ "12": "0x0F01141E",
+ "13": "0x0F01142E",
+ "14": "0x0F01181E",
+ "15": "0x0F01182E"
+ }
+ },
+ "MC_OMI_DL_CYA_BITS": {
+ "instances": {
+ "0": "0x0C01141F",
+ "1": "0x0C01142F",
+ "2": "0x0C01181F",
+ "3": "0x0C01182F",
+ "4": "0x0D01141F",
+ "5": "0x0D01142F",
+ "6": "0x0D01181F",
+ "7": "0x0D01182F",
+ "8": "0x0E01141F",
+ "9": "0x0E01142F",
+ "10": "0x0E01181F",
+ "11": "0x0E01182F",
+ "12": "0x0F01141F",
+ "13": "0x0F01142F",
+ "14": "0x0F01181F",
+ "15": "0x0F01182F"
+ }
+ },
+ "MC_DSTL_ERR_RPT": {
+ "instances": {
+ "0": "0x0C010D0C",
+ "1": "0x0C010D4C",
+ "2": "0x0D010D0C",
+ "3": "0x0D010D4C",
+ "4": "0x0E010D0C",
+ "5": "0x0E010D4C",
+ "6": "0x0F010D0C",
+ "7": "0x0F010D4C"
+ }
+ },
+ "MC_DSTL_CFG2": {
+ "instances": {
+ "0": "0x0C010D0E",
+ "1": "0x0C010D4E",
+ "2": "0x0D010D0E",
+ "3": "0x0D010D4E",
+ "4": "0x0E010D0E",
+ "5": "0x0E010D4E",
+ "6": "0x0F010D0E",
+ "7": "0x0F010D4E"
+ }
+ },
+ "MC_ERR_RPT0": {
+ "instances": {
+ "0": "0x0C010C1E",
+ "1": "0x0D010C1E",
+ "2": "0x0E010C1E",
+ "3": "0x0F010C1E"
+ }
+ },
+ "MC_ERR_RPT1": {
+ "instances": {
+ "0": "0x0C010C1F",
+ "1": "0x0D010C1F",
+ "2": "0x0E010C1F",
+ "3": "0x0F010C1F"
+ }
+ },
+ "MC_ERR_RPT2": {
+ "instances": {
+ "0": "0x0C010C1A",
+ "1": "0x0D010C1A",
+ "2": "0x0E010C1A",
+ "3": "0x0F010C1A"
+ }
+ },
+ "MC_MISC_ERR_RPT": {
+ "instances": {
+ "0": "0x0C010FE7",
+ "1": "0x0D010FE7",
+ "2": "0x0E010FE7",
+ "3": "0x0F010FE7"
+ }
+ },
+ "CMN_CONFIG": {
+ "instances": {
+ "0": "0x0C01140E",
+ "1": "0x0C01180E",
+ "2": "0x0D01140E",
+ "3": "0x0D01180E",
+ "4": "0x0E01140E",
+ "5": "0x0E01180E",
+ "6": "0x0F01140E",
+ "7": "0x0F01180E"
+ }
+ },
+ "PMU_CNTR": {
+ "instances": {
+ "0": "0x0C01140F",
+ "1": "0x0C01180F",
+ "2": "0x0D01140F",
+ "3": "0x0D01180F",
+ "4": "0x0E01140F",
+ "5": "0x0E01180F",
+ "6": "0x0F01140F",
+ "7": "0x0F01180F"
+ }
+ },
+ "MC_USTL_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0C010E0E",
+ "1": "0x0C010E4E",
+ "2": "0x0D010E0E",
+ "3": "0x0D010E4E",
+ "4": "0x0E010E0E",
+ "5": "0x0E010E4E",
+ "6": "0x0F010E0E",
+ "7": "0x0F010E4E"
+ }
+ },
+ "MC_USTL_LOL_DROP": {
+ "instances": {
+ "0": "0x0C010E11",
+ "1": "0x0C010E51",
+ "2": "0x0D010E11",
+ "3": "0x0D010E51",
+ "4": "0x0E010E11",
+ "5": "0x0E010E51",
+ "6": "0x0F010E11",
+ "7": "0x0F010E51"
+ }
+ },
+ "MC_USTL_LOL_MASK": {
+ "instances": {
+ "0": "0x0C010E12",
+ "1": "0x0C010E52",
+ "2": "0x0D010E12",
+ "3": "0x0D010E52",
+ "4": "0x0E010E12",
+ "5": "0x0E010E52",
+ "6": "0x0F010E12",
+ "7": "0x0F010E52"
+ }
+ },
+ "MC_USTL_FAIL_MASK": {
+ "instances": {
+ "0": "0x0C010E13",
+ "1": "0x0C010E53",
+ "2": "0x0D010E13",
+ "3": "0x0D010E53",
+ "4": "0x0E010E13",
+ "5": "0x0E010E53",
+ "6": "0x0F010E13",
+ "7": "0x0F010E53"
+ }
+ },
+ "MC_USTL_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0C010E16",
+ "1": "0x0C010E56",
+ "2": "0x0D010E16",
+ "3": "0x0D010E56",
+ "4": "0x0E010E16",
+ "5": "0x0E010E56",
+ "6": "0x0F010E16",
+ "7": "0x0F010E56"
+ }
+ }
+ },
+ "capture_groups": {
+ "MC_OMI_DL_FIR": [
+ {
+ "reg_name": "MC_OMI_DL_CONFIG0",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG0",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG1",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG1",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_MASK",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_RPT",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_CAPTURE",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_STATUS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_CONFIG",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_INFO",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_ACTION",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_ACTION",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DEBUG_AID",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DEBUG_AID",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CYA_BITS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CYA_BITS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ }
+ ],
+ "MC_DSTL_FIR": [
+ {
+ "reg_name": "MC_DSTL_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_DSTL_CFG2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ],
+ "MC_FIR": [
+ {
+ "reg_name": "MC_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "MC_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "MC_ERR_RPT2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "MC_MISC_FIR": [
+ {
+ "reg_name": "MC_MISC_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "MC_USTL_FIR": [
+ {
+ "reg_name": "MC_USTL_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_LOL_DROP",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_LOL_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_FAIL_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_10/regs_other.json b/chip_data/p10_10/regs_other.json
new file mode 100644
index 0000000..1c89b17
--- /dev/null
+++ b/chip_data/p10_10/regs_other.json
@@ -0,0 +1,756 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "HCA_ERR_RPT_HOLD_REG": {
+ "instances": {
+ "0": "0x03011D56"
+ }
+ },
+ "INT_CQ_ERR_RPT_HOLD": {
+ "instances": {
+ "0": "0x02010839"
+ }
+ },
+ "INT_CQ_ERR_INFO1": {
+ "instances": {
+ "0": "0x0201083B"
+ }
+ },
+ "INT_CQ_ERR_INFO2": {
+ "instances": {
+ "0": "0x0201083C"
+ }
+ },
+ "INT_CQ_ERR_INFO3": {
+ "instances": {
+ "0": "0x0201083D"
+ }
+ },
+ "INT_PC_ERR0_WOF": {
+ "instances": {
+ "0": "0x02010AC2"
+ }
+ },
+ "INT_PC_ERR0_WOF_DETAIL": {
+ "instances": {
+ "0": "0x02010AC3"
+ }
+ },
+ "INT_PC_ERR0_FATAL": {
+ "instances": {
+ "0": "0x02010AC4"
+ }
+ },
+ "INT_PC_ERR0_RECOV": {
+ "instances": {
+ "0": "0x02010AC5"
+ }
+ },
+ "INT_PC_ERR0_INFO": {
+ "instances": {
+ "0": "0x02010AC6"
+ }
+ },
+ "INT_PC_ERR1_WOF": {
+ "instances": {
+ "0": "0x02010ACA"
+ }
+ },
+ "INT_PC_ERR1_WOF_DETAIL": {
+ "instances": {
+ "0": "0x02010ACB"
+ }
+ },
+ "INT_PC_ERR1_FATAL": {
+ "instances": {
+ "0": "0x02010ACC"
+ }
+ },
+ "INT_PC_ERR1_RECOV": {
+ "instances": {
+ "0": "0x02010ACD"
+ }
+ },
+ "INT_PC_ERR1_INFO": {
+ "instances": {
+ "0": "0x02010ACE"
+ }
+ },
+ "INT_PC_NXC_WOF_ERR": {
+ "instances": {
+ "0": "0x02010AD2"
+ }
+ },
+ "INT_PC_NXC_WOF_ERR_DETAIL": {
+ "instances": {
+ "0": "0x02010AD3"
+ }
+ },
+ "INT_PC_NXC_FATAL_ERR": {
+ "instances": {
+ "0": "0x02010AD4"
+ }
+ },
+ "INT_PC_NXC_RECOV_ERR": {
+ "instances": {
+ "0": "0x02010AD5"
+ }
+ },
+ "INT_PC_NXC_INFO_ERR": {
+ "instances": {
+ "0": "0x02010AD6"
+ }
+ },
+ "INT_VC_WOF_ERR_G0": {
+ "instances": {
+ "0": "0x020109C2"
+ }
+ },
+ "INT_VC_WOF_ERR_G0_DETAIL": {
+ "instances": {
+ "0": "0x020109C3"
+ }
+ },
+ "INT_VC_FATAL_ERR_G0": {
+ "instances": {
+ "0": "0x020109C4"
+ }
+ },
+ "INT_VC_RECOV_ERR_G0": {
+ "instances": {
+ "0": "0x020109C5"
+ }
+ },
+ "INT_VC_INFO_ERR_G0": {
+ "instances": {
+ "0": "0x020109C6"
+ }
+ },
+ "INT_VC_WOF_ERR_G1": {
+ "instances": {
+ "0": "0x020109CA"
+ }
+ },
+ "INT_VC_WOF_ERR_G1_DETAIL": {
+ "instances": {
+ "0": "0x020109CB"
+ }
+ },
+ "INT_VC_FATAL_ERR_G1": {
+ "instances": {
+ "0": "0x020109CC"
+ }
+ },
+ "INT_VC_RECOV_ERR_G1": {
+ "instances": {
+ "0": "0x020109CD"
+ }
+ },
+ "INT_VC_INFO_ERR_G1": {
+ "instances": {
+ "0": "0x020109CE"
+ }
+ },
+ "NMMU_CQ_ERR_RPT_0": {
+ "instances": {
+ "0": "0x02010C22",
+ "1": "0x03010C22"
+ }
+ },
+ "NX_CQ_ERR_RPT_0": {
+ "instances": {
+ "0": "0x020110A2"
+ }
+ },
+ "NX_CQ_ERR_RPT_1": {
+ "instances": {
+ "0": "0x020110A1"
+ }
+ },
+ "SU_DMA_ERROR_REPORT_0": {
+ "instances": {
+ "0": "0x02011057"
+ }
+ },
+ "SU_DMA_ERROR_REPORT_1": {
+ "instances": {
+ "0": "0x02011058"
+ }
+ },
+ "OCC_SCOM_ERR_RPT": {
+ "instances": {
+ "0": "0x0101080A"
+ }
+ },
+ "OCC_SCOM_ERR_RPT2": {
+ "instances": {
+ "0": "0x0101080B"
+ }
+ },
+ "PB_TL_LINK_SYN_01": {
+ "instances": {
+ "0": "0x10011812",
+ "1": "0x11011812",
+ "2": "0x12011812",
+ "3": "0x13011812"
+ }
+ },
+ "PB_TL_LINK_SYN_23": {
+ "instances": {
+ "0": "0x10011813",
+ "1": "0x11011813",
+ "2": "0x12011813",
+ "3": "0x13011813"
+ }
+ },
+ "PB_EN_DOB_ECC_ERR": {
+ "instances": {
+ "0": "0x10011818",
+ "1": "0x11011818",
+ "2": "0x12011818",
+ "3": "0x13011818"
+ }
+ },
+ "PB_MISC_CFG": {
+ "instances": {
+ "0": "0x10011825",
+ "1": "0x11011825",
+ "2": "0x12011825",
+ "3": "0x13011825"
+ }
+ },
+ "PB_STATION_MODE_EN1": {
+ "instances": {
+ "0": "0x0301120A"
+ }
+ },
+ "PB_STATION_MODE_EN2": {
+ "instances": {
+ "0": "0x0301124A"
+ }
+ },
+ "PB_STATION_MODE_EN3": {
+ "instances": {
+ "0": "0x0301128A"
+ }
+ },
+ "PB_STATION_MODE_EN4": {
+ "instances": {
+ "0": "0x030112CA"
+ }
+ },
+ "PB_STATION_MODE_EQ": {
+ "instances": {
+ "0": "0x0301100A",
+ "1": "0x0301104A",
+ "2": "0x0301108A",
+ "3": "0x030110CA",
+ "4": "0x0301110A",
+ "5": "0x0301114A",
+ "6": "0x0301118A",
+ "7": "0x030111CA"
+ }
+ },
+ "PB_STATION_MODE_ES1": {
+ "instances": {
+ "0": "0x0301130A"
+ }
+ },
+ "PB_STATION_MODE_ES2": {
+ "instances": {
+ "0": "0x0301134A"
+ }
+ },
+ "PB_STATION_MODE_ES3": {
+ "instances": {
+ "0": "0x0301138A"
+ }
+ },
+ "PB_STATION_MODE_ES4": {
+ "instances": {
+ "0": "0x030113CA"
+ }
+ },
+ "PBA_ERR_RPT0": {
+ "instances": {
+ "0": "0x03011DCC"
+ }
+ },
+ "PBA_ERR_RPT1": {
+ "instances": {
+ "0": "0x03011DCD"
+ }
+ },
+ "PBA_ERR_RPT2": {
+ "instances": {
+ "0": "0x03011DCE"
+ }
+ },
+ "PBAO_ERR_RPT_1": {
+ "instances": {
+ "0": "0x01010CCD"
+ }
+ },
+ "PBAO_ERR_RPT_2": {
+ "instances": {
+ "0": "0x01010CCE"
+ }
+ },
+ "PBAIB_CERR_RPT_REG": {
+ "instances": {
+ "0": "0x0801084B",
+ "1": "0x0801088B",
+ "2": "0x080108CB",
+ "3": "0x0901084B",
+ "4": "0x0901088B",
+ "5": "0x090108CB"
+ }
+ },
+ "PCI_NFIR_ERR_RPT0": {
+ "instances": {
+ "0": "0x0301184A",
+ "1": "0x0301188A",
+ "2": "0x030118CA",
+ "3": "0x0201184A",
+ "4": "0x0201188A",
+ "5": "0x020118CA"
+ }
+ },
+ "PCI_NFIR_ERR_RPT1": {
+ "instances": {
+ "0": "0x0301184B",
+ "1": "0x0301188B",
+ "2": "0x030118CB",
+ "3": "0x0201184B",
+ "4": "0x0201188B",
+ "5": "0x020118CB"
+ }
+ }
+ },
+ "capture_groups": {
+ "HCA_FIR": [
+ {
+ "reg_name": "HCA_ERR_RPT_HOLD_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "INT_CQ_FIR": [
+ {
+ "reg_name": "INT_CQ_ERR_RPT_HOLD",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_WOF",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_WOF_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_FATAL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_RECOV",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_WOF",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_WOF_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_FATAL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_RECOV",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_WOF_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_WOF_ERR_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_FATAL_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_RECOV_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_INFO_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G0_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_FATAL_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_RECOV_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_INFO_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G1_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_FATAL_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_RECOV_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_INFO_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "NMMU_CQ_FIR": [
+ {
+ "reg_name": "NMMU_CQ_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ],
+ "NX_CQ_FIR": [
+ {
+ "reg_name": "NX_CQ_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "NX_CQ_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "NX_DMA_ENG_FIR": [
+ {
+ "reg_name": "SU_DMA_ERROR_REPORT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SU_DMA_ERROR_REPORT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "OCC_FIR": [
+ {
+ "reg_name": "OCC_SCOM_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OCC_SCOM_ERR_RPT2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PAU_PTL_FIR": [
+ {
+ "reg_name": "PB_TL_LINK_SYN_01",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_TL_LINK_SYN_23",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_EN_DOB_ECC_ERR",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_MISC_CFG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN1": [
+ {
+ "reg_name": "PB_STATION_MODE_EN1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN2": [
+ {
+ "reg_name": "PB_STATION_MODE_EN2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN3": [
+ {
+ "reg_name": "PB_STATION_MODE_EN3",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN4": [
+ {
+ "reg_name": "PB_STATION_MODE_EN4",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EQ": [
+ {
+ "reg_name": "PB_STATION_MODE_EQ",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES1": [
+ {
+ "reg_name": "PB_STATION_MODE_ES1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES2": [
+ {
+ "reg_name": "PB_STATION_MODE_ES2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES3": [
+ {
+ "reg_name": "PB_STATION_MODE_ES3",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES4": [
+ {
+ "reg_name": "PB_STATION_MODE_ES4",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PBAF_FIR": [
+ {
+ "reg_name": "PBA_ERR_RPT0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBA_ERR_RPT1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBA_ERR_RPT2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PBAO_FIR": [
+ {
+ "reg_name": "PBAO_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBAO_ERR_RPT_2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PCI_FIR": [
+ {
+ "reg_name": "PBAIB_CERR_RPT_REG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ],
+ "PCI_NEST_FIR": [
+ {
+ "reg_name": "PCI_NFIR_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ },
+ {
+ "reg_name": "PCI_NFIR_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_10/tod_error.json b/chip_data/p10_10/tod_error.json
new file mode 100644
index 0000000..323ac9f
--- /dev/null
+++ b/chip_data/p10_10/tod_error.json
@@ -0,0 +1,599 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "TOD_M_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040000"
+ }
+ },
+ "TOD_PRI_PORT_0_CTRL": {
+ "instances": {
+ "0": "0x00040001"
+ }
+ },
+ "TOD_PRI_PORT_1_CTRL": {
+ "instances": {
+ "0": "0x00040002"
+ }
+ },
+ "TOD_SEC_PORT_0_CTRL": {
+ "instances": {
+ "0": "0x00040003"
+ }
+ },
+ "TOD_SEC_PORT_1_CTRL": {
+ "instances": {
+ "0": "0x00040004"
+ }
+ },
+ "TOD_S_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040005"
+ }
+ },
+ "TOD_I_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040006"
+ }
+ },
+ "TOD_PSS_MSS_CTRL": {
+ "instances": {
+ "0": "0x00040007"
+ }
+ },
+ "TOD_PSS_MSS_STATUS": {
+ "instances": {
+ "0": "0x00040008"
+ }
+ },
+ "TOD_M_PATH_STATUS": {
+ "instances": {
+ "0": "0x00040009"
+ }
+ },
+ "TOD_S_PATH_STATUS": {
+ "instances": {
+ "0": "0x0004000A"
+ }
+ },
+ "TOD_M_PATH_0_STEP_STEER": {
+ "instances": {
+ "0": "0x0004000E"
+ }
+ },
+ "TOD_M_PATH_1_STEP_STEER": {
+ "instances": {
+ "0": "0x0004000F"
+ }
+ },
+ "TOD_CHIP_CTRL": {
+ "instances": {
+ "0": "0x00040010"
+ }
+ },
+ "TOD_TRACE_DATA_1": {
+ "instances": {
+ "0": "0x0004001D"
+ }
+ },
+ "TOD_TRACE_DATA_2": {
+ "instances": {
+ "0": "0x0004001E"
+ }
+ },
+ "TOD_TRACE_DATA_3": {
+ "instances": {
+ "0": "0x0004001F"
+ }
+ },
+ "TOD_FSM": {
+ "instances": {
+ "0": "0x00040024"
+ }
+ },
+ "TOD_TX_TTYPE_CTRL": {
+ "instances": {
+ "0": "0x00040027"
+ }
+ },
+ "TOD_RX_TTYPE_CTRL": {
+ "instances": {
+ "0": "0x00040029"
+ }
+ },
+ "TOD_ERROR": {
+ "instances": {
+ "0": "0x00040030"
+ }
+ },
+ "TOD_ERROR_MASK": {
+ "instances": {
+ "0": "0x00040032"
+ }
+ },
+ "TOD_ERROR_ROUTING": {
+ "instances": {
+ "0": "0x00040033"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TOD_ERROR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "M_PATH_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "1": {
+ "desc": "M_PATH_0_PARITY_ERROR"
+ },
+ "2": {
+ "desc": "M_PATH_1_PARITY_ERROR"
+ },
+ "3": {
+ "desc": "PCRP0_DATA_PARITY_ERROR"
+ },
+ "4": {
+ "desc": "PCRP1_DATA_PARITY_ERROR"
+ },
+ "5": {
+ "desc": "SCRP0_DATA_PARITY_ERROR"
+ },
+ "6": {
+ "desc": "SCRP1_DATA_PARITY_ERROR"
+ },
+ "7": {
+ "desc": "SPCR_DATA_PARITY_ERROR"
+ },
+ "8": {
+ "desc": "IPCR_DATA_PARITY_ERROR"
+ },
+ "9": {
+ "desc": "PSMSCR_DATA_PARITY_ERROR"
+ },
+ "10": {
+ "desc": "S_PATH_0_PARITY_ERROr"
+ },
+ "11": {
+ "desc": "REG_0X08_DATA_PARITY_ERROR"
+ },
+ "12": {
+ "desc": "M_PATH_STATUS_REG_DATA_PARITY_ERROR"
+ },
+ "13": {
+ "desc": "S_PATH_STATUS_REG_DATA_PARITY_ERROR"
+ },
+ "14": {
+ "desc": "M_PATH_0_STEP_CHECK_ERROR"
+ },
+ "15": {
+ "desc": "M_PATH_1_STEP_CHECK_ERROR"
+ },
+ "16": {
+ "desc": "S_PATH_0_STEP_CHECK_ERROR"
+ },
+ "17": {
+ "desc": "I_PATH_STEP_CHECK_ERROR"
+ },
+ "18": {
+ "desc": "PSS HAMMING DISTANCE"
+ },
+ "19": {
+ "desc": "MISC_RESET_REG_DATA_PARITY_ERROR"
+ },
+ "20": {
+ "desc": "S_PATH_0_PARITY_ERROR"
+ },
+ "21": {
+ "desc": "S_PATH_1_STEP_CHECK_ERROR"
+ },
+ "22": {
+ "desc": "I_PATH_DELAY_STEP_CHECK_PARITY_ERROR"
+ },
+ "23": {
+ "desc": "REG_0X0C DATA_PARITY ERROR"
+ },
+ "24": {
+ "desc": "REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR"
+ },
+ "25": {
+ "desc": "REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR"
+ },
+ "26": {
+ "desc": "REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR"
+ },
+ "27": {
+ "desc": "TIMER_VALUE_REG_DATA_PARITY_ERROR"
+ },
+ "28": {
+ "desc": "LOW_ORDER_STEP_REG_DATA_PARITY_ERROR"
+ },
+ "29": {
+ "desc": "FSM_REG_DATA_PARITY_ERROR"
+ },
+ "30": {
+ "desc": "RX_TTYPE_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "31": {
+ "desc": "REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR"
+ },
+ "32": {
+ "desc": "CHIP_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "33": {
+ "desc": "I_PATH_SYNC_CHECK_ERROR"
+ },
+ "34": {
+ "desc": "I_PATH_FSM_STATE_PARITY_ERROR"
+ },
+ "35": {
+ "desc": "I_PATH_TIME_REG_PARITY_ERROR"
+ },
+ "36": {
+ "desc": "I_PATH_TIME_REG_OVERFLOW"
+ },
+ "37": {
+ "desc": "WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR"
+ },
+ "38": {
+ "desc": "RX_TTYPE_1"
+ },
+ "39": {
+ "desc": "RX_TTYPE_1"
+ },
+ "40": {
+ "desc": "RX_TTYPE_1"
+ },
+ "41": {
+ "desc": "RX_TTYPE_1"
+ },
+ "42": {
+ "desc": "RX_TTYPE_1"
+ },
+ "43": {
+ "desc": "RX_TTYPE_1"
+ },
+ "44": {
+ "desc": "PIB_SLAVE_ADDR_INVALID_ERROR"
+ },
+ "45": {
+ "desc": "PIB_SLAVE_WRITE_INVALID_ERROR"
+ },
+ "46": {
+ "desc": "PIB_SLAVE_READ_INVALID_ERROR"
+ },
+ "47": {
+ "desc": "PIB_SLAVE_ADDR_PARITY_ERROR"
+ },
+ "48": {
+ "desc": "PIB_SLAVE_DATA_PARITY_ERROR"
+ },
+ "49": {
+ "desc": "TTYPE_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "50": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "51": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "52": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "53": {
+ "desc": "RX_TTYPE_INVALID_ERROR"
+ },
+ "54": {
+ "desc": "RX_TTYPE_4_DATA_PARITY_ERROR"
+ },
+ "55": {
+ "desc": "PIB_MASTER_REQUEST_ERROR"
+ },
+ "56": {
+ "desc": "PIB_RESET_DURING_PIB_ACCESS_ERROR"
+ },
+ "57": {
+ "desc": "EXTERNAL_XSTOP_ERROR"
+ },
+ "58": {
+ "desc": "SPARE_ERROR"
+ },
+ "59": {
+ "desc": "SPARE_ERROR"
+ },
+ "60": {
+ "desc": "SPARE_ERROR"
+ },
+ "61": {
+ "desc": "SPARE_ERROR"
+ },
+ "62": {
+ "desc": "SPARE_ERROR"
+ },
+ "63": {
+ "desc": "SPARE_ERROR"
+ }
+ }
+ }
+ },
+ "capture_groups": {
+ "TOD_ERROR": [
+ {
+ "reg_name": "TOD_M_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PRI_PORT_0_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PRI_PORT_1_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_SEC_PORT_0_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_SEC_PORT_1_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_S_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_I_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PSS_MSS_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PSS_MSS_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_S_PATH_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_0_STEP_STEER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_1_STEP_STEER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_CHIP_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_FSM",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TX_TTYPE_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_RX_TTYPE_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR_ROUTING",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/eq_spattn.json b/chip_data/p10_20/eq_spattn.json
new file mode 100644
index 0000000..848cca6
--- /dev/null
+++ b/chip_data/p10_20/eq_spattn.json
@@ -0,0 +1,502 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CORE_THREAD_STATE": {
+ "instances": {
+ "0": "0x20028412",
+ "1": "0x20024412",
+ "2": "0x20022412",
+ "3": "0x20021412",
+ "4": "0x21028412",
+ "5": "0x21024412",
+ "6": "0x21022412",
+ "7": "0x21021412",
+ "8": "0x22028412",
+ "9": "0x22024412",
+ "10": "0x22022412",
+ "11": "0x22021412",
+ "12": "0x23028412",
+ "13": "0x23024412",
+ "14": "0x23022412",
+ "15": "0x23021412",
+ "16": "0x24028412",
+ "17": "0x24024412",
+ "18": "0x24022412",
+ "19": "0x24021412",
+ "20": "0x25028412",
+ "21": "0x25024412",
+ "22": "0x25022412",
+ "23": "0x25021412",
+ "24": "0x26028412",
+ "25": "0x26024412",
+ "26": "0x26022412",
+ "27": "0x26021412",
+ "28": "0x27028412",
+ "29": "0x27024412",
+ "30": "0x27022412",
+ "31": "0x27021412"
+ }
+ },
+ "EQ_SPATTN": {
+ "instances": {
+ "0": "0x20028499",
+ "1": "0x20024499",
+ "2": "0x20022499",
+ "3": "0x20021499",
+ "4": "0x21028499",
+ "5": "0x21024499",
+ "6": "0x21022499",
+ "7": "0x21021499",
+ "8": "0x22028499",
+ "9": "0x22024499",
+ "10": "0x22022499",
+ "11": "0x22021499",
+ "12": "0x23028499",
+ "13": "0x23024499",
+ "14": "0x23022499",
+ "15": "0x23021499",
+ "16": "0x24028499",
+ "17": "0x24024499",
+ "18": "0x24022499",
+ "19": "0x24021499",
+ "20": "0x25028499",
+ "21": "0x25024499",
+ "22": "0x25022499",
+ "23": "0x25021499",
+ "24": "0x26028499",
+ "25": "0x26024499",
+ "26": "0x26022499",
+ "27": "0x26021499",
+ "28": "0x27028499",
+ "29": "0x27024499",
+ "30": "0x27022499",
+ "31": "0x27021499"
+ }
+ },
+ "EQ_SPATTN_MASK": {
+ "instances": {
+ "0": "0x2002849A",
+ "1": "0x2002449A",
+ "2": "0x2002249A",
+ "3": "0x2002149A",
+ "4": "0x2102849A",
+ "5": "0x2102449A",
+ "6": "0x2102249A",
+ "7": "0x2102149A",
+ "8": "0x2202849A",
+ "9": "0x2202449A",
+ "10": "0x2202249A",
+ "11": "0x2202149A",
+ "12": "0x2302849A",
+ "13": "0x2302449A",
+ "14": "0x2302249A",
+ "15": "0x2302149A",
+ "16": "0x2402849A",
+ "17": "0x2402449A",
+ "18": "0x2402249A",
+ "19": "0x2402149A",
+ "20": "0x2502849A",
+ "21": "0x2502449A",
+ "22": "0x2502249A",
+ "23": "0x2502149A",
+ "24": "0x2602849A",
+ "25": "0x2602449A",
+ "26": "0x2602249A",
+ "27": "0x2602149A",
+ "28": "0x2702849A",
+ "29": "0x2702449A",
+ "30": "0x2702249A",
+ "31": "0x2702149A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_CORE_THREAD_STATE": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CORE_THREAD_STATE"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000001"
+ }
+ ]
+ },
+ "shift_value": 63
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CORE_THREAD_STATE"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000001"
+ }
+ ]
+ },
+ "shift_value": 62
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "EQ_SPATTN normal core mode",
+ "child_node": {
+ "name": "EQ_SPATTN_NORMAL",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ },
+ "1": {
+ "desc": "EQ_SPATTN fused core mode",
+ "child_node": {
+ "name": "EQ_SPATTN_FUSED",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ }
+ }
+ },
+ "EQ_SPATTN_NORMAL": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0xFFFF000000000000"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "lt0_spr_instr_stop"
+ },
+ "1": {
+ "desc": "lt0_attn_complete"
+ },
+ "2": {
+ "desc": "lt0_core_checkstop_recovery_handshake"
+ },
+ "3": {
+ "desc": "lt0_core_code_to_sp"
+ },
+ "4": {
+ "desc": "lt1_spr_instr_stop"
+ },
+ "5": {
+ "desc": "lt1_attn_complete"
+ },
+ "6": {
+ "desc": "lt1_core_checkstop_recovery_handshake"
+ },
+ "7": {
+ "desc": "lt1_core_code_to_sp"
+ },
+ "8": {
+ "desc": "lt2_spr_instr_stop"
+ },
+ "9": {
+ "desc": "lt2_attn_complete"
+ },
+ "10": {
+ "desc": "lt2_core_checkstop_recovery_handshake"
+ },
+ "11": {
+ "desc": "lt2_core_code_to_sp"
+ },
+ "12": {
+ "desc": "lt3_spr_instr_stop"
+ },
+ "13": {
+ "desc": "lt3_attn_complete"
+ },
+ "14": {
+ "desc": "lt3_core_checkstop_recovery_handshake"
+ },
+ "15": {
+ "desc": "lt3_core_code_to_sp"
+ }
+ }
+ },
+ "EQ_SPATTN_FUSED": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28,
+ 30
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0xF0F0F0F000000000"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29,
+ 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_SPATTN_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0F0F0F0F00000000"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "lt0_spr_instr_stop"
+ },
+ "1": {
+ "desc": "lt0_attn_complete"
+ },
+ "2": {
+ "desc": "lt0_core_checkstop_recovery_handshake"
+ },
+ "3": {
+ "desc": "lt0_core_code_to_sp"
+ },
+ "4": {
+ "desc": "lt1_spr_instr_stop"
+ },
+ "5": {
+ "desc": "lt1_attn_complete"
+ },
+ "6": {
+ "desc": "lt1_core_checkstop_recovery_handshake"
+ },
+ "7": {
+ "desc": "lt1_core_code_to_sp"
+ },
+ "8": {
+ "desc": "lt2_spr_instr_stop"
+ },
+ "9": {
+ "desc": "lt2_attn_complete"
+ },
+ "10": {
+ "desc": "lt2_core_checkstop_recovery_handshake"
+ },
+ "11": {
+ "desc": "lt2_core_code_to_sp"
+ },
+ "12": {
+ "desc": "lt3_spr_instr_stop"
+ },
+ "13": {
+ "desc": "lt3_attn_complete"
+ },
+ "14": {
+ "desc": "lt3_core_checkstop_recovery_handshake"
+ },
+ "15": {
+ "desc": "lt3_core_code_to_sp"
+ },
+ "16": {
+ "desc": "lt4_spr_instr_stop"
+ },
+ "17": {
+ "desc": "lt4_attn_complete"
+ },
+ "18": {
+ "desc": "lt4_core_checkstop_recovery_handshake"
+ },
+ "19": {
+ "desc": "lt4_core_code_to_sp"
+ },
+ "20": {
+ "desc": "lt5_spr_instr_stop"
+ },
+ "21": {
+ "desc": "lt5_attn_complete"
+ },
+ "22": {
+ "desc": "lt5_core_checkstop_recovery_handshake"
+ },
+ "23": {
+ "desc": "lt5_core_code_to_sp"
+ },
+ "24": {
+ "desc": "lt6_spr_instr_stop"
+ },
+ "25": {
+ "desc": "lt6_attn_complete"
+ },
+ "26": {
+ "desc": "lt6_core_checkstop_recovery_handshake"
+ },
+ "27": {
+ "desc": "lt6_core_code_to_sp"
+ },
+ "28": {
+ "desc": "lt7_spr_instr_stop"
+ },
+ "29": {
+ "desc": "lt7_attn_complete"
+ },
+ "30": {
+ "desc": "lt7_core_checkstop_recovery_handshake"
+ },
+ "31": {
+ "desc": "lt7_core_code_to_sp"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/iohs_dlp_phy_config.json b/chip_data/p10_20/iohs_dlp_phy_config.json
new file mode 100644
index 0000000..3081c96
--- /dev/null
+++ b/chip_data/p10_20/iohs_dlp_phy_config.json
@@ -0,0 +1,1317 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "IOHS_DLP_FIR": {
+ "instances": {
+ "0": "0x18011000",
+ "1": "0x19011000",
+ "2": "0x1A011000",
+ "3": "0x1B011000",
+ "4": "0x1C011000",
+ "5": "0x1D011000",
+ "6": "0x1E011000",
+ "7": "0x1F011000"
+ }
+ },
+ "IOHS_DLP_FIR_MASK": {
+ "instances": {
+ "0": "0x18011003",
+ "1": "0x19011003",
+ "2": "0x1A011003",
+ "3": "0x1B011003",
+ "4": "0x1C011003",
+ "5": "0x1D011003",
+ "6": "0x1E011003",
+ "7": "0x1F011003"
+ }
+ },
+ "IOHS_DLP_FIR_ACT0": {
+ "instances": {
+ "0": "0x18011006",
+ "1": "0x19011006",
+ "2": "0x1A011006",
+ "3": "0x1B011006",
+ "4": "0x1C011006",
+ "5": "0x1D011006",
+ "6": "0x1E011006",
+ "7": "0x1F011006"
+ }
+ },
+ "IOHS_DLP_FIR_ACT1": {
+ "instances": {
+ "0": "0x18011007",
+ "1": "0x19011007",
+ "2": "0x1A011007",
+ "3": "0x1B011007",
+ "4": "0x1C011007",
+ "5": "0x1D011007",
+ "6": "0x1E011007",
+ "7": "0x1F011007"
+ }
+ },
+ "IOHS_DLP_FIR_WOF": {
+ "instances": {
+ "0": "0x18011008",
+ "1": "0x19011008",
+ "2": "0x1A011008",
+ "3": "0x1B011008",
+ "4": "0x1C011008",
+ "5": "0x1D011008",
+ "6": "0x1E011008",
+ "7": "0x1F011008"
+ }
+ },
+ "IOHS_DLP_CONFIG": {
+ "instances": {
+ "0": "0x1801100A",
+ "1": "0x1901100A",
+ "2": "0x1A01100A",
+ "3": "0x1B01100A",
+ "4": "0x1C01100A",
+ "5": "0x1D01100A",
+ "6": "0x1E01100A",
+ "7": "0x1F01100A"
+ }
+ },
+ "IOHS_DLP_CONTROL": {
+ "instances": {
+ "0": "0x1801100B",
+ "1": "0x1901100B",
+ "2": "0x1A01100B",
+ "3": "0x1B01100B",
+ "4": "0x1C01100B",
+ "5": "0x1D01100B",
+ "6": "0x1E01100B",
+ "7": "0x1F01100B"
+ }
+ },
+ "IOHS_DLP_PHY_CONFIG": {
+ "instances": {
+ "0": "0x1801100C",
+ "1": "0x1901100C",
+ "2": "0x1A01100C",
+ "3": "0x1B01100C",
+ "4": "0x1C01100C",
+ "5": "0x1D01100C",
+ "6": "0x1E01100C",
+ "7": "0x1F01100C"
+ }
+ },
+ "IOHS_DLP_SEC_CONFIG": {
+ "instances": {
+ "0": "0x1801100D",
+ "1": "0x1901100D",
+ "2": "0x1A01100D",
+ "3": "0x1B01100D",
+ "4": "0x1C01100D",
+ "5": "0x1D01100D",
+ "6": "0x1E01100D",
+ "7": "0x1F01100D"
+ }
+ },
+ "IOHS_DLP_OPTICAL_CONFIG": {
+ "instances": {
+ "0": "0x1801100F",
+ "1": "0x1901100F",
+ "2": "0x1A01100F",
+ "3": "0x1B01100F",
+ "4": "0x1C01100F",
+ "5": "0x1D01100F",
+ "6": "0x1E01100F",
+ "7": "0x1F01100F"
+ }
+ },
+ "IOHS_DLP_LINK0_TX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011010",
+ "1": "0x19011010",
+ "2": "0x1A011010",
+ "3": "0x1B011010",
+ "4": "0x1C011010",
+ "5": "0x1D011010",
+ "6": "0x1E011010",
+ "7": "0x1F011010"
+ }
+ },
+ "IOHS_DLP_LINK1_TX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011011",
+ "1": "0x19011011",
+ "2": "0x1A011011",
+ "3": "0x1B011011",
+ "4": "0x1C011011",
+ "5": "0x1D011011",
+ "6": "0x1E011011",
+ "7": "0x1F011011"
+ }
+ },
+ "IOHS_DLP_LINK0_RX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011012",
+ "1": "0x19011012",
+ "2": "0x1A011012",
+ "3": "0x1B011012",
+ "4": "0x1C011012",
+ "5": "0x1D011012",
+ "6": "0x1E011012",
+ "7": "0x1F011012"
+ }
+ },
+ "IOHS_DLP_LINK1_RX_LANE_CONTROL": {
+ "instances": {
+ "0": "0x18011013",
+ "1": "0x19011013",
+ "2": "0x1A011013",
+ "3": "0x1B011013",
+ "4": "0x1C011013",
+ "5": "0x1D011013",
+ "6": "0x1E011013",
+ "7": "0x1F011013"
+ }
+ },
+ "IOHS_DLP_LINK0_INFO": {
+ "instances": {
+ "0": "0x18011014",
+ "1": "0x19011014",
+ "2": "0x1A011014",
+ "3": "0x1B011014",
+ "4": "0x1C011014",
+ "5": "0x1D011014",
+ "6": "0x1E011014",
+ "7": "0x1F011014"
+ }
+ },
+ "IOHS_DLP_LINK1_INFO": {
+ "instances": {
+ "0": "0x18011015",
+ "1": "0x19011015",
+ "2": "0x1A011015",
+ "3": "0x1B011015",
+ "4": "0x1C011015",
+ "5": "0x1D011015",
+ "6": "0x1E011015",
+ "7": "0x1F011015"
+ }
+ },
+ "IOHS_DLP_LINK0_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011016",
+ "1": "0x19011016",
+ "2": "0x1A011016",
+ "3": "0x1B011016",
+ "4": "0x1C011016",
+ "5": "0x1D011016",
+ "6": "0x1E011016",
+ "7": "0x1F011016"
+ }
+ },
+ "IOHS_DLP_LINK1_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011017",
+ "1": "0x19011017",
+ "2": "0x1A011017",
+ "3": "0x1B011017",
+ "4": "0x1C011017",
+ "5": "0x1D011017",
+ "6": "0x1E011017",
+ "7": "0x1F011017"
+ }
+ },
+ "IOHS_DLP_REPLAY_THRESHOLD": {
+ "instances": {
+ "0": "0x18011018",
+ "1": "0x19011018",
+ "2": "0x1A011018",
+ "3": "0x1B011018",
+ "4": "0x1C011018",
+ "5": "0x1D011018",
+ "6": "0x1E011018",
+ "7": "0x1F011018"
+ }
+ },
+ "IOHS_DLP_SL_ECC_THRESHOLD": {
+ "instances": {
+ "0": "0x18011019",
+ "1": "0x19011019",
+ "2": "0x1A011019",
+ "3": "0x1B011019",
+ "4": "0x1C011019",
+ "5": "0x1D011019",
+ "6": "0x1E011019",
+ "7": "0x1F011019"
+ }
+ },
+ "IOHS_DLP_LINK0_SYN_CAPTURE": {
+ "instances": {
+ "0": "0x18011022",
+ "1": "0x19011022",
+ "2": "0x1A011022",
+ "3": "0x1B011022",
+ "4": "0x1C011022",
+ "5": "0x1D011022",
+ "6": "0x1E011022",
+ "7": "0x1F011022"
+ }
+ },
+ "IOHS_DLP_LINK1_SYN_CAPTURE": {
+ "instances": {
+ "0": "0x18011023",
+ "1": "0x19011023",
+ "2": "0x1A011023",
+ "3": "0x1B011023",
+ "4": "0x1C011023",
+ "5": "0x1D011023",
+ "6": "0x1E011023",
+ "7": "0x1F011023"
+ }
+ },
+ "IOHS_DLP_LINK0_EDPL_STATUS": {
+ "instances": {
+ "0": "0x18011024",
+ "1": "0x19011024",
+ "2": "0x1A011024",
+ "3": "0x1B011024",
+ "4": "0x1C011024",
+ "5": "0x1D011024",
+ "6": "0x1E011024",
+ "7": "0x1F011024"
+ }
+ },
+ "IOHS_DLP_LINK1_EDPL_STATUS": {
+ "instances": {
+ "0": "0x18011025",
+ "1": "0x19011025",
+ "2": "0x1A011025",
+ "3": "0x1B011025",
+ "4": "0x1C011025",
+ "5": "0x1D011025",
+ "6": "0x1E011025",
+ "7": "0x1F011025"
+ }
+ },
+ "IOHS_DLP_LINK0_QUALITY": {
+ "instances": {
+ "0": "0x18011026",
+ "1": "0x19011026",
+ "2": "0x1A011026",
+ "3": "0x1B011026",
+ "4": "0x1C011026",
+ "5": "0x1D011026",
+ "6": "0x1E011026",
+ "7": "0x1F011026"
+ }
+ },
+ "IOHS_DLP_LINK1_QUALITY": {
+ "instances": {
+ "0": "0x18011027",
+ "1": "0x19011027",
+ "2": "0x1A011027",
+ "3": "0x1B011027",
+ "4": "0x1C011027",
+ "5": "0x1D011027",
+ "6": "0x1E011027",
+ "7": "0x1F011027"
+ }
+ },
+ "IOHS_DLP_DLL_STATUS": {
+ "instances": {
+ "0": "0x18011028",
+ "1": "0x19011028",
+ "2": "0x1A011028",
+ "3": "0x1B011028",
+ "4": "0x1C011028",
+ "5": "0x1D011028",
+ "6": "0x1E011028",
+ "7": "0x1F011028"
+ }
+ },
+ "IOHS_DLP_MISC_ERROR_STATUS": {
+ "instances": {
+ "0": "0x18011029",
+ "1": "0x19011029",
+ "2": "0x1A011029",
+ "3": "0x1B011029",
+ "4": "0x1C011029",
+ "5": "0x1D011029",
+ "6": "0x1E011029",
+ "7": "0x1F011029"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "IOHS_DLP_PHY_CONFIG": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_PHY_CONFIG"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000003"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "62": {
+ "desc": "Attention from IOHS_DLP_FIR in OpenCAPI mode",
+ "child_node": {
+ "name": "IOHS_DLP_FIR_OC",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "63": {
+ "desc": "Attention from IOHS_DLP_FIR in SMP mode",
+ "child_node": {
+ "name": "IOHS_DLP_FIR_SMP",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "IOHS_DLP_FIR_OC": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "unused"
+ },
+ "1": {
+ "desc": "unused"
+ },
+ "2": {
+ "desc": "unused"
+ },
+ "3": {
+ "desc": "unused"
+ },
+ "4": {
+ "desc": "unused"
+ },
+ "5": {
+ "desc": "unused"
+ },
+ "6": {
+ "desc": "link0 crc error"
+ },
+ "7": {
+ "desc": "link1 crc error"
+ },
+ "8": {
+ "desc": "link0 nak received"
+ },
+ "9": {
+ "desc": "link1 nak received"
+ },
+ "10": {
+ "desc": "unused"
+ },
+ "11": {
+ "desc": "unused"
+ },
+ "12": {
+ "desc": "unused"
+ },
+ "13": {
+ "desc": "unused"
+ },
+ "14": {
+ "desc": "unused"
+ },
+ "15": {
+ "desc": "unused"
+ },
+ "16": {
+ "desc": "unused"
+ },
+ "17": {
+ "desc": "unused"
+ },
+ "18": {
+ "desc": "unused"
+ },
+ "19": {
+ "desc": "unused"
+ },
+ "20": {
+ "desc": "link0 loss block align"
+ },
+ "21": {
+ "desc": "link1 loss block align"
+ },
+ "22": {
+ "desc": "link0 invalid block"
+ },
+ "23": {
+ "desc": "link1 invalid block"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "link0 deskew overflow"
+ },
+ "27": {
+ "desc": "link1 deskew overflow"
+ },
+ "28": {
+ "desc": "link0 sw retrain"
+ },
+ "29": {
+ "desc": "link1 sw retrain"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "link0 no forward progress"
+ },
+ "35": {
+ "desc": "link1 no forward progress"
+ },
+ "36": {
+ "desc": "link0 training set received"
+ },
+ "37": {
+ "desc": "link1 training set received"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "link0 degraded mode"
+ },
+ "45": {
+ "desc": "link1 degraded mode"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "link0 dlx error"
+ },
+ "49": {
+ "desc": "link1 dlx error"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "link0 correctable array error"
+ },
+ "53": {
+ "desc": "link1 correctable array error"
+ },
+ "54": {
+ "desc": "link0 uncorrectable array error"
+ },
+ "55": {
+ "desc": "link1 uncorrectable array error"
+ },
+ "56": {
+ "desc": "link0 dlx clock frequency error"
+ },
+ "57": {
+ "desc": "link1 dlx clock frequency error"
+ },
+ "58": {
+ "desc": "link0 unrecoverable error"
+ },
+ "59": {
+ "desc": "link1 unrecoverable error"
+ },
+ "60": {
+ "desc": "link0 internal error"
+ },
+ "61": {
+ "desc": "link1 internal error"
+ }
+ }
+ },
+ "IOHS_DLP_FIR_SMP": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_DLP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "link0 trained"
+ },
+ "1": {
+ "desc": "link1 trained"
+ },
+ "2": {
+ "desc": "link0 op irq"
+ },
+ "3": {
+ "desc": "link1 op irq"
+ },
+ "4": {
+ "desc": "link0 replay threshold"
+ },
+ "5": {
+ "desc": "link1 replay threshold"
+ },
+ "6": {
+ "desc": "link0 crc error"
+ },
+ "7": {
+ "desc": "link1 crc error"
+ },
+ "8": {
+ "desc": "link0 nak received"
+ },
+ "9": {
+ "desc": "link1 nak received"
+ },
+ "10": {
+ "desc": "link0 replay buffer full"
+ },
+ "11": {
+ "desc": "link1 replay buffer full"
+ },
+ "12": {
+ "desc": "link0 sl ecc threshold"
+ },
+ "13": {
+ "desc": "link1 sl ecc threshold"
+ },
+ "14": {
+ "desc": "link0 sl ecc correctable"
+ },
+ "15": {
+ "desc": "link1 sl ecc correctable"
+ },
+ "16": {
+ "desc": "link0 sl ecc ue"
+ },
+ "17": {
+ "desc": "link1 sl ecc ue"
+ },
+ "18": {
+ "desc": "link0 retrain threshold"
+ },
+ "19": {
+ "desc": "link1 retrain threshold"
+ },
+ "20": {
+ "desc": "link0 loss block align"
+ },
+ "21": {
+ "desc": "link1 loss block align"
+ },
+ "22": {
+ "desc": "link0 invalid block"
+ },
+ "23": {
+ "desc": "link1 invalid block"
+ },
+ "24": {
+ "desc": "link0 deskew error"
+ },
+ "25": {
+ "desc": "link1 deskew error"
+ },
+ "26": {
+ "desc": "link0 deskew overflow"
+ },
+ "27": {
+ "desc": "link1 deskew overflow"
+ },
+ "28": {
+ "desc": "link0 sw retrain"
+ },
+ "29": {
+ "desc": "link1 sw retrain"
+ },
+ "30": {
+ "desc": "link0 ack queue overflow"
+ },
+ "31": {
+ "desc": "link1 ack queue overflow"
+ },
+ "32": {
+ "desc": "link0 ack queue underflow"
+ },
+ "33": {
+ "desc": "link1 ack queue underflow"
+ },
+ "34": {
+ "desc": "link0 num replay"
+ },
+ "35": {
+ "desc": "link1 num replay"
+ },
+ "36": {
+ "desc": "link0 training set received"
+ },
+ "37": {
+ "desc": "link1 training set received"
+ },
+ "38": {
+ "desc": "link0 prbs select error"
+ },
+ "39": {
+ "desc": "link1 prbs select error"
+ },
+ "40": {
+ "desc": "link0 tcomplete bad"
+ },
+ "41": {
+ "desc": "link1 tcomplete bad"
+ },
+ "42": {
+ "desc": "link0 no spare lane available"
+ },
+ "43": {
+ "desc": "link1 no spare lane available"
+ },
+ "44": {
+ "desc": "link0 spare done"
+ },
+ "45": {
+ "desc": "link1 spare done"
+ },
+ "46": {
+ "desc": "link0 too many crc errors"
+ },
+ "47": {
+ "desc": "link1 too many crc errors"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "link0 osc switch"
+ },
+ "51": {
+ "desc": "link1 osc switch"
+ },
+ "52": {
+ "desc": "link0 correctable array error"
+ },
+ "53": {
+ "desc": "link1 correctable array error"
+ },
+ "54": {
+ "desc": "link0 uncorrectable array error"
+ },
+ "55": {
+ "desc": "link1 uncorrectable array error"
+ },
+ "56": {
+ "desc": "link0 training failed"
+ },
+ "57": {
+ "desc": "link1 training failed"
+ },
+ "58": {
+ "desc": "link0 unrecoverable error"
+ },
+ "59": {
+ "desc": "link1 unrecoverable error"
+ },
+ "60": {
+ "desc": "link0 internal error"
+ },
+ "61": {
+ "desc": "link1 internal error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "IOHS_DLP_FIR_SMP",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "IOHS_DLP_FIR_SMP": [
+ {
+ "reg_name": "IOHS_DLP_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_SEC_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_OPTICAL_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_TX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_TX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_RX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_RX_LANE_CONTROL",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_REPLAY_THRESHOLD",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_SL_ECC_THRESHOLD",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_SYN_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_SYN_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_EDPL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_EDPL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK0_QUALITY",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_LINK1_QUALITY",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_DLL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "IOHS_DLP_MISC_ERROR_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/mc_omi_dl_err_rpt.json b/chip_data/p10_20/mc_omi_dl_err_rpt.json
new file mode 100644
index 0000000..b3129cb
--- /dev/null
+++ b/chip_data/p10_20/mc_omi_dl_err_rpt.json
@@ -0,0 +1,106 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "isolation_nodes": {
+ "MC_OMI_DL_ERR_RPT": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000000FFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "52": {
+ "desc": "spare"
+ },
+ "53": {
+ "desc": "flit hammer"
+ },
+ "54": {
+ "desc": "illegal TX lane reversal request"
+ },
+ "55": {
+ "desc": "RX receiving slow A"
+ },
+ "56": {
+ "desc": "RX receiving illegal run length"
+ },
+ "57": {
+ "desc": "control parity error"
+ },
+ "58": {
+ "desc": "spare"
+ },
+ "59": {
+ "desc": "truncated flit from TL"
+ },
+ "60": {
+ "desc": "illegal run length from TL"
+ },
+ "61": {
+ "desc": "Ack pointer overflow"
+ },
+ "62": {
+ "desc": "UE on control flit replay buffer"
+ },
+ "63": {
+ "desc": "UE on control flit frame buffer"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_eq.json b/chip_data/p10_20/node_cfir_eq.json
new file mode 100644
index 0000000..f3140a2
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_eq.json
@@ -0,0 +1,1227 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_EQ_CS": {
+ "instances": {
+ "0": "0x20040000",
+ "1": "0x21040000",
+ "2": "0x22040000",
+ "3": "0x23040000",
+ "4": "0x24040000",
+ "5": "0x25040000",
+ "6": "0x26040000",
+ "7": "0x27040000"
+ }
+ },
+ "CFIR_EQ_CS_MASK": {
+ "instances": {
+ "0": "0x20040040",
+ "1": "0x21040040",
+ "2": "0x22040040",
+ "3": "0x23040040",
+ "4": "0x24040040",
+ "5": "0x25040040",
+ "6": "0x26040040",
+ "7": "0x27040040"
+ }
+ },
+ "CFIR_EQ_RE": {
+ "instances": {
+ "0": "0x20040001",
+ "1": "0x21040001",
+ "2": "0x22040001",
+ "3": "0x23040001",
+ "4": "0x24040001",
+ "5": "0x25040001",
+ "6": "0x26040001",
+ "7": "0x27040001"
+ }
+ },
+ "CFIR_EQ_RE_MASK": {
+ "instances": {
+ "0": "0x20040041",
+ "1": "0x21040041",
+ "2": "0x22040041",
+ "3": "0x23040041",
+ "4": "0x24040041",
+ "5": "0x25040041",
+ "6": "0x26040041",
+ "7": "0x27040041"
+ }
+ },
+ "CFIR_EQ_SPA": {
+ "instances": {
+ "0": "0x20040002",
+ "1": "0x21040002",
+ "2": "0x22040002",
+ "3": "0x23040002",
+ "4": "0x24040002",
+ "5": "0x25040002",
+ "6": "0x26040002",
+ "7": "0x27040002"
+ }
+ },
+ "CFIR_EQ_SPA_MASK": {
+ "instances": {
+ "0": "0x20040042",
+ "1": "0x21040042",
+ "2": "0x22040042",
+ "3": "0x23040042",
+ "4": "0x24040042",
+ "5": "0x25040042",
+ "6": "0x26040042",
+ "7": "0x27040042"
+ }
+ },
+ "CFIR_EQ_UCS": {
+ "instances": {
+ "0": "0x20040003",
+ "1": "0x21040003",
+ "2": "0x22040003",
+ "3": "0x23040003",
+ "4": "0x24040003",
+ "5": "0x25040003",
+ "6": "0x26040003",
+ "7": "0x27040003"
+ }
+ },
+ "CFIR_EQ_UCS_MASK": {
+ "instances": {
+ "0": "0x20040043",
+ "1": "0x21040043",
+ "2": "0x22040043",
+ "3": "0x23040043",
+ "4": "0x24040043",
+ "5": "0x25040043",
+ "6": "0x26040043",
+ "7": "0x27040043"
+ }
+ },
+ "CFIR_EQ_HA": {
+ "instances": {
+ "0": "0x20040004",
+ "1": "0x21040004",
+ "2": "0x22040004",
+ "3": "0x23040004",
+ "4": "0x24040004",
+ "5": "0x25040004",
+ "6": "0x26040004",
+ "7": "0x27040004"
+ }
+ },
+ "CFIR_EQ_HA_MASK": {
+ "instances": {
+ "0": "0x20040044",
+ "1": "0x21040044",
+ "2": "0x22040044",
+ "3": "0x23040044",
+ "4": "0x24040044",
+ "5": "0x25040044",
+ "6": "0x26040044",
+ "7": "0x27040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_EQ_CS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from EQ_QME_FIR",
+ "child_node": {
+ "name": "EQ_QME_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_RE": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from EQ_L2_FIR",
+ "child_node": {
+ "name": "EQ_L2_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from EQ_L3_FIR",
+ "child_node": {
+ "name": "EQ_L3_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from EQ_NCU_FIR",
+ "child_node": {
+ "name": "EQ_NCU_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from EQ_QME_FIR",
+ "child_node": {
+ "name": "EQ_QME_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_SPA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "7": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "8": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "9": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "10": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "11": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "12": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "13": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "14": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "15": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "16": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "17": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "18": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "19": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ },
+ "20": {
+ "desc": "Core Special Attention Register",
+ "child_node": {
+ "name": "EQ_CORE_THREAD_STATE",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_UCS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 0,
+ "1": 4,
+ "2": 8,
+ "3": 12,
+ "4": 16,
+ "5": 20,
+ "6": 24,
+ "7": 28
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 1,
+ "1": 5,
+ "2": 9,
+ "3": 13,
+ "4": 17,
+ "5": 21,
+ "6": 25,
+ "7": 29
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 2,
+ "1": 6,
+ "2": 10,
+ "3": 14,
+ "4": 18,
+ "5": 22,
+ "6": 26,
+ "7": 30
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from EQ_CORE_FIR",
+ "child_node": {
+ "name": "EQ_CORE_FIR",
+ "inst": {
+ "0": 3,
+ "1": 7,
+ "2": 11,
+ "3": 15,
+ "4": 19,
+ "5": 23,
+ "6": 27,
+ "7": 31
+ }
+ }
+ }
+ }
+ },
+ "CFIR_EQ_HA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_EQ_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from EQ_LOCAL_FIR",
+ "child_node": {
+ "name": "EQ_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_iohs.json b/chip_data/p10_20/node_cfir_iohs.json
new file mode 100644
index 0000000..f031a4b
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_iohs.json
@@ -0,0 +1,411 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_IOHS_CS": {
+ "instances": {
+ "0": "0x18040000",
+ "1": "0x19040000",
+ "2": "0x1A040000",
+ "3": "0x1B040000",
+ "4": "0x1C040000",
+ "5": "0x1D040000",
+ "6": "0x1E040000",
+ "7": "0x1F040000"
+ }
+ },
+ "CFIR_IOHS_CS_MASK": {
+ "instances": {
+ "0": "0x18040040",
+ "1": "0x19040040",
+ "2": "0x1A040040",
+ "3": "0x1B040040",
+ "4": "0x1C040040",
+ "5": "0x1D040040",
+ "6": "0x1E040040",
+ "7": "0x1F040040"
+ }
+ },
+ "CFIR_IOHS_RE": {
+ "instances": {
+ "0": "0x18040001",
+ "1": "0x19040001",
+ "2": "0x1A040001",
+ "3": "0x1B040001",
+ "4": "0x1C040001",
+ "5": "0x1D040001",
+ "6": "0x1E040001",
+ "7": "0x1F040001"
+ }
+ },
+ "CFIR_IOHS_RE_MASK": {
+ "instances": {
+ "0": "0x18040041",
+ "1": "0x19040041",
+ "2": "0x1A040041",
+ "3": "0x1B040041",
+ "4": "0x1C040041",
+ "5": "0x1D040041",
+ "6": "0x1E040041",
+ "7": "0x1F040041"
+ }
+ },
+ "CFIR_IOHS_SPA": {
+ "instances": {
+ "0": "0x18040002",
+ "1": "0x19040002",
+ "2": "0x1A040002",
+ "3": "0x1B040002",
+ "4": "0x1C040002",
+ "5": "0x1D040002",
+ "6": "0x1E040002",
+ "7": "0x1F040002"
+ }
+ },
+ "CFIR_IOHS_SPA_MASK": {
+ "instances": {
+ "0": "0x18040042",
+ "1": "0x19040042",
+ "2": "0x1A040042",
+ "3": "0x1B040042",
+ "4": "0x1C040042",
+ "5": "0x1D040042",
+ "6": "0x1E040042",
+ "7": "0x1F040042"
+ }
+ },
+ "CFIR_IOHS_UCS": {
+ "instances": {
+ "0": "0x18040003",
+ "1": "0x19040003",
+ "2": "0x1A040003",
+ "3": "0x1B040003",
+ "4": "0x1C040003",
+ "5": "0x1D040003",
+ "6": "0x1E040003",
+ "7": "0x1F040003"
+ }
+ },
+ "CFIR_IOHS_UCS_MASK": {
+ "instances": {
+ "0": "0x18040043",
+ "1": "0x19040043",
+ "2": "0x1A040043",
+ "3": "0x1B040043",
+ "4": "0x1C040043",
+ "5": "0x1D040043",
+ "6": "0x1E040043",
+ "7": "0x1F040043"
+ }
+ },
+ "CFIR_IOHS_HA": {
+ "instances": {
+ "0": "0x18040004",
+ "1": "0x19040004",
+ "2": "0x1A040004",
+ "3": "0x1B040004",
+ "4": "0x1C040004",
+ "5": "0x1D040004",
+ "6": "0x1E040004",
+ "7": "0x1F040004"
+ }
+ },
+ "CFIR_IOHS_HA_MASK": {
+ "instances": {
+ "0": "0x18040044",
+ "1": "0x19040044",
+ "2": "0x1A040044",
+ "3": "0x1B040044",
+ "4": "0x1C040044",
+ "5": "0x1D040044",
+ "6": "0x1E040044",
+ "7": "0x1F040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_IOHS_CS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_RE": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_SPA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from IOHS_DLP_FIR",
+ "child_node": {
+ "name": "IOHS_DLP_PHY_CONFIG",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_UCS": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_IOHS_HA": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_IOHS_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from IOHS_LOCAL_FIR",
+ "child_node": {
+ "name": "IOHS_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_mc.json b/chip_data/p10_20/node_cfir_mc.json
new file mode 100644
index 0000000..b86cbfb
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_mc.json
@@ -0,0 +1,735 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_MC_CS": {
+ "instances": {
+ "0": "0x0C040000",
+ "1": "0x0D040000",
+ "2": "0x0E040000",
+ "3": "0x0F040000"
+ }
+ },
+ "CFIR_MC_CS_MASK": {
+ "instances": {
+ "0": "0x0C040040",
+ "1": "0x0D040040",
+ "2": "0x0E040040",
+ "3": "0x0F040040"
+ }
+ },
+ "CFIR_MC_RE": {
+ "instances": {
+ "0": "0x0C040001",
+ "1": "0x0D040001",
+ "2": "0x0E040001",
+ "3": "0x0F040001"
+ }
+ },
+ "CFIR_MC_RE_MASK": {
+ "instances": {
+ "0": "0x0C040041",
+ "1": "0x0D040041",
+ "2": "0x0E040041",
+ "3": "0x0F040041"
+ }
+ },
+ "CFIR_MC_SPA": {
+ "instances": {
+ "0": "0x0C040002",
+ "1": "0x0D040002",
+ "2": "0x0E040002",
+ "3": "0x0F040002"
+ }
+ },
+ "CFIR_MC_SPA_MASK": {
+ "instances": {
+ "0": "0x0C040042",
+ "1": "0x0D040042",
+ "2": "0x0E040042",
+ "3": "0x0F040042"
+ }
+ },
+ "CFIR_MC_UCS": {
+ "instances": {
+ "0": "0x0C040003",
+ "1": "0x0D040003",
+ "2": "0x0E040003",
+ "3": "0x0F040003"
+ }
+ },
+ "CFIR_MC_UCS_MASK": {
+ "instances": {
+ "0": "0x0C040043",
+ "1": "0x0D040043",
+ "2": "0x0E040043",
+ "3": "0x0F040043"
+ }
+ },
+ "CFIR_MC_HA": {
+ "instances": {
+ "0": "0x0C040004",
+ "1": "0x0D040004",
+ "2": "0x0E040004",
+ "3": "0x0F040004"
+ }
+ },
+ "CFIR_MC_HA_MASK": {
+ "instances": {
+ "0": "0x0C040044",
+ "1": "0x0D040044",
+ "2": "0x0E040044",
+ "3": "0x0F040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_MC_CS": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_RE": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_SPA": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC_OMI_DL_FIR",
+ "child_node": {
+ "name": "MC_OMI_DL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_UCS": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_MC_HA": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MC_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MC_LOCAL_FIR",
+ "child_node": {
+ "name": "MC_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MC_DSTL_FIR",
+ "child_node": {
+ "name": "MC_DSTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MC_USTL_FIR",
+ "child_node": {
+ "name": "MC_USTL_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from MC_FIR",
+ "child_node": {
+ "name": "MC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from MC_MISC_FIR",
+ "child_node": {
+ "name": "MC_MISC_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_n0.json b/chip_data/p10_20/node_cfir_n0.json
new file mode 100644
index 0000000..e729158
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_n0.json
@@ -0,0 +1,474 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_N0_CS": {
+ "instances": {
+ "0": "0x02040000"
+ }
+ },
+ "CFIR_N0_CS_MASK": {
+ "instances": {
+ "0": "0x02040040"
+ }
+ },
+ "CFIR_N0_RE": {
+ "instances": {
+ "0": "0x02040001"
+ }
+ },
+ "CFIR_N0_RE_MASK": {
+ "instances": {
+ "0": "0x02040041"
+ }
+ },
+ "CFIR_N0_SPA": {
+ "instances": {
+ "0": "0x02040002"
+ }
+ },
+ "CFIR_N0_SPA_MASK": {
+ "instances": {
+ "0": "0x02040042"
+ }
+ },
+ "CFIR_N0_UCS": {
+ "instances": {
+ "0": "0x02040003"
+ }
+ },
+ "CFIR_N0_UCS_MASK": {
+ "instances": {
+ "0": "0x02040043"
+ }
+ },
+ "CFIR_N0_HA": {
+ "instances": {
+ "0": "0x02040004"
+ }
+ },
+ "CFIR_N0_HA_MASK": {
+ "instances": {
+ "0": "0x02040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_N0_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 5
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 5
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from INT_CQ_FIR",
+ "child_node": {
+ "name": "INT_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from VAS_FIR",
+ "child_node": {
+ "name": "VAS_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from NX_DMA_ENG_FIR",
+ "child_node": {
+ "name": "NX_DMA_ENG_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from NX_CQ_FIR",
+ "child_node": {
+ "name": "NX_CQ_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N0_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N0_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N0_LOCAL_FIR",
+ "child_node": {
+ "name": "N0_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_n1.json b/chip_data/p10_20/node_cfir_n1.json
new file mode 100644
index 0000000..d512ec1
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_n1.json
@@ -0,0 +1,906 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_N1_CS": {
+ "instances": {
+ "0": "0x03040000"
+ }
+ },
+ "CFIR_N1_CS_MASK": {
+ "instances": {
+ "0": "0x03040040"
+ }
+ },
+ "CFIR_N1_RE": {
+ "instances": {
+ "0": "0x03040001"
+ }
+ },
+ "CFIR_N1_RE_MASK": {
+ "instances": {
+ "0": "0x03040041"
+ }
+ },
+ "CFIR_N1_SPA": {
+ "instances": {
+ "0": "0x03040002"
+ }
+ },
+ "CFIR_N1_SPA_MASK": {
+ "instances": {
+ "0": "0x03040042"
+ }
+ },
+ "CFIR_N1_UCS": {
+ "instances": {
+ "0": "0x03040003"
+ }
+ },
+ "CFIR_N1_UCS_MASK": {
+ "instances": {
+ "0": "0x03040043"
+ }
+ },
+ "CFIR_N1_HA": {
+ "instances": {
+ "0": "0x03040004"
+ }
+ },
+ "CFIR_N1_HA_MASK": {
+ "instances": {
+ "0": "0x03040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_N1_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from HCA_FIR",
+ "child_node": {
+ "name": "HCA_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from LPC_FIR",
+ "child_node": {
+ "name": "LPC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from PB_EXT_FIR",
+ "child_node": {
+ "name": "PB_EXT_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from PSIHB_FIR",
+ "child_node": {
+ "name": "PSIHB_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from PBAF_FIR",
+ "child_node": {
+ "name": "PBAF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from HCA_FIR",
+ "child_node": {
+ "name": "HCA_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from LPC_FIR",
+ "child_node": {
+ "name": "LPC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from PCI_NEST_FIR",
+ "child_node": {
+ "name": "PCI_NEST_FIR",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from PSIHB_FIR",
+ "child_node": {
+ "name": "PSIHB_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from PBAF_FIR",
+ "child_node": {
+ "name": "PBAF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from MCD_FIR",
+ "child_node": {
+ "name": "MCD_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "20": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "22": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "23": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from PB_STATION_FIR_EQ",
+ "child_node": {
+ "name": "PB_STATION_FIR_EQ",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from PB_STATION_FIR_EN1",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from PB_STATION_FIR_EN2",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from PB_STATION_FIR_EN3",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from PB_STATION_FIR_EN4",
+ "child_node": {
+ "name": "PB_STATION_FIR_EN4",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from PB_STATION_FIR_ES1",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES1",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from PB_STATION_FIR_ES2",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES2",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from PB_STATION_FIR_ES3",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES3",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from PB_STATION_FIR_ES4",
+ "child_node": {
+ "name": "PB_STATION_FIR_ES4",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from NMMU_CQ_FIR",
+ "child_node": {
+ "name": "NMMU_CQ_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from NMMU_FIR",
+ "child_node": {
+ "name": "NMMU_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_N1_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_N1_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from N1_LOCAL_FIR",
+ "child_node": {
+ "name": "N1_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_paue.json b/chip_data/p10_20/node_cfir_paue.json
new file mode 100644
index 0000000..a8bea12
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_paue.json
@@ -0,0 +1,433 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_PAUE_CS": {
+ "instances": {
+ "0": "0x10040000",
+ "1": "0x11040000"
+ }
+ },
+ "CFIR_PAUE_CS_MASK": {
+ "instances": {
+ "0": "0x10040040",
+ "1": "0x11040040"
+ }
+ },
+ "CFIR_PAUE_RE": {
+ "instances": {
+ "0": "0x10040001",
+ "1": "0x11040001"
+ }
+ },
+ "CFIR_PAUE_RE_MASK": {
+ "instances": {
+ "0": "0x10040041",
+ "1": "0x11040041"
+ }
+ },
+ "CFIR_PAUE_SPA": {
+ "instances": {
+ "0": "0x10040002",
+ "1": "0x11040002"
+ }
+ },
+ "CFIR_PAUE_SPA_MASK": {
+ "instances": {
+ "0": "0x10040042",
+ "1": "0x11040042"
+ }
+ },
+ "CFIR_PAUE_UCS": {
+ "instances": {
+ "0": "0x10040003",
+ "1": "0x11040003"
+ }
+ },
+ "CFIR_PAUE_UCS_MASK": {
+ "instances": {
+ "0": "0x10040043",
+ "1": "0x11040043"
+ }
+ },
+ "CFIR_PAUE_HA": {
+ "instances": {
+ "0": "0x10040004",
+ "1": "0x11040004"
+ }
+ },
+ "CFIR_PAUE_HA_MASK": {
+ "instances": {
+ "0": "0x10040044",
+ "1": "0x11040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PAUE_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUE_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUE_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_pauw.json b/chip_data/p10_20/node_cfir_pauw.json
new file mode 100644
index 0000000..dd2d1ee
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_pauw.json
@@ -0,0 +1,523 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_PAUW_CS": {
+ "instances": {
+ "0": "0x12040000",
+ "1": "0x13040000"
+ }
+ },
+ "CFIR_PAUW_CS_MASK": {
+ "instances": {
+ "0": "0x12040040",
+ "1": "0x13040040"
+ }
+ },
+ "CFIR_PAUW_RE": {
+ "instances": {
+ "0": "0x12040001",
+ "1": "0x13040001"
+ }
+ },
+ "CFIR_PAUW_RE_MASK": {
+ "instances": {
+ "0": "0x12040041",
+ "1": "0x13040041"
+ }
+ },
+ "CFIR_PAUW_SPA": {
+ "instances": {
+ "0": "0x12040002",
+ "1": "0x13040002"
+ }
+ },
+ "CFIR_PAUW_SPA_MASK": {
+ "instances": {
+ "0": "0x12040042",
+ "1": "0x13040042"
+ }
+ },
+ "CFIR_PAUW_UCS": {
+ "instances": {
+ "0": "0x12040003",
+ "1": "0x13040003"
+ }
+ },
+ "CFIR_PAUW_UCS_MASK": {
+ "instances": {
+ "0": "0x12040043",
+ "1": "0x13040043"
+ }
+ },
+ "CFIR_PAUW_HA": {
+ "instances": {
+ "0": "0x12040004",
+ "1": "0x13040004"
+ }
+ },
+ "CFIR_PAUW_HA_MASK": {
+ "instances": {
+ "0": "0x12040044",
+ "1": "0x13040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PAUW_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAU_PTL_FIR",
+ "child_node": {
+ "name": "PAU_PTL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 4,
+ "1": 6
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PAU_FIR_0",
+ "child_node": {
+ "name": "PAU_FIR_0",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PAU_FIR_1",
+ "child_node": {
+ "name": "PAU_FIR_1",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PAU_FIR_2",
+ "child_node": {
+ "name": "PAU_FIR_2",
+ "inst": {
+ "0": 5,
+ "1": 7
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PAU_PHY_FIR",
+ "child_node": {
+ "name": "PAU_PHY_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PAUW_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PAUW_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PAU_LOCAL_FIR",
+ "child_node": {
+ "name": "PAU_LOCAL_FIR",
+ "inst": {
+ "0": 2,
+ "1": 3
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_pci.json b/chip_data/p10_20/node_cfir_pci.json
new file mode 100644
index 0000000..fd5a1df
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_pci.json
@@ -0,0 +1,453 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_PCI_CS": {
+ "instances": {
+ "0": "0x08040000",
+ "1": "0x09040000"
+ }
+ },
+ "CFIR_PCI_CS_MASK": {
+ "instances": {
+ "0": "0x08040040",
+ "1": "0x09040040"
+ }
+ },
+ "CFIR_PCI_RE": {
+ "instances": {
+ "0": "0x08040001",
+ "1": "0x09040001"
+ }
+ },
+ "CFIR_PCI_RE_MASK": {
+ "instances": {
+ "0": "0x08040041",
+ "1": "0x09040041"
+ }
+ },
+ "CFIR_PCI_SPA": {
+ "instances": {
+ "0": "0x08040002",
+ "1": "0x09040002"
+ }
+ },
+ "CFIR_PCI_SPA_MASK": {
+ "instances": {
+ "0": "0x08040042",
+ "1": "0x09040042"
+ }
+ },
+ "CFIR_PCI_UCS": {
+ "instances": {
+ "0": "0x08040003",
+ "1": "0x09040003"
+ }
+ },
+ "CFIR_PCI_UCS_MASK": {
+ "instances": {
+ "0": "0x08040043",
+ "1": "0x09040043"
+ }
+ },
+ "CFIR_PCI_HA": {
+ "instances": {
+ "0": "0x08040004",
+ "1": "0x09040004"
+ }
+ },
+ "CFIR_PCI_HA_MASK": {
+ "instances": {
+ "0": "0x08040044",
+ "1": "0x09040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_PCI_CS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_RE": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "7": {
+ "desc": "Attention from PCI_ETU_FIR",
+ "child_node": {
+ "name": "PCI_ETU_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 0,
+ "1": 3
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 1,
+ "1": 4
+ }
+ }
+ },
+ "11": {
+ "desc": "Attention from PCI_FIR",
+ "child_node": {
+ "name": "PCI_FIR",
+ "inst": {
+ "0": 2,
+ "1": 5
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_SPA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_UCS": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 0,
+ "1": 2
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from PCI_IOP_FIR",
+ "child_node": {
+ "name": "PCI_IOP_FIR",
+ "inst": {
+ "0": 1,
+ "1": 3
+ }
+ }
+ }
+ }
+ },
+ "CFIR_PCI_HA": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_PCI_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from PCI_LOCAL_FIR",
+ "child_node": {
+ "name": "PCI_LOCAL_FIR",
+ "inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_cfir_tp.json b/chip_data/p10_20/node_cfir_tp.json
new file mode 100644
index 0000000..423fb81
--- /dev/null
+++ b/chip_data/p10_20/node_cfir_tp.json
@@ -0,0 +1,294 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "CFIR_TP_CS": {
+ "instances": {
+ "0": "0x01040000"
+ }
+ },
+ "CFIR_TP_CS_MASK": {
+ "instances": {
+ "0": "0x01040040"
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": {
+ "0": "0x01040001"
+ }
+ },
+ "CFIR_TP_RE_MASK": {
+ "instances": {
+ "0": "0x01040041"
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": {
+ "0": "0x01040002"
+ }
+ },
+ "CFIR_TP_SPA_MASK": {
+ "instances": {
+ "0": "0x01040042"
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": {
+ "0": "0x01040003"
+ }
+ },
+ "CFIR_TP_UCS_MASK": {
+ "instances": {
+ "0": "0x01040043"
+ }
+ },
+ "CFIR_TP_HA": {
+ "instances": {
+ "0": "0x01040004"
+ }
+ },
+ "CFIR_TP_HA_MASK": {
+ "instances": {
+ "0": "0x01040044"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_TP_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from OCC_FIR",
+ "child_node": {
+ "name": "OCC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PBAO_FIR",
+ "child_node": {
+ "name": "PBAO_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "5": {
+ "desc": "Attention from OCC_FIR",
+ "child_node": {
+ "name": "OCC_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "6": {
+ "desc": "Attention from PBAO_FIR",
+ "child_node": {
+ "name": "PBAO_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ },
+ "CFIR_TP_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_HA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_HA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_core_fir.json b/chip_data/p10_20/node_eq_core_fir.json
new file mode 100644
index 0000000..3ad5b39
--- /dev/null
+++ b/chip_data/p10_20/node_eq_core_fir.json
@@ -0,0 +1,543 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_CORE_FIR": {
+ "instances": {
+ "0": "0x20028440",
+ "1": "0x20024440",
+ "2": "0x20022440",
+ "3": "0x20021440",
+ "4": "0x21028440",
+ "5": "0x21024440",
+ "6": "0x21022440",
+ "7": "0x21021440",
+ "8": "0x22028440",
+ "9": "0x22024440",
+ "10": "0x22022440",
+ "11": "0x22021440",
+ "12": "0x23028440",
+ "13": "0x23024440",
+ "14": "0x23022440",
+ "15": "0x23021440",
+ "16": "0x24028440",
+ "17": "0x24024440",
+ "18": "0x24022440",
+ "19": "0x24021440",
+ "20": "0x25028440",
+ "21": "0x25024440",
+ "22": "0x25022440",
+ "23": "0x25021440",
+ "24": "0x26028440",
+ "25": "0x26024440",
+ "26": "0x26022440",
+ "27": "0x26021440",
+ "28": "0x27028440",
+ "29": "0x27024440",
+ "30": "0x27022440",
+ "31": "0x27021440"
+ }
+ },
+ "EQ_CORE_FIR_MASK": {
+ "instances": {
+ "0": "0x20028443",
+ "1": "0x20024443",
+ "2": "0x20022443",
+ "3": "0x20021443",
+ "4": "0x21028443",
+ "5": "0x21024443",
+ "6": "0x21022443",
+ "7": "0x21021443",
+ "8": "0x22028443",
+ "9": "0x22024443",
+ "10": "0x22022443",
+ "11": "0x22021443",
+ "12": "0x23028443",
+ "13": "0x23024443",
+ "14": "0x23022443",
+ "15": "0x23021443",
+ "16": "0x24028443",
+ "17": "0x24024443",
+ "18": "0x24022443",
+ "19": "0x24021443",
+ "20": "0x25028443",
+ "21": "0x25024443",
+ "22": "0x25022443",
+ "23": "0x25021443",
+ "24": "0x26028443",
+ "25": "0x26024443",
+ "26": "0x26022443",
+ "27": "0x26021443",
+ "28": "0x27028443",
+ "29": "0x27024443",
+ "30": "0x27022443",
+ "31": "0x27021443"
+ }
+ },
+ "EQ_CORE_FIR_ACT0": {
+ "instances": {
+ "0": "0x20028446",
+ "1": "0x20024446",
+ "2": "0x20022446",
+ "3": "0x20021446",
+ "4": "0x21028446",
+ "5": "0x21024446",
+ "6": "0x21022446",
+ "7": "0x21021446",
+ "8": "0x22028446",
+ "9": "0x22024446",
+ "10": "0x22022446",
+ "11": "0x22021446",
+ "12": "0x23028446",
+ "13": "0x23024446",
+ "14": "0x23022446",
+ "15": "0x23021446",
+ "16": "0x24028446",
+ "17": "0x24024446",
+ "18": "0x24022446",
+ "19": "0x24021446",
+ "20": "0x25028446",
+ "21": "0x25024446",
+ "22": "0x25022446",
+ "23": "0x25021446",
+ "24": "0x26028446",
+ "25": "0x26024446",
+ "26": "0x26022446",
+ "27": "0x26021446",
+ "28": "0x27028446",
+ "29": "0x27024446",
+ "30": "0x27022446",
+ "31": "0x27021446"
+ }
+ },
+ "EQ_CORE_FIR_ACT1": {
+ "instances": {
+ "0": "0x20028447",
+ "1": "0x20024447",
+ "2": "0x20022447",
+ "3": "0x20021447",
+ "4": "0x21028447",
+ "5": "0x21024447",
+ "6": "0x21022447",
+ "7": "0x21021447",
+ "8": "0x22028447",
+ "9": "0x22024447",
+ "10": "0x22022447",
+ "11": "0x22021447",
+ "12": "0x23028447",
+ "13": "0x23024447",
+ "14": "0x23022447",
+ "15": "0x23021447",
+ "16": "0x24028447",
+ "17": "0x24024447",
+ "18": "0x24022447",
+ "19": "0x24021447",
+ "20": "0x25028447",
+ "21": "0x25024447",
+ "22": "0x25022447",
+ "23": "0x25021447",
+ "24": "0x26028447",
+ "25": "0x26024447",
+ "26": "0x26022447",
+ "27": "0x26021447",
+ "28": "0x27028447",
+ "29": "0x27024447",
+ "30": "0x27022447",
+ "31": "0x27021447"
+ }
+ },
+ "EQ_CORE_FIR_WOF": {
+ "instances": {
+ "0": "0x20028448",
+ "1": "0x20024448",
+ "2": "0x20022448",
+ "3": "0x20021448",
+ "4": "0x21028448",
+ "5": "0x21024448",
+ "6": "0x21022448",
+ "7": "0x21021448",
+ "8": "0x22028448",
+ "9": "0x22024448",
+ "10": "0x22022448",
+ "11": "0x22021448",
+ "12": "0x23028448",
+ "13": "0x23024448",
+ "14": "0x23022448",
+ "15": "0x23021448",
+ "16": "0x24028448",
+ "17": "0x24024448",
+ "18": "0x24022448",
+ "19": "0x24021448",
+ "20": "0x25028448",
+ "21": "0x25024448",
+ "22": "0x25022448",
+ "23": "0x25021448",
+ "24": "0x26028448",
+ "25": "0x26024448",
+ "26": "0x26022448",
+ "27": "0x26021448",
+ "28": "0x27028448",
+ "29": "0x27024448",
+ "30": "0x27022448",
+ "31": "0x27021448"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_CORE_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_WOF"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_WOF"
+ }
+ ]
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_CORE_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "IFU SRAM recoverable error (ICACHE parity error, etc)"
+ },
+ "1": {
+ "desc": "TC checkstop"
+ },
+ "2": {
+ "desc": "IFU RegFile recoverable error"
+ },
+ "3": {
+ "desc": "IFU RegFile core checkstop"
+ },
+ "4": {
+ "desc": "IFU logic recoverable error"
+ },
+ "5": {
+ "desc": "IFU logic core checkstop"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "VSU Inference Accumulator recoverable error"
+ },
+ "8": {
+ "desc": "Recovery core checkstop"
+ },
+ "9": {
+ "desc": "VSU Slice Targeted File (STF) recoverable error"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "ISU logic recoverable error"
+ },
+ "12": {
+ "desc": "ISU logic core checkstop"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "MCHK received while ME=0 - non recoverable"
+ },
+ "15": {
+ "desc": "UE from L2"
+ },
+ "16": {
+ "desc": "Number of UEs from L2 above threshold"
+ },
+ "17": {
+ "desc": "UE on CI load"
+ },
+ "18": {
+ "desc": "MMU TLB parity recoverable error"
+ },
+ "19": {
+ "desc": "MMU SLB parity recoverable error"
+ },
+ "20": {
+ "desc": "reserved"
+ },
+ "21": {
+ "desc": "MMU CXT recoverable error"
+ },
+ "22": {
+ "desc": "MMU logic core checkstop"
+ },
+ "23": {
+ "desc": "MMU system checkstop"
+ },
+ "24": {
+ "desc": "VSU logic recoverable error"
+ },
+ "25": {
+ "desc": "VSU logic core checkstop"
+ },
+ "26": {
+ "desc": "Thread in maintenance mode and receives recovery request"
+ },
+ "27": {
+ "desc": "reserved"
+ },
+ "28": {
+ "desc": "PC system checkstop - Recoverable error received when recovery disabled"
+ },
+ "29": {
+ "desc": "LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)"
+ },
+ "30": {
+ "desc": "LSU set deleted"
+ },
+ "31": {
+ "desc": "LSU RegFile recoverable error"
+ },
+ "32": {
+ "desc": "LSU RegFile core checkstop"
+ },
+ "33": {
+ "desc": "MMU TLB multi hit error occurred"
+ },
+ "34": {
+ "desc": "MMU SLB multi hit error occurred"
+ },
+ "35": {
+ "desc": "LSU ERAT multi hit error occurred"
+ },
+ "36": {
+ "desc": "PC forward progress error"
+ },
+ "37": {
+ "desc": "LSU logic recoverable error"
+ },
+ "38": {
+ "desc": "LSU logic core checkstop"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "LSU system checkstop"
+ },
+ "42": {
+ "desc": "reserved"
+ },
+ "43": {
+ "desc": "PC thread hang recoverable error"
+ },
+ "44": {
+ "desc": "reserved"
+ },
+ "45": {
+ "desc": "PC logic checkstop"
+ },
+ "46": {
+ "desc": "PC TimeBase Facility checkstop"
+ },
+ "47": {
+ "desc": "PC TimeBase Facility checkstop"
+ },
+ "48": {
+ "desc": "reserved"
+ },
+ "49": {
+ "desc": "reserved"
+ },
+ "50": {
+ "desc": "reserved"
+ },
+ "51": {
+ "desc": "reserved"
+ },
+ "52": {
+ "desc": "Hang Recovery Failed"
+ },
+ "53": {
+ "desc": "Core Hang detected"
+ },
+ "54": {
+ "desc": "reserved"
+ },
+ "55": {
+ "desc": "Nest Hang detected"
+ },
+ "56": {
+ "desc": "Other Core Chiplet recoverable error"
+ },
+ "57": {
+ "desc": "Other Core Chiplet core checkstop"
+ },
+ "58": {
+ "desc": "Other Core Chiplet system checkstop"
+ },
+ "59": {
+ "desc": "SCOM satellite error detected"
+ },
+ "60": {
+ "desc": "Debug Trigger error inject"
+ },
+ "61": {
+ "desc": "SCOM or Firmware recoverable error inject"
+ },
+ "62": {
+ "desc": "Firmware checkstop error inject"
+ },
+ "63": {
+ "desc": "PHYP checkstop via SPRC/SPRD"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_CORE_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_l2_fir.json b/chip_data/p10_20/node_eq_l2_fir.json
new file mode 100644
index 0000000..386edbf
--- /dev/null
+++ b/chip_data/p10_20/node_eq_l2_fir.json
@@ -0,0 +1,394 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_L2_FIR": {
+ "instances": {
+ "0": "0x20028000",
+ "1": "0x20024000",
+ "2": "0x20022000",
+ "3": "0x20021000",
+ "4": "0x21028000",
+ "5": "0x21024000",
+ "6": "0x21022000",
+ "7": "0x21021000",
+ "8": "0x22028000",
+ "9": "0x22024000",
+ "10": "0x22022000",
+ "11": "0x22021000",
+ "12": "0x23028000",
+ "13": "0x23024000",
+ "14": "0x23022000",
+ "15": "0x23021000",
+ "16": "0x24028000",
+ "17": "0x24024000",
+ "18": "0x24022000",
+ "19": "0x24021000",
+ "20": "0x25028000",
+ "21": "0x25024000",
+ "22": "0x25022000",
+ "23": "0x25021000",
+ "24": "0x26028000",
+ "25": "0x26024000",
+ "26": "0x26022000",
+ "27": "0x26021000",
+ "28": "0x27028000",
+ "29": "0x27024000",
+ "30": "0x27022000",
+ "31": "0x27021000"
+ }
+ },
+ "EQ_L2_FIR_MASK": {
+ "instances": {
+ "0": "0x20028003",
+ "1": "0x20024003",
+ "2": "0x20022003",
+ "3": "0x20021003",
+ "4": "0x21028003",
+ "5": "0x21024003",
+ "6": "0x21022003",
+ "7": "0x21021003",
+ "8": "0x22028003",
+ "9": "0x22024003",
+ "10": "0x22022003",
+ "11": "0x22021003",
+ "12": "0x23028003",
+ "13": "0x23024003",
+ "14": "0x23022003",
+ "15": "0x23021003",
+ "16": "0x24028003",
+ "17": "0x24024003",
+ "18": "0x24022003",
+ "19": "0x24021003",
+ "20": "0x25028003",
+ "21": "0x25024003",
+ "22": "0x25022003",
+ "23": "0x25021003",
+ "24": "0x26028003",
+ "25": "0x26024003",
+ "26": "0x26022003",
+ "27": "0x26021003",
+ "28": "0x27028003",
+ "29": "0x27024003",
+ "30": "0x27022003",
+ "31": "0x27021003"
+ }
+ },
+ "EQ_L2_FIR_ACT0": {
+ "instances": {
+ "0": "0x20028006",
+ "1": "0x20024006",
+ "2": "0x20022006",
+ "3": "0x20021006",
+ "4": "0x21028006",
+ "5": "0x21024006",
+ "6": "0x21022006",
+ "7": "0x21021006",
+ "8": "0x22028006",
+ "9": "0x22024006",
+ "10": "0x22022006",
+ "11": "0x22021006",
+ "12": "0x23028006",
+ "13": "0x23024006",
+ "14": "0x23022006",
+ "15": "0x23021006",
+ "16": "0x24028006",
+ "17": "0x24024006",
+ "18": "0x24022006",
+ "19": "0x24021006",
+ "20": "0x25028006",
+ "21": "0x25024006",
+ "22": "0x25022006",
+ "23": "0x25021006",
+ "24": "0x26028006",
+ "25": "0x26024006",
+ "26": "0x26022006",
+ "27": "0x26021006",
+ "28": "0x27028006",
+ "29": "0x27024006",
+ "30": "0x27022006",
+ "31": "0x27021006"
+ }
+ },
+ "EQ_L2_FIR_ACT1": {
+ "instances": {
+ "0": "0x20028007",
+ "1": "0x20024007",
+ "2": "0x20022007",
+ "3": "0x20021007",
+ "4": "0x21028007",
+ "5": "0x21024007",
+ "6": "0x21022007",
+ "7": "0x21021007",
+ "8": "0x22028007",
+ "9": "0x22024007",
+ "10": "0x22022007",
+ "11": "0x22021007",
+ "12": "0x23028007",
+ "13": "0x23024007",
+ "14": "0x23022007",
+ "15": "0x23021007",
+ "16": "0x24028007",
+ "17": "0x24024007",
+ "18": "0x24022007",
+ "19": "0x24021007",
+ "20": "0x25028007",
+ "21": "0x25024007",
+ "22": "0x25022007",
+ "23": "0x25021007",
+ "24": "0x26028007",
+ "25": "0x26024007",
+ "26": "0x26022007",
+ "27": "0x26021007",
+ "28": "0x27028007",
+ "29": "0x27024007",
+ "30": "0x27022007",
+ "31": "0x27021007"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_L2_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L2_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "L2 cache read CE"
+ },
+ "1": {
+ "desc": "L2 cache read UE"
+ },
+ "2": {
+ "desc": "L2 cache read SUE"
+ },
+ "3": {
+ "desc": "Hw directory initiated line delete"
+ },
+ "4": {
+ "desc": "UE or SUE detected by on modified line"
+ },
+ "5": {
+ "desc": "UE or SUE detected on non-modified line"
+ },
+ "6": {
+ "desc": "L2 directory read CE"
+ },
+ "7": {
+ "desc": "L2 directory read UE"
+ },
+ "8": {
+ "desc": "L2 directory CE due to stuck bit"
+ },
+ "9": {
+ "desc": "L2 directory stuck bit CE repair failed"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "LRU read error detected"
+ },
+ "12": {
+ "desc": "RC timed out waiting for powerbus to return data"
+ },
+ "13": {
+ "desc": "NCU timed out waiting for powerbus to return data"
+ },
+ "14": {
+ "desc": "Internal h/w control error"
+ },
+ "15": {
+ "desc": "LRU all members in a class line deleted"
+ },
+ "16": {
+ "desc": "Cache Inhibited Ld/St hit a line in the L2 cache"
+ },
+ "17": {
+ "desc": "(RC) load received pb cresp addr error"
+ },
+ "18": {
+ "desc": "(RC) store received pb cresp addr error"
+ },
+ "19": {
+ "desc": "RC incoming Power Bus data had a CE error"
+ },
+ "20": {
+ "desc": "RC incoming Power Bus data had a UE error"
+ },
+ "21": {
+ "desc": "RC incoming Power Bus data had a SUE error"
+ },
+ "22": {
+ "desc": "Targetted nodal request got rty_inc cresp"
+ },
+ "23": {
+ "desc": "RC fabric op Ld cresp addr error for hyp"
+ },
+ "24": {
+ "desc": "RCDAT read parity error"
+ },
+ "25": {
+ "desc": "L2 castout or CN cresp addr err"
+ },
+ "26": {
+ "desc": "LVDIR took a parity error"
+ },
+ "27": {
+ "desc": "Bad topology table config software error"
+ },
+ "28": {
+ "desc": "Darn timed out waiting for data"
+ },
+ "29": {
+ "desc": "Early hang in L2"
+ },
+ "30": {
+ "desc": "Unexpected cast-out or push during chip_contained"
+ },
+ "31": {
+ "desc": "reserved"
+ },
+ "32": {
+ "desc": "Time out during PEC sequence trying to correct l2dir error"
+ },
+ "33": {
+ "desc": "reserved"
+ },
+ "34": {
+ "desc": "reserved"
+ },
+ "35": {
+ "desc": "reserved"
+ },
+ "36": {
+ "desc": "Cache CE and UE in short time period"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_L2_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_l3_fir.json b/chip_data/p10_20/node_eq_l3_fir.json
new file mode 100644
index 0000000..784111b
--- /dev/null
+++ b/chip_data/p10_20/node_eq_l3_fir.json
@@ -0,0 +1,373 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_L3_FIR": {
+ "instances": {
+ "0": "0x20018600",
+ "1": "0x20014600",
+ "2": "0x20012600",
+ "3": "0x20011600",
+ "4": "0x21018600",
+ "5": "0x21014600",
+ "6": "0x21012600",
+ "7": "0x21011600",
+ "8": "0x22018600",
+ "9": "0x22014600",
+ "10": "0x22012600",
+ "11": "0x22011600",
+ "12": "0x23018600",
+ "13": "0x23014600",
+ "14": "0x23012600",
+ "15": "0x23011600",
+ "16": "0x24018600",
+ "17": "0x24014600",
+ "18": "0x24012600",
+ "19": "0x24011600",
+ "20": "0x25018600",
+ "21": "0x25014600",
+ "22": "0x25012600",
+ "23": "0x25011600",
+ "24": "0x26018600",
+ "25": "0x26014600",
+ "26": "0x26012600",
+ "27": "0x26011600",
+ "28": "0x27018600",
+ "29": "0x27014600",
+ "30": "0x27012600",
+ "31": "0x27011600"
+ }
+ },
+ "EQ_L3_FIR_MASK": {
+ "instances": {
+ "0": "0x20018603",
+ "1": "0x20014603",
+ "2": "0x20012603",
+ "3": "0x20011603",
+ "4": "0x21018603",
+ "5": "0x21014603",
+ "6": "0x21012603",
+ "7": "0x21011603",
+ "8": "0x22018603",
+ "9": "0x22014603",
+ "10": "0x22012603",
+ "11": "0x22011603",
+ "12": "0x23018603",
+ "13": "0x23014603",
+ "14": "0x23012603",
+ "15": "0x23011603",
+ "16": "0x24018603",
+ "17": "0x24014603",
+ "18": "0x24012603",
+ "19": "0x24011603",
+ "20": "0x25018603",
+ "21": "0x25014603",
+ "22": "0x25012603",
+ "23": "0x25011603",
+ "24": "0x26018603",
+ "25": "0x26014603",
+ "26": "0x26012603",
+ "27": "0x26011603",
+ "28": "0x27018603",
+ "29": "0x27014603",
+ "30": "0x27012603",
+ "31": "0x27011603"
+ }
+ },
+ "EQ_L3_FIR_ACT0": {
+ "instances": {
+ "0": "0x20018606",
+ "1": "0x20014606",
+ "2": "0x20012606",
+ "3": "0x20011606",
+ "4": "0x21018606",
+ "5": "0x21014606",
+ "6": "0x21012606",
+ "7": "0x21011606",
+ "8": "0x22018606",
+ "9": "0x22014606",
+ "10": "0x22012606",
+ "11": "0x22011606",
+ "12": "0x23018606",
+ "13": "0x23014606",
+ "14": "0x23012606",
+ "15": "0x23011606",
+ "16": "0x24018606",
+ "17": "0x24014606",
+ "18": "0x24012606",
+ "19": "0x24011606",
+ "20": "0x25018606",
+ "21": "0x25014606",
+ "22": "0x25012606",
+ "23": "0x25011606",
+ "24": "0x26018606",
+ "25": "0x26014606",
+ "26": "0x26012606",
+ "27": "0x26011606",
+ "28": "0x27018606",
+ "29": "0x27014606",
+ "30": "0x27012606",
+ "31": "0x27011606"
+ }
+ },
+ "EQ_L3_FIR_ACT1": {
+ "instances": {
+ "0": "0x20018607",
+ "1": "0x20014607",
+ "2": "0x20012607",
+ "3": "0x20011607",
+ "4": "0x21018607",
+ "5": "0x21014607",
+ "6": "0x21012607",
+ "7": "0x21011607",
+ "8": "0x22018607",
+ "9": "0x22014607",
+ "10": "0x22012607",
+ "11": "0x22011607",
+ "12": "0x23018607",
+ "13": "0x23014607",
+ "14": "0x23012607",
+ "15": "0x23011607",
+ "16": "0x24018607",
+ "17": "0x24014607",
+ "18": "0x24012607",
+ "19": "0x24011607",
+ "20": "0x25018607",
+ "21": "0x25014607",
+ "22": "0x25012607",
+ "23": "0x25011607",
+ "24": "0x26018607",
+ "25": "0x26014607",
+ "26": "0x26012607",
+ "27": "0x26011607",
+ "28": "0x27018607",
+ "29": "0x27014607",
+ "30": "0x27012607",
+ "31": "0x27011607"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_L3_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "No members available for a CGC"
+ },
+ "1": {
+ "desc": "L3 attempted to master a CP (Castout/Push) command"
+ },
+ "2": {
+ "desc": "Access attempted to use invalid topology table entry"
+ },
+ "3": {
+ "desc": "L3 cache CE and UE within a short period"
+ },
+ "4": {
+ "desc": "CE detected on L3 cache read"
+ },
+ "5": {
+ "desc": "UE detected on L3 cache read"
+ },
+ "6": {
+ "desc": "SUE detected on L3 cache read"
+ },
+ "7": {
+ "desc": "L3 cache write data CE from Power Bus"
+ },
+ "8": {
+ "desc": "L3 cache write data UE from Power Bus"
+ },
+ "9": {
+ "desc": "L3 cache write data sue from Power Bus"
+ },
+ "10": {
+ "desc": "L3 cache write data CE from L2"
+ },
+ "11": {
+ "desc": "L3 cache write data UE from L2"
+ },
+ "12": {
+ "desc": "L3 cache write SUE from L2"
+ },
+ "13": {
+ "desc": "L3 DIR read CE"
+ },
+ "14": {
+ "desc": "L3 Dir read UE"
+ },
+ "15": {
+ "desc": "Dir error not found during corr seq"
+ },
+ "16": {
+ "desc": "Received addr_error cresp on Snoop Machine or Castout Operation"
+ },
+ "17": {
+ "desc": "Received addr_error cresp for Prefetch Operation"
+ },
+ "18": {
+ "desc": "L3_PB_HANG_POLL"
+ },
+ "19": {
+ "desc": "Invalid LRU count error"
+ },
+ "20": {
+ "desc": "Reserved"
+ },
+ "21": {
+ "desc": "Reserved"
+ },
+ "22": {
+ "desc": "Reserved"
+ },
+ "23": {
+ "desc": "Prefetch or Write Inject machine PowerBus data hang check"
+ },
+ "24": {
+ "desc": "L3 Hw control err"
+ },
+ "25": {
+ "desc": "Cache inhibited op in L3 directory"
+ },
+ "26": {
+ "desc": "L3 line delete CE done"
+ },
+ "27": {
+ "desc": "L3 snooped an incoming LCO"
+ },
+ "28": {
+ "desc": "LRU intended to victimize a line, but invalid line selected"
+ },
+ "29": {
+ "desc": "L3 cache congruence class deleted"
+ },
+ "30": {
+ "desc": "Incoming LCO ID mismatch"
+ },
+ "31": {
+ "desc": "L3 PowerBus Master Write CRESP ack_dead"
+ },
+ "32": {
+ "desc": "PB Master Read received ack_dead CRESP"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_L3_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_local_fir.json b/chip_data/p10_20/node_eq_local_fir.json
new file mode 100644
index 0000000..284bf4a
--- /dev/null
+++ b/chip_data/p10_20/node_eq_local_fir.json
@@ -0,0 +1,469 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_LOCAL_FIR": {
+ "instances": {
+ "0": "0x20040100",
+ "1": "0x21040100",
+ "2": "0x22040100",
+ "3": "0x23040100",
+ "4": "0x24040100",
+ "5": "0x25040100",
+ "6": "0x26040100",
+ "7": "0x27040100"
+ }
+ },
+ "EQ_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x20040103",
+ "1": "0x21040103",
+ "2": "0x22040103",
+ "3": "0x23040103",
+ "4": "0x24040103",
+ "5": "0x25040103",
+ "6": "0x26040103",
+ "7": "0x27040103"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x20040106",
+ "1": "0x21040106",
+ "2": "0x22040106",
+ "3": "0x23040106",
+ "4": "0x24040106",
+ "5": "0x25040106",
+ "6": "0x26040106",
+ "7": "0x27040106"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x20040107",
+ "1": "0x21040107",
+ "2": "0x22040107",
+ "3": "0x23040107",
+ "4": "0x24040107",
+ "5": "0x25040107",
+ "6": "0x26040107",
+ "7": "0x27040107"
+ }
+ },
+ "EQ_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x20040109",
+ "1": "0x21040109",
+ "2": "0x22040109",
+ "3": "0x23040109",
+ "4": "0x24040109",
+ "5": "0x25040109",
+ "6": "0x26040109",
+ "7": "0x27040109"
+ }
+ },
+ "EQ_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x20040108",
+ "1": "0x21040108",
+ "2": "0x22040108",
+ "3": "0x23040108",
+ "4": "0x24040108",
+ "5": "0x25040108",
+ "6": "0x26040108",
+ "7": "0x27040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM1 - internal error"
+ },
+ "7": {
+ "desc": "THERM1 - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP1 - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP1 - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP1 - Voltage sense error"
+ },
+ "11": {
+ "desc": "THERM2 - internal error"
+ },
+ "12": {
+ "desc": "THERM2 - pcb error"
+ },
+ "13": {
+ "desc": "THERMTRIP2 - Critical temperature indicator"
+ },
+ "14": {
+ "desc": "THERMTRIP2 - Fatal temperature indicator"
+ },
+ "15": {
+ "desc": "VOLTTRIP2 - Voltage sense error"
+ },
+ "16": {
+ "desc": "DBG - scom parity fail"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "L30 Trace Err"
+ },
+ "21": {
+ "desc": "L31 Trace Err"
+ },
+ "22": {
+ "desc": "L32 Trace Err"
+ },
+ "23": {
+ "desc": "L33 Trace Err"
+ },
+ "24": {
+ "desc": "DCADJ FIR ERR Core 0"
+ },
+ "25": {
+ "desc": "DCADJ FIR ERR Core 1"
+ },
+ "26": {
+ "desc": "DCADJ FIR ERR Core 2"
+ },
+ "27": {
+ "desc": "DCADJ FIR ERR Core 3"
+ },
+ "28": {
+ "desc": "SKEWADJ FIR ERR Core0"
+ },
+ "29": {
+ "desc": "SKEWADJ FIR ERR Core1"
+ },
+ "30": {
+ "desc": "SKEWADJ FIR ERR Core2"
+ },
+ "31": {
+ "desc": "SKEWADJ FIR ERR Core3"
+ },
+ "32": {
+ "desc": "DC_SCOM_ERR_0"
+ },
+ "33": {
+ "desc": "DC_SCOM_ERR_1"
+ },
+ "34": {
+ "desc": "DC_SCOM_ERR_2"
+ },
+ "35": {
+ "desc": "DC_SCOM_ERR_3"
+ },
+ "36": {
+ "desc": "SKEW_SCOM_ERR_0"
+ },
+ "37": {
+ "desc": "SKEW_SCOM_ERR_1"
+ },
+ "38": {
+ "desc": "SKEW_SCOM_ERR_2"
+ },
+ "39": {
+ "desc": "SKEW_SCOM_ERR_3"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_ncu_fir.json b/chip_data/p10_20/node_eq_ncu_fir.json
new file mode 100644
index 0000000..63e9bd8
--- /dev/null
+++ b/chip_data/p10_20/node_eq_ncu_fir.json
@@ -0,0 +1,361 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_NCU_FIR": {
+ "instances": {
+ "0": "0x20018640",
+ "1": "0x20014640",
+ "2": "0x20012640",
+ "3": "0x20011640",
+ "4": "0x21018640",
+ "5": "0x21014640",
+ "6": "0x21012640",
+ "7": "0x21011640",
+ "8": "0x22018640",
+ "9": "0x22014640",
+ "10": "0x22012640",
+ "11": "0x22011640",
+ "12": "0x23018640",
+ "13": "0x23014640",
+ "14": "0x23012640",
+ "15": "0x23011640",
+ "16": "0x24018640",
+ "17": "0x24014640",
+ "18": "0x24012640",
+ "19": "0x24011640",
+ "20": "0x25018640",
+ "21": "0x25014640",
+ "22": "0x25012640",
+ "23": "0x25011640",
+ "24": "0x26018640",
+ "25": "0x26014640",
+ "26": "0x26012640",
+ "27": "0x26011640",
+ "28": "0x27018640",
+ "29": "0x27014640",
+ "30": "0x27012640",
+ "31": "0x27011640"
+ }
+ },
+ "EQ_NCU_FIR_MASK": {
+ "instances": {
+ "0": "0x20018643",
+ "1": "0x20014643",
+ "2": "0x20012643",
+ "3": "0x20011643",
+ "4": "0x21018643",
+ "5": "0x21014643",
+ "6": "0x21012643",
+ "7": "0x21011643",
+ "8": "0x22018643",
+ "9": "0x22014643",
+ "10": "0x22012643",
+ "11": "0x22011643",
+ "12": "0x23018643",
+ "13": "0x23014643",
+ "14": "0x23012643",
+ "15": "0x23011643",
+ "16": "0x24018643",
+ "17": "0x24014643",
+ "18": "0x24012643",
+ "19": "0x24011643",
+ "20": "0x25018643",
+ "21": "0x25014643",
+ "22": "0x25012643",
+ "23": "0x25011643",
+ "24": "0x26018643",
+ "25": "0x26014643",
+ "26": "0x26012643",
+ "27": "0x26011643",
+ "28": "0x27018643",
+ "29": "0x27014643",
+ "30": "0x27012643",
+ "31": "0x27011643"
+ }
+ },
+ "EQ_NCU_FIR_ACT0": {
+ "instances": {
+ "0": "0x20018646",
+ "1": "0x20014646",
+ "2": "0x20012646",
+ "3": "0x20011646",
+ "4": "0x21018646",
+ "5": "0x21014646",
+ "6": "0x21012646",
+ "7": "0x21011646",
+ "8": "0x22018646",
+ "9": "0x22014646",
+ "10": "0x22012646",
+ "11": "0x22011646",
+ "12": "0x23018646",
+ "13": "0x23014646",
+ "14": "0x23012646",
+ "15": "0x23011646",
+ "16": "0x24018646",
+ "17": "0x24014646",
+ "18": "0x24012646",
+ "19": "0x24011646",
+ "20": "0x25018646",
+ "21": "0x25014646",
+ "22": "0x25012646",
+ "23": "0x25011646",
+ "24": "0x26018646",
+ "25": "0x26014646",
+ "26": "0x26012646",
+ "27": "0x26011646",
+ "28": "0x27018646",
+ "29": "0x27014646",
+ "30": "0x27012646",
+ "31": "0x27011646"
+ }
+ },
+ "EQ_NCU_FIR_ACT1": {
+ "instances": {
+ "0": "0x20018647",
+ "1": "0x20014647",
+ "2": "0x20012647",
+ "3": "0x20011647",
+ "4": "0x21018647",
+ "5": "0x21014647",
+ "6": "0x21012647",
+ "7": "0x21011647",
+ "8": "0x22018647",
+ "9": "0x22014647",
+ "10": "0x22012647",
+ "11": "0x22011647",
+ "12": "0x23018647",
+ "13": "0x23014647",
+ "14": "0x23012647",
+ "15": "0x23011647",
+ "16": "0x24018647",
+ "17": "0x24014647",
+ "18": "0x24012647",
+ "19": "0x24011647",
+ "20": "0x25018647",
+ "21": "0x25014647",
+ "22": "0x25012647",
+ "23": "0x25011647",
+ "24": "0x26018647",
+ "25": "0x26014647",
+ "26": "0x26012647",
+ "27": "0x26011647",
+ "28": "0x27018647",
+ "29": "0x27014647",
+ "30": "0x27012647",
+ "31": "0x27011647"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_NCU_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_NCU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NCU store queue control error"
+ },
+ "1": {
+ "desc": "TLBIE control error"
+ },
+ "2": {
+ "desc": "TLBIE or SLBIEG received illegal fields from core"
+ },
+ "3": {
+ "desc": "Store address machine received addr_err cresp"
+ },
+ "4": {
+ "desc": "Load address machine received addr_err cresp"
+ },
+ "5": {
+ "desc": "Topology table error - tried accessing invalid entry"
+ },
+ "6": {
+ "desc": "An NCU machine triggerd PB into early hang recovery"
+ },
+ "7": {
+ "desc": "MSGSND received addr_err"
+ },
+ "8": {
+ "desc": "Store data parity error from regfile detected"
+ },
+ "9": {
+ "desc": "Store timed out on PB"
+ },
+ "10": {
+ "desc": "TLBIE master timed out on PB"
+ },
+ "11": {
+ "desc": "TLBIE snooper timed out waiting for core"
+ },
+ "12": {
+ "desc": "IMA received addr_err cresp"
+ },
+ "13": {
+ "desc": "TLBIE/sync machine received addr_err cresp"
+ },
+ "14": {
+ "desc": "PMISC received address error cresp"
+ },
+ "15": {
+ "desc": "cHTM logic recieve an HTM/IMA packet"
+ },
+ "16": {
+ "desc": "spare"
+ },
+ "17": {
+ "desc": "spare"
+ },
+ "18": {
+ "desc": "spare"
+ },
+ "19": {
+ "desc": "Targeted nodal request got rty_inc cresp"
+ },
+ "20": {
+ "desc": "Darn ttype while darn not enabled"
+ },
+ "21": {
+ "desc": "Darn Address Error cresp"
+ },
+ "22": {
+ "desc": "spare"
+ },
+ "23": {
+ "desc": "spare"
+ },
+ "24": {
+ "desc": "spare"
+ },
+ "25": {
+ "desc": "spare"
+ },
+ "26": {
+ "desc": "spare"
+ },
+ "27": {
+ "desc": "spare"
+ },
+ "28": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_NCU_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_eq_qme_fir.json b/chip_data/p10_20/node_eq_qme_fir.json
new file mode 100644
index 0000000..4621453
--- /dev/null
+++ b/chip_data/p10_20/node_eq_qme_fir.json
@@ -0,0 +1,236 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "EQ_QME_FIR": {
+ "instances": {
+ "0": "0x200E0000",
+ "1": "0x210E0000",
+ "2": "0x220E0000",
+ "3": "0x230E0000",
+ "4": "0x240E0000",
+ "5": "0x250E0000",
+ "6": "0x260E0000",
+ "7": "0x270E0000"
+ }
+ },
+ "EQ_QME_FIR_MASK": {
+ "instances": {
+ "0": "0x200E0004",
+ "1": "0x210E0004",
+ "2": "0x220E0004",
+ "3": "0x230E0004",
+ "4": "0x240E0004",
+ "5": "0x250E0004",
+ "6": "0x260E0004",
+ "7": "0x270E0004"
+ }
+ },
+ "EQ_QME_FIR_ACT0": {
+ "instances": {
+ "0": "0x200E0008",
+ "1": "0x210E0008",
+ "2": "0x220E0008",
+ "3": "0x230E0008",
+ "4": "0x240E0008",
+ "5": "0x250E0008",
+ "6": "0x260E0008",
+ "7": "0x270E0008"
+ }
+ },
+ "EQ_QME_FIR_ACT1": {
+ "instances": {
+ "0": "0x200E000C",
+ "1": "0x210E000C",
+ "2": "0x220E000C",
+ "3": "0x230E000C",
+ "4": "0x240E000C",
+ "5": "0x250E000C",
+ "6": "0x260E000C",
+ "7": "0x270E000C"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_QME_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_QME_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PPE halted due to an error"
+ },
+ "1": {
+ "desc": "PPE asserted debug trigger"
+ },
+ "2": {
+ "desc": "Spare trigger for testing or workarounds"
+ },
+ "3": {
+ "desc": "PPE asserted a watchdog timeout condition"
+ },
+ "4": {
+ "desc": "QME hardware detected its own timeout on the PCB Slave interface"
+ },
+ "5": {
+ "desc": "Block Copy Engine or QME PPE direct access error from the Fabric"
+ },
+ "6": {
+ "desc": "SRAM Uncorrectable Error"
+ },
+ "7": {
+ "desc": "SRAM Correctable Error"
+ },
+ "8": {
+ "desc": "Resonant Clock Table array Parity Error"
+ },
+ "9": {
+ "desc": "PIG request of PCB interrupt before its previous interrupt completed"
+ },
+ "10": {
+ "desc": "Scrub timer tick occurred when scrub is still pending"
+ },
+ "11": {
+ "desc": "QME_LFIR_CTFS_ERR"
+ },
+ "12": {
+ "desc": "QME_LFIR_CPMS_ERR"
+ },
+ "13": {
+ "desc": "PGPE Heartbeat Lost from a hw deadman timer controlled by QHB"
+ },
+ "14": {
+ "desc": "BCE forward progress error"
+ },
+ "15": {
+ "desc": "Resclk TARGET_PSTATE Change Protocol Error"
+ },
+ "16": {
+ "desc": "PCB Network or Endpoint Reset occurred when QME was not halted"
+ },
+ "17": {
+ "desc": "Firmware cleared special wakeup request before SPECIAL_WKUP_DONE"
+ },
+ "18": {
+ "desc": "A new special wakeup right after previous cleared"
+ },
+ "19": {
+ "desc": "Core External Interrupt wakeup sources present but disabled by threads"
+ },
+ "20": {
+ "desc": "Core External Interrupt present but the chiplet is deconfigured"
+ },
+ "21": {
+ "desc": "Reserved"
+ },
+ "22": {
+ "desc": "PB read cmd waited too long for lost data (hang)"
+ },
+ "23": {
+ "desc": "PPE tried to write a protected addr as defined by the SWPR[n] register"
+ },
+ "24": {
+ "desc": "DTC Sequencer read a UE from SRAM"
+ },
+ "25": {
+ "desc": "Correctable error detected on incoming data for a PowerBus read"
+ },
+ "26": {
+ "desc": "UE Detected on incoming data for a PowerBus read"
+ },
+ "27": {
+ "desc": "SUE Detected on incoming data for a PowerBus read"
+ },
+ "28": {
+ "desc": "PB Request address hit an invalid entry in the TOPOLOGY XLATE TABLE"
+ },
+ "29": {
+ "desc": "Parity error detected on a powerbus tag"
+ },
+ "30": {
+ "desc": "Code attempted to write the PIG register when the previous request was still pending"
+ },
+ "31": {
+ "desc": "Local access error bit(s) set"
+ },
+ "32": {
+ "desc": "CE detected on read to the SSA located in QME powerbus routing logic"
+ },
+ "33": {
+ "desc": "UE detected on read to the SSA located in QME powerbus routing logic"
+ },
+ "34": {
+ "desc": "Resonant clock CCFG parity error"
+ },
+ "35": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_gfir.json b/chip_data/p10_20/node_gfir.json
new file mode 100644
index 0000000..4b8c933
--- /dev/null
+++ b/chip_data/p10_20/node_gfir.json
@@ -0,0 +1,1435 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "GFIR_CS": {
+ "instances": {
+ "0": "0x570F001C"
+ }
+ },
+ "GFIR_RE": {
+ "instances": {
+ "0": "0x570F001B"
+ }
+ },
+ "GFIR_SPA": {
+ "instances": {
+ "0": "0x570F001A"
+ }
+ },
+ "GFIR_UCS": {
+ "instances": {
+ "0": "0x570F002A"
+ }
+ },
+ "GFIR_HA": {
+ "instances": {
+ "0": "0x570F002B"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "GFIR_CS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_CS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_CS",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_CS",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_RE": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_RE"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_RE",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_RE",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_SPA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_SPA"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_SPA",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_SPA",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_UCS": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_UCS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_UCS",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_UCS",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ },
+ "GFIR_HA": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_HA"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "Attention from N0 chiplet",
+ "child_node": {
+ "name": "CFIR_N0_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "Attention from N1 chiplet",
+ "child_node": {
+ "name": "CFIR_N1_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from PCI chiplet",
+ "child_node": {
+ "name": "CFIR_PCI_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "12": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "15": {
+ "desc": "Attention from MC chiplet",
+ "child_node": {
+ "name": "CFIR_MC_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "17": {
+ "desc": "Attention from PAUE chiplet",
+ "child_node": {
+ "name": "CFIR_PAUE_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "18": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "19": {
+ "desc": "Attention from PAUW chiplet",
+ "child_node": {
+ "name": "CFIR_PAUW_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "24": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "25": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "26": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "27": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "29": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "30": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "31": {
+ "desc": "Attention from IOHS chiplet",
+ "child_node": {
+ "name": "CFIR_IOHS_HA",
+ "inst": {
+ "0": 7
+ }
+ }
+ },
+ "32": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "33": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "34": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 2
+ }
+ }
+ },
+ "35": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 3
+ }
+ }
+ },
+ "36": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 4
+ }
+ }
+ },
+ "37": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 5
+ }
+ }
+ },
+ "38": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 6
+ }
+ }
+ },
+ "39": {
+ "desc": "Attention from EQ chiplet",
+ "child_node": {
+ "name": "CFIR_EQ_HA",
+ "inst": {
+ "0": 7
+ }
+ }
+ }
+ }
+ }
+ },
+ "root_nodes": {
+ "CS": {
+ "name": "GFIR_CS",
+ "inst": 0
+ },
+ "RE": {
+ "name": "GFIR_RE",
+ "inst": 0
+ },
+ "SPA": {
+ "name": "GFIR_SPA",
+ "inst": 0
+ },
+ "UCS": {
+ "name": "GFIR_UCS",
+ "inst": 0
+ },
+ "HA": {
+ "name": "GFIR_HA",
+ "inst": 0
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_hca_fir.json b/chip_data/p10_20/node_hca_fir.json
new file mode 100644
index 0000000..9d98d7a
--- /dev/null
+++ b/chip_data/p10_20/node_hca_fir.json
@@ -0,0 +1,197 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "HCA_FIR": {
+ "instances": {
+ "0": "0x03011D40"
+ }
+ },
+ "HCA_FIR_MASK": {
+ "instances": {
+ "0": "0x03011D43"
+ }
+ },
+ "HCA_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011D46"
+ }
+ },
+ "HCA_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011D47"
+ }
+ },
+ "HCA_FIR_WOF": {
+ "instances": {
+ "0": "0x03011D48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "HCA_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "HCA_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Powerbus rcmd address parity error"
+ },
+ "1": {
+ "desc": "Powerbus rcmd ttag parity error"
+ },
+ "2": {
+ "desc": "Powerbus cresp ttag parity error"
+ },
+ "3": {
+ "desc": "Powerbus cresp atag parity error"
+ },
+ "4": {
+ "desc": "HCA updt received addr_err cresp"
+ },
+ "5": {
+ "desc": "HCA updt received invalid cresp"
+ },
+ "6": {
+ "desc": "HCA updt received unexpected cresp"
+ },
+ "7": {
+ "desc": "HCA detected powerbus hang"
+ },
+ "8": {
+ "desc": "HCA rcmd hits both BARs"
+ },
+ "9": {
+ "desc": "HCA cache array correctable error"
+ },
+ "10": {
+ "desc": "HCA cache array uncorrectable error"
+ },
+ "11": {
+ "desc": "HCA rcmd drop counter overflow"
+ },
+ "12": {
+ "desc": "HCA updt command drop counter overflow"
+ },
+ "13": {
+ "desc": "HCA updt lost decay request. No pbi machine available."
+ },
+ "14": {
+ "desc": "ADU or PSI SMF error"
+ },
+ "15": {
+ "desc": "Spare FIR bit"
+ },
+ "16": {
+ "desc": "ADU recoverable error 0"
+ },
+ "17": {
+ "desc": "ADU recoverable error 1"
+ },
+ "18": {
+ "desc": "ADU recoverable error 2"
+ },
+ "19": {
+ "desc": "ADU recoverable error 3"
+ },
+ "20": {
+ "desc": "ADU recoverable error 4"
+ },
+ "21": {
+ "desc": "ADU recoverable error 5"
+ },
+ "22": {
+ "desc": "ADU checkstop error 0"
+ },
+ "23": {
+ "desc": "ADU checkstop error 1"
+ },
+ "24": {
+ "desc": "ADU checkstop error 2"
+ },
+ "25": {
+ "desc": "ADU checkstop error 3"
+ },
+ "26": {
+ "desc": "ADU checkstop error 4"
+ },
+ "27": {
+ "desc": "ADU checkstop error 5"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "HCA_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_int_cq_fir.json b/chip_data/p10_20/node_int_cq_fir.json
new file mode 100644
index 0000000..1bf2fd1
--- /dev/null
+++ b/chip_data/p10_20/node_int_cq_fir.json
@@ -0,0 +1,336 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "INT_CQ_FIR": {
+ "instances": {
+ "0": "0x02010830"
+ }
+ },
+ "INT_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02010833"
+ }
+ },
+ "INT_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010836"
+ }
+ },
+ "INT_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010837"
+ }
+ },
+ "INT_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02010838"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "INT_CQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "INT_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CE while consuming data from the PowerBus Data ramp"
+ },
+ "1": {
+ "desc": "UE while consuming data from the PowerBus Data ramp"
+ },
+ "2": {
+ "desc": "SUE while consuming data from the PowerBus Data ramp"
+ },
+ "3": {
+ "desc": "CE while reading the PowerBus Data In Array"
+ },
+ "4": {
+ "desc": "UE detected while reading the PowerBus Data In Array"
+ },
+ "5": {
+ "desc": "CE while reading the PowerBus Data Out Array"
+ },
+ "6": {
+ "desc": "UE while reading the PowerBus Data Out Array"
+ },
+ "7": {
+ "desc": "CE while consuming data on the AIB Data Bus"
+ },
+ "8": {
+ "desc": "UE while consuming data on the AIB Data Bus"
+ },
+ "9": {
+ "desc": "Received an unsolicited master Combined Response"
+ },
+ "10": {
+ "desc": "Received unsolicited PowerBus data"
+ },
+ "11": {
+ "desc": "Parity error detected on AIB credit signals from PC"
+ },
+ "12": {
+ "desc": "Parity error detected on AIB credit available signals from PC"
+ },
+ "13": {
+ "desc": "Parity error detected on AIB credit signals from VC"
+ },
+ "14": {
+ "desc": "Parity error detected on AIB credit available signals from VC"
+ },
+ "15": {
+ "desc": "Parity error detected on AIB Command Control"
+ },
+ "16": {
+ "desc": "Parity error detected on AIB Command Bus"
+ },
+ "17": {
+ "desc": "Parity error detected on AIB Data Control"
+ },
+ "18": {
+ "desc": "Parity err detected in a PowerBus interface(Rcmdx, cRespx, Data rtag)"
+ },
+ "19": {
+ "desc": "Slave CI Store or CI Load to an improper location"
+ },
+ "20": {
+ "desc": "Slave CI Store or CI Load to an invalid Set Translation Table entry"
+ },
+ "21": {
+ "desc": "Slave CI Store or CI Load error (targeting IC_BAR)"
+ },
+ "22": {
+ "desc": "Slave CI Store or CI Load error (not targetting IC_BAR)"
+ },
+ "23": {
+ "desc": "Migration Register Table (MRT) access - invalid entry selected"
+ },
+ "24": {
+ "desc": "Migration Register Table (MRT) access - size error"
+ },
+ "25": {
+ "desc": "SCOM satellite error"
+ },
+ "26": {
+ "desc": "Topology ID Index Translation Table Entry Invalid"
+ },
+ "27": {
+ "desc": "Master Write Queue has flagged a PowerBus operational hang"
+ },
+ "28": {
+ "desc": "Master Read Queue has flagged a PowerBus operational hang"
+ },
+ "29": {
+ "desc": "Master Interrupt Queue has flagged a PowerBus operational hang"
+ },
+ "30": {
+ "desc": "Master Read Queue has flagged a PowerBus data hang"
+ },
+ "31": {
+ "desc": "CI Store Queue has flagged a PowerBus data hang"
+ },
+ "32": {
+ "desc": "CI Load Queue has flagged an AIB data hang"
+ },
+ "33": {
+ "desc": "Bad cResp received during a Master Write command"
+ },
+ "34": {
+ "desc": "Bad cResp received during a Master Read command"
+ },
+ "35": {
+ "desc": "Bad cResp received during a Master Interrupt command"
+ },
+ "36": {
+ "desc": "A Master Read machine received cResp of abort_trm or abort_trm_ed"
+ },
+ "37": {
+ "desc": "Master Interrupt Protocol Error"
+ },
+ "38": {
+ "desc": "Master Memory Op Targeted Secure Memory"
+ },
+ "39": {
+ "desc": "AIB Fence Raised"
+ },
+ "40": {
+ "desc": "Parity error detected on CQs configuration registers"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "Command Queue (FSM) severe error summary"
+ },
+ "43": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "44": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "45": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "46": {
+ "desc": "PC fatal error summary, as indicated on pc_cq_fatal_error(0:3)"
+ },
+ "47": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "48": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "49": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "50": {
+ "desc": "PC recoverable error summary, as indicated on pc_cq_recov_error(0:3)"
+ },
+ "51": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "52": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "53": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "54": {
+ "desc": "PC informational error summary, as indicated on pc_cq_info_error(0:3)"
+ },
+ "55": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "56": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "57": {
+ "desc": "VC fatal error summary, as indicated on vc_cq_fatal_error(0:2)"
+ },
+ "58": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "59": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "60": {
+ "desc": "VC recoverable error summary, as indicated on vc_cq_recov_error(0:2)"
+ },
+ "61": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ },
+ "62": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ },
+ "63": {
+ "desc": "VC informational error summary, as indicated on vc_cq_info_error(0:2)"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "INT_CQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_iohs_local_fir.json b/chip_data/p10_20/node_iohs_local_fir.json
new file mode 100644
index 0000000..93c94ae
--- /dev/null
+++ b/chip_data/p10_20/node_iohs_local_fir.json
@@ -0,0 +1,469 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "IOHS_LOCAL_FIR": {
+ "instances": {
+ "0": "0x18040100",
+ "1": "0x19040100",
+ "2": "0x1A040100",
+ "3": "0x1B040100",
+ "4": "0x1C040100",
+ "5": "0x1D040100",
+ "6": "0x1E040100",
+ "7": "0x1F040100"
+ }
+ },
+ "IOHS_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x18040103",
+ "1": "0x19040103",
+ "2": "0x1A040103",
+ "3": "0x1B040103",
+ "4": "0x1C040103",
+ "5": "0x1D040103",
+ "6": "0x1E040103",
+ "7": "0x1F040103"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x18040106",
+ "1": "0x19040106",
+ "2": "0x1A040106",
+ "3": "0x1B040106",
+ "4": "0x1C040106",
+ "5": "0x1D040106",
+ "6": "0x1E040106",
+ "7": "0x1F040106"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x18040107",
+ "1": "0x19040107",
+ "2": "0x1A040107",
+ "3": "0x1B040107",
+ "4": "0x1C040107",
+ "5": "0x1D040107",
+ "6": "0x1E040107",
+ "7": "0x1F040107"
+ }
+ },
+ "IOHS_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x18040109",
+ "1": "0x19040109",
+ "2": "0x1A040109",
+ "3": "0x1B040109",
+ "4": "0x1C040109",
+ "5": "0x1D040109",
+ "6": "0x1E040109",
+ "7": "0x1F040109"
+ }
+ },
+ "IOHS_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x18040108",
+ "1": "0x19040108",
+ "2": "0x1A040108",
+ "3": "0x1B040108",
+ "4": "0x1C040108",
+ "5": "0x1D040108",
+ "6": "0x1E040108",
+ "7": "0x1F040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "IOHS_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "IOHS_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - interal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_lpc_fir.json b/chip_data/p10_20/node_lpc_fir.json
new file mode 100644
index 0000000..bd234ff
--- /dev/null
+++ b/chip_data/p10_20/node_lpc_fir.json
@@ -0,0 +1,135 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "LPC_FIR": {
+ "instances": {
+ "0": "0x03012000"
+ }
+ },
+ "LPC_FIR_MASK": {
+ "instances": {
+ "0": "0x03012003"
+ }
+ },
+ "LPC_FIR_ACT0": {
+ "instances": {
+ "0": "0x03012006"
+ }
+ },
+ "LPC_FIR_ACT1": {
+ "instances": {
+ "0": "0x03012007"
+ }
+ },
+ "LPC_FIR_WOF": {
+ "instances": {
+ "0": "0x03012008"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "LPC_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "LPC_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OPB_Master_LS_received_a_transfer_size_value_unequal_to_1-_or_2-_or_4-Byte"
+ },
+ "1": {
+ "desc": "OPB_Master_LS_received_a_invalid_command_no_ci_store_and_no_ci_load"
+ },
+ "2": {
+ "desc": "OPB_Master_LS_received_a_address_which_was_not_aligned_to_the_received_transfer_size"
+ },
+ "3": {
+ "desc": "OPB_Master_LS_detected_OPB_ErrAck_which_was_activated_by_the_accessed_OPB_slave"
+ },
+ "4": {
+ "desc": "the_OPB_arbiter_activated_the_OPB_Timeout_signal_Typical_reason_is_that_the_OPB_access_did_not_hit_any_available_OPB_slave"
+ },
+ "5": {
+ "desc": "the_OPB_Master_LS_was_not_able_to_end_the_requested_OPB_access_within_the_OPB_Master_LS_hang_timeout_time"
+ },
+ "6": {
+ "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_command_buffer"
+ },
+ "7": {
+ "desc": "a parity_error_was_detected_in_the_OPB_Master_LS_data_buffer"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_dstl_fir.json b/chip_data/p10_20/node_mc_dstl_fir.json
new file mode 100644
index 0000000..d9a5827
--- /dev/null
+++ b/chip_data/p10_20/node_mc_dstl_fir.json
@@ -0,0 +1,415 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_DSTL_FIR": {
+ "instances": {
+ "0": "0x0C010D00",
+ "1": "0x0C010D40",
+ "2": "0x0D010D00",
+ "3": "0x0D010D40",
+ "4": "0x0E010D00",
+ "5": "0x0E010D40",
+ "6": "0x0F010D00",
+ "7": "0x0F010D40"
+ }
+ },
+ "MC_DSTL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010D03",
+ "1": "0x0C010D43",
+ "2": "0x0D010D03",
+ "3": "0x0D010D43",
+ "4": "0x0E010D03",
+ "5": "0x0E010D43",
+ "6": "0x0F010D03",
+ "7": "0x0F010D43"
+ }
+ },
+ "MC_DSTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010D06",
+ "1": "0x0C010D46",
+ "2": "0x0D010D06",
+ "3": "0x0D010D46",
+ "4": "0x0E010D06",
+ "5": "0x0E010D46",
+ "6": "0x0F010D06",
+ "7": "0x0F010D46"
+ }
+ },
+ "MC_DSTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010D07",
+ "1": "0x0C010D47",
+ "2": "0x0D010D07",
+ "3": "0x0D010D47",
+ "4": "0x0E010D07",
+ "5": "0x0E010D47",
+ "6": "0x0F010D07",
+ "7": "0x0F010D47"
+ }
+ },
+ "MC_DSTL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010D09",
+ "1": "0x0C010D49",
+ "2": "0x0D010D09",
+ "3": "0x0D010D49",
+ "4": "0x0E010D09",
+ "5": "0x0E010D49",
+ "6": "0x0F010D09",
+ "7": "0x0F010D49"
+ }
+ },
+ "MC_DSTL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010D08",
+ "1": "0x0C010D48",
+ "2": "0x0D010D08",
+ "3": "0x0D010D48",
+ "4": "0x0E010D08",
+ "5": "0x0E010D48",
+ "6": "0x0F010D08",
+ "7": "0x0F010D48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_DSTL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_DSTL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Subchannel A AFU initiated Checkstop"
+ },
+ "1": {
+ "desc": "Subchannel A AFU initiated Recoverable Attention"
+ },
+ "2": {
+ "desc": "Subchannel A AFU initiated Special Attention"
+ },
+ "3": {
+ "desc": "Subchannel A AFU initiated Application Interrupt Attention"
+ },
+ "4": {
+ "desc": "Subchannel B AFU initiated Checkstop"
+ },
+ "5": {
+ "desc": "Subchannel B AFU initiated Recoverable Attention"
+ },
+ "6": {
+ "desc": "Subchannel B AFU initiated Special Attention"
+ },
+ "7": {
+ "desc": "Subchannel B AFU initiated Application Interrupt Attention"
+ },
+ "8": {
+ "desc": "Error on parity bits protecting incoming command from MCS to DSTL"
+ },
+ "9": {
+ "desc": "A credit reset was attempted while rd and wdf buffers in use"
+ },
+ "10": {
+ "desc": "Config reg recoverable parity error"
+ },
+ "11": {
+ "desc": "Config reg fatal parity error"
+ },
+ "12": {
+ "desc": "Subchannel A counter error"
+ },
+ "13": {
+ "desc": "Subchannel B counter error"
+ },
+ "14": {
+ "desc": "Subchannel A valid cmd timeout error"
+ },
+ "15": {
+ "desc": "Subchannel B valid cmd timeout error"
+ },
+ "16": {
+ "desc": "Subchannel A buffer overuse error"
+ },
+ "17": {
+ "desc": "Subchannel B buffer overuse error"
+ },
+ "18": {
+ "desc": "Subchannel A DL link down"
+ },
+ "19": {
+ "desc": "Subchannel B DL link down"
+ },
+ "20": {
+ "desc": "Subchannel A has entered the fail state"
+ },
+ "21": {
+ "desc": "Subchannel B has entered the fail state"
+ },
+ "22": {
+ "desc": "Subchannel A Channel timeout"
+ },
+ "23": {
+ "desc": "Subchannel B Channel timeout"
+ },
+ "24": {
+ "desc": "decrypt err: scom reg has parity error"
+ },
+ "25": {
+ "desc": "decrypt err: attempt to write or access key when locked"
+ },
+ "26": {
+ "desc": "decrypt err: address pipe parity error"
+ },
+ "27": {
+ "desc": "decrypt err: CL to decrypt parity error on valid tag"
+ },
+ "28": {
+ "desc": "decrypt err: parity error on USTL decrypt DMX interface"
+ },
+ "29": {
+ "desc": "encrypt err: scom reg has parity error"
+ },
+ "30": {
+ "desc": "encrypt err: attempt to write or access key when locked"
+ },
+ "31": {
+ "desc": "encrypt err: parity error on address encryption rounds"
+ },
+ "32": {
+ "desc": "encrypt err: parity error on data encryption rounds"
+ },
+ "33": {
+ "desc": "Subchannel A AFU Application Interrupt Attention while another in process"
+ },
+ "34": {
+ "desc": "Subchannel B AFU Application Interrupt Attention while another in process"
+ },
+ "35": {
+ "desc": "A parity error local to Subchhanel A occurred"
+ },
+ "36": {
+ "desc": "A parity error local to Subchhanel B occurred"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "Subchannel A has significant traffic flow"
+ },
+ "40": {
+ "desc": "Subchannel B has significant traffic flow"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_DSTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_fir.json b/chip_data/p10_20/node_mc_fir.json
new file mode 100644
index 0000000..00c2de0
--- /dev/null
+++ b/chip_data/p10_20/node_mc_fir.json
@@ -0,0 +1,336 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_FIR": {
+ "instances": {
+ "0": "0x0C010C00",
+ "1": "0x0D010C00",
+ "2": "0x0E010C00",
+ "3": "0x0F010C00"
+ }
+ },
+ "MC_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010C03",
+ "1": "0x0D010C03",
+ "2": "0x0E010C03",
+ "3": "0x0F010C03"
+ }
+ },
+ "MC_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010C06",
+ "1": "0x0D010C06",
+ "2": "0x0E010C06",
+ "3": "0x0F010C06"
+ }
+ },
+ "MC_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010C07",
+ "1": "0x0D010C07",
+ "2": "0x0E010C07",
+ "3": "0x0F010C07"
+ }
+ },
+ "MC_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010C09",
+ "1": "0x0D010C09",
+ "2": "0x0E010C09",
+ "3": "0x0F010C09"
+ }
+ },
+ "MC_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010C08",
+ "1": "0x0D010C08",
+ "2": "0x0E010C08",
+ "3": "0x0F010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "MC internal recoverable error"
+ },
+ "1": {
+ "desc": "MC internal non-recoverable error"
+ },
+ "2": {
+ "desc": "MC powerbus protocol error"
+ },
+ "3": {
+ "desc": "MC inband bar with incorrect ttype"
+ },
+ "4": {
+ "desc": "MC multiple BAR hit"
+ },
+ "5": {
+ "desc": "Command list early hang trigger activated"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "reserved"
+ },
+ "8": {
+ "desc": "Command list state machine timeout"
+ },
+ "9": {
+ "desc": "reserved"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "WAT0 event occurred"
+ },
+ "12": {
+ "desc": "WAT1 event occurred"
+ },
+ "13": {
+ "desc": "WAT2 event occurred"
+ },
+ "14": {
+ "desc": "WAT3 event occurred"
+ },
+ "15": {
+ "desc": "Plus One Prefetch generated command did not hit any BARs"
+ },
+ "16": {
+ "desc": "Plus One Prefetch generated command hit config or mmio BAR"
+ },
+ "17": {
+ "desc": "Parity Error in WAT/Debug config register"
+ },
+ "18": {
+ "desc": "PBI received overcommit signal from READ0"
+ },
+ "19": {
+ "desc": "PBI received ocercommit signal from READ1"
+ },
+ "20": {
+ "desc": "Incoming Powerbus Command hit multiple valid configured topology IDs"
+ },
+ "21": {
+ "desc": "reserved"
+ },
+ "22": {
+ "desc": "Secure mem facility access privilege error by originating thread"
+ },
+ "23": {
+ "desc": "Multiple sync cmds received by an MC, or while one is pending"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_local_fir.json b/chip_data/p10_20/node_mc_local_fir.json
new file mode 100644
index 0000000..c3549d1
--- /dev/null
+++ b/chip_data/p10_20/node_mc_local_fir.json
@@ -0,0 +1,445 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_LOCAL_FIR": {
+ "instances": {
+ "0": "0x0C040100",
+ "1": "0x0D040100",
+ "2": "0x0E040100",
+ "3": "0x0F040100"
+ }
+ },
+ "MC_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C040103",
+ "1": "0x0D040103",
+ "2": "0x0E040103",
+ "3": "0x0F040103"
+ }
+ },
+ "MC_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C040106",
+ "1": "0x0D040106",
+ "2": "0x0E040106",
+ "3": "0x0F040106"
+ }
+ },
+ "MC_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C040107",
+ "1": "0x0D040107",
+ "2": "0x0E040107",
+ "3": "0x0F040107"
+ }
+ },
+ "MC_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C040109",
+ "1": "0x0D040109",
+ "2": "0x0E040109",
+ "3": "0x0F040109"
+ }
+ },
+ "MC_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C040108",
+ "1": "0x0D040108",
+ "2": "0x0E040108",
+ "3": "0x0F040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_misc_fir.json b/chip_data/p10_20/node_mc_misc_fir.json
new file mode 100644
index 0000000..d206e4b
--- /dev/null
+++ b/chip_data/p10_20/node_mc_misc_fir.json
@@ -0,0 +1,300 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_MISC_FIR": {
+ "instances": {
+ "0": "0x0C010F00",
+ "1": "0x0D010F00",
+ "2": "0x0E010F00",
+ "3": "0x0F010F00"
+ }
+ },
+ "MC_MISC_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010F03",
+ "1": "0x0D010F03",
+ "2": "0x0E010F03",
+ "3": "0x0F010F03"
+ }
+ },
+ "MC_MISC_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010F06",
+ "1": "0x0D010F06",
+ "2": "0x0E010F06",
+ "3": "0x0F010F06"
+ }
+ },
+ "MC_MISC_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010F07",
+ "1": "0x0D010F07",
+ "2": "0x0E010F07",
+ "3": "0x0F010F07"
+ }
+ },
+ "MC_MISC_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010F09",
+ "1": "0x0D010F09",
+ "2": "0x0E010F09",
+ "3": "0x0F010F09"
+ }
+ },
+ "MC_MISC_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010F08",
+ "1": "0x0D010F08",
+ "2": "0x0E010F08",
+ "3": "0x0F010F08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_MISC_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_MISC_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "WAT Debug Bus Attention"
+ },
+ "1": {
+ "desc": "SCOM DBGSRC Register parity Error"
+ },
+ "2": {
+ "desc": "SCOM Recoverable Register Parity Error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "Application interrupt received from OCMB on channel 0, subchannel A"
+ },
+ "5": {
+ "desc": "Application interrupt received from OCMB on channel 0, subchannel B"
+ },
+ "6": {
+ "desc": "Application interrupt received from OCMB on channel 1, subchannel A"
+ },
+ "7": {
+ "desc": "Application interrupt received from OCMB on channel 1, subchannel B"
+ },
+ "8": {
+ "desc": "Parity Error taken on MCEBUSEN[0,1,2,3] regs"
+ },
+ "9": {
+ "desc": "Parity Error taken on WAT* Regs"
+ },
+ "10": {
+ "desc": "Reserved"
+ },
+ "11": {
+ "desc": "Reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_MISC_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_omi_dl_fir.json b/chip_data/p10_20/node_mc_omi_dl_fir.json
new file mode 100644
index 0000000..ce73ea6
--- /dev/null
+++ b/chip_data/p10_20/node_mc_omi_dl_fir.json
@@ -0,0 +1,398 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_OMI_DL_FIR": {
+ "instances": {
+ "0": "0x0C011400",
+ "1": "0x0C011800",
+ "2": "0x0D011400",
+ "3": "0x0D011800",
+ "4": "0x0E011400",
+ "5": "0x0E011800",
+ "6": "0x0F011400",
+ "7": "0x0F011800"
+ }
+ },
+ "MC_OMI_DL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C011403",
+ "1": "0x0C011803",
+ "2": "0x0D011403",
+ "3": "0x0D011803",
+ "4": "0x0E011403",
+ "5": "0x0E011803",
+ "6": "0x0F011403",
+ "7": "0x0F011803"
+ }
+ },
+ "MC_OMI_DL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C011406",
+ "1": "0x0C011806",
+ "2": "0x0D011406",
+ "3": "0x0D011806",
+ "4": "0x0E011406",
+ "5": "0x0E011806",
+ "6": "0x0F011406",
+ "7": "0x0F011806"
+ }
+ },
+ "MC_OMI_DL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C011407",
+ "1": "0x0C011807",
+ "2": "0x0D011407",
+ "3": "0x0D011807",
+ "4": "0x0E011407",
+ "5": "0x0E011807",
+ "6": "0x0F011407",
+ "7": "0x0F011807"
+ }
+ },
+ "MC_OMI_DL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C011408",
+ "1": "0x0C011808",
+ "2": "0x0D011408",
+ "3": "0x0D011808",
+ "4": "0x0E011408",
+ "5": "0x0E011808",
+ "6": "0x0F011408",
+ "7": "0x0F011808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_OMI_DL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_OMI_DL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OMI-DL0 fatal error",
+ "child_node": {
+ "name": "MC_OMI_DL_ERR_RPT",
+ "inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ }
+ },
+ "1": {
+ "desc": "OMI-DL0 UE on data flit"
+ },
+ "2": {
+ "desc": "OMI-DL0 CE on TL flit"
+ },
+ "3": {
+ "desc": "OMI-DL0 detected a CRC error"
+ },
+ "4": {
+ "desc": "OMI-DL0 received a nack"
+ },
+ "5": {
+ "desc": "OMI-DL0 running in degraded mode"
+ },
+ "6": {
+ "desc": "OMI-DL0 parity error detection on a lane"
+ },
+ "7": {
+ "desc": "OMI-DL0 retrained due to no forward progress"
+ },
+ "8": {
+ "desc": "OMI-DL0 remote side initiated a retrain"
+ },
+ "9": {
+ "desc": "OMI-DL0 retrain due to internal error or software"
+ },
+ "10": {
+ "desc": "OMI-DL0 threshold reached"
+ },
+ "11": {
+ "desc": "OMI-DL0 trained"
+ },
+ "12": {
+ "desc": "OMI-DL0 endpoint error bit 0"
+ },
+ "13": {
+ "desc": "OMI-DL0 endpoint error bit 1"
+ },
+ "14": {
+ "desc": "OMI-DL0 endpoint error bit 2"
+ },
+ "15": {
+ "desc": "OMI-DL0 endpoint error bit 3"
+ },
+ "16": {
+ "desc": "OMI-DL0 endpoint error bit 4"
+ },
+ "17": {
+ "desc": "OMI-DL0 endpoint error bit 5"
+ },
+ "18": {
+ "desc": "OMI-DL0 endpoint error bit 6"
+ },
+ "19": {
+ "desc": "OMI-DL0 endpoint error bit 7"
+ },
+ "20": {
+ "desc": "OMI-DL1 fatal error",
+ "child_node": {
+ "name": "MC_OMI_DL_ERR_RPT",
+ "inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ }
+ },
+ "21": {
+ "desc": "OMI-DL1 UE on data flit"
+ },
+ "22": {
+ "desc": "OMI-DL1 CE on TL flit"
+ },
+ "23": {
+ "desc": "OMI-DL1 detected a CRC error"
+ },
+ "24": {
+ "desc": "OMI-DL1 received a nack"
+ },
+ "25": {
+ "desc": "OMI-DL1 running in degraded mode"
+ },
+ "26": {
+ "desc": "OMI-DL1 parity error detection on a lane"
+ },
+ "27": {
+ "desc": "OMI-DL1 retrained due to no forward progress"
+ },
+ "28": {
+ "desc": "OMI-DL1 remote side initiated a retrain"
+ },
+ "29": {
+ "desc": "OMI-DL1 retrain due to internal error or software"
+ },
+ "30": {
+ "desc": "OMI-DL1 threshold reached"
+ },
+ "31": {
+ "desc": "OMI-DL1 trained"
+ },
+ "32": {
+ "desc": "OMI-DL1 endpoint error bit 0"
+ },
+ "33": {
+ "desc": "OMI-DL1 endpoint error bit 1"
+ },
+ "34": {
+ "desc": "OMI-DL1 endpoint error bit 2"
+ },
+ "35": {
+ "desc": "OMI-DL1 endpoint error bit 3"
+ },
+ "36": {
+ "desc": "OMI-DL1 endpoint error bit 4"
+ },
+ "37": {
+ "desc": "OMI-DL1 endpoint error bit 5"
+ },
+ "38": {
+ "desc": "OMI-DL1 endpoint error bit 6"
+ },
+ "39": {
+ "desc": "OMI-DL1 endpoint error bit 7"
+ },
+ "40": {
+ "desc": "OMI-DL2 unused"
+ },
+ "41": {
+ "desc": "OMI-DL2 unused"
+ },
+ "42": {
+ "desc": "OMI-DL2 unused"
+ },
+ "43": {
+ "desc": "OMI-DL2 unused"
+ },
+ "44": {
+ "desc": "OMI-DL2 unused"
+ },
+ "45": {
+ "desc": "OMI-DL2 unused"
+ },
+ "46": {
+ "desc": "OMI-DL2 unused"
+ },
+ "47": {
+ "desc": "OMI-DL2 unused"
+ },
+ "48": {
+ "desc": "OMI-DL2 unused"
+ },
+ "49": {
+ "desc": "OMI-DL2 unused"
+ },
+ "50": {
+ "desc": "OMI-DL2 unused"
+ },
+ "51": {
+ "desc": "OMI-DL2 unused"
+ },
+ "52": {
+ "desc": "OMI-DL2 unused"
+ },
+ "53": {
+ "desc": "OMI-DL2 unused"
+ },
+ "54": {
+ "desc": "OMI-DL2 unused"
+ },
+ "55": {
+ "desc": "OMI-DL2 unused"
+ },
+ "56": {
+ "desc": "OMI-DL2 unused"
+ },
+ "57": {
+ "desc": "OMI-DL2 unused"
+ },
+ "58": {
+ "desc": "OMI-DL2 unused"
+ },
+ "59": {
+ "desc": "OMI-DL2 unused"
+ },
+ "60": {
+ "desc": "Performance monitor wrapped"
+ },
+ "61": {
+ "desc": "OMI-DL common FIR Register"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_OMI_DL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mc_ustl_fir.json b/chip_data/p10_20/node_mc_ustl_fir.json
new file mode 100644
index 0000000..7cc2510
--- /dev/null
+++ b/chip_data/p10_20/node_mc_ustl_fir.json
@@ -0,0 +1,478 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_USTL_FIR": {
+ "instances": {
+ "0": "0x0C010E00",
+ "1": "0x0C010E40",
+ "2": "0x0D010E00",
+ "3": "0x0D010E40",
+ "4": "0x0E010E00",
+ "5": "0x0E010E40",
+ "6": "0x0F010E00",
+ "7": "0x0F010E40"
+ }
+ },
+ "MC_USTL_FIR_MASK": {
+ "instances": {
+ "0": "0x0C010E03",
+ "1": "0x0C010E43",
+ "2": "0x0D010E03",
+ "3": "0x0D010E43",
+ "4": "0x0E010E03",
+ "5": "0x0E010E43",
+ "6": "0x0F010E03",
+ "7": "0x0F010E43"
+ }
+ },
+ "MC_USTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x0C010E06",
+ "1": "0x0C010E46",
+ "2": "0x0D010E06",
+ "3": "0x0D010E46",
+ "4": "0x0E010E06",
+ "5": "0x0E010E46",
+ "6": "0x0F010E06",
+ "7": "0x0F010E46"
+ }
+ },
+ "MC_USTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x0C010E07",
+ "1": "0x0C010E47",
+ "2": "0x0D010E07",
+ "3": "0x0D010E47",
+ "4": "0x0E010E07",
+ "5": "0x0E010E47",
+ "6": "0x0F010E07",
+ "7": "0x0F010E47"
+ }
+ },
+ "MC_USTL_FIR_ACT2": {
+ "instances": {
+ "0": "0x0C010E09",
+ "1": "0x0C010E49",
+ "2": "0x0D010E09",
+ "3": "0x0D010E49",
+ "4": "0x0E010E09",
+ "5": "0x0E010E49",
+ "6": "0x0F010E09",
+ "7": "0x0F010E49"
+ }
+ },
+ "MC_USTL_FIR_WOF": {
+ "instances": {
+ "0": "0x0C010E08",
+ "1": "0x0C010E48",
+ "2": "0x0D010E08",
+ "3": "0x0D010E48",
+ "4": "0x0E010E08",
+ "5": "0x0E010E48",
+ "6": "0x0F010E08",
+ "7": "0x0F010E48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MC_USTL_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MC_USTL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Unexpected Flit Data showed up for Chana"
+ },
+ "1": {
+ "desc": "Unexpected Flit Data showed up for Chanb"
+ },
+ "2": {
+ "desc": "A unsupported template for a command flit for chana"
+ },
+ "3": {
+ "desc": "A unsupported template for a command flit for chanb"
+ },
+ "4": {
+ "desc": "Reserved"
+ },
+ "5": {
+ "desc": "Reserved"
+ },
+ "6": {
+ "desc": "WDF CE detected on buffer output"
+ },
+ "7": {
+ "desc": "WDF UE detected on buffer output"
+ },
+ "8": {
+ "desc": "WDF SUE detected on buffer output"
+ },
+ "9": {
+ "desc": "WDF buffer overrun detected"
+ },
+ "10": {
+ "desc": "WDF detected parity on USTL tag interface"
+ },
+ "11": {
+ "desc": "WDF detected a scom sequencer error"
+ },
+ "12": {
+ "desc": "WDF detected a pwctl sequencer error"
+ },
+ "13": {
+ "desc": "WDF detected a parity error on the misc_reg scom register"
+ },
+ "14": {
+ "desc": "Parity Error detected in WDF for CL pop"
+ },
+ "15": {
+ "desc": "WDF detected a non-zero syndrome (CE ore UE) from USTL"
+ },
+ "16": {
+ "desc": "WDF CMD parity errror"
+ },
+ "17": {
+ "desc": "Unused"
+ },
+ "18": {
+ "desc": "Unused"
+ },
+ "19": {
+ "desc": "Read Buffers overflowed/underflowed (more than 64 in use)"
+ },
+ "20": {
+ "desc": "WRT CE detected on buffer output"
+ },
+ "21": {
+ "desc": "WRT UE detected on buffer output"
+ },
+ "22": {
+ "desc": "WRT SUE detected on buffer output"
+ },
+ "23": {
+ "desc": "WRT detected a scom sequencer error"
+ },
+ "24": {
+ "desc": "WRT detected a parity error on the misc_reg scom register"
+ },
+ "25": {
+ "desc": "WRT Data Syndrome not equal to 0 for input for write buffer"
+ },
+ "26": {
+ "desc": "No buffer error; Buffer manager parity error"
+ },
+ "27": {
+ "desc": "A fail response set as checkstop occurred for chana"
+ },
+ "28": {
+ "desc": "A fail response set as checkstop occurred for chanb"
+ },
+ "29": {
+ "desc": "A fail response set as recoverable occurred for chana"
+ },
+ "30": {
+ "desc": "A fail response set as recoverable occurred for chanb"
+ },
+ "31": {
+ "desc": "A lol drop set as checkstop occurred for chana"
+ },
+ "32": {
+ "desc": "A lol drop set as checkstop occurred for chanb"
+ },
+ "33": {
+ "desc": "A lol drop set as recoverable occurred for chana"
+ },
+ "34": {
+ "desc": "A lol drop set as recoverable occurred for chanb"
+ },
+ "35": {
+ "desc": "flit data pariry error from dl for chana"
+ },
+ "36": {
+ "desc": "flit data pariry error from dl for chanb"
+ },
+ "37": {
+ "desc": "internal fifo parity error for chana"
+ },
+ "38": {
+ "desc": "internal fifo parity error for chanb"
+ },
+ "39": {
+ "desc": "Unexpected read or write response received, chana"
+ },
+ "40": {
+ "desc": "Unexpected read or write response received, chanb"
+ },
+ "41": {
+ "desc": "Bad data set for data that is not valid chana"
+ },
+ "42": {
+ "desc": "Bad data set for data that is not valid chanb"
+ },
+ "43": {
+ "desc": "Memory read data returned in template 0, chana"
+ },
+ "44": {
+ "desc": "Memory read data returned in template 0, chanb"
+ },
+ "45": {
+ "desc": "Recieved mmio response while in LOL mode chana"
+ },
+ "46": {
+ "desc": "Recieved mmio response while in LOL mode chanb"
+ },
+ "47": {
+ "desc": "valid bad data or SUE received channel a"
+ },
+ "48": {
+ "desc": "Valid bad data or SUE received chanb"
+ },
+ "49": {
+ "desc": "ChanA excessive data error"
+ },
+ "50": {
+ "desc": "ChanB excessive data error"
+ },
+ "51": {
+ "desc": "Commit state where commit data is not marked as valid"
+ },
+ "52": {
+ "desc": "Commit state where commit data is not marked as valid"
+ },
+ "53": {
+ "desc": "A fifo in the ustl chana overflowed"
+ },
+ "54": {
+ "desc": "A fifo in the ustl chanb overflowed"
+ },
+ "55": {
+ "desc": "Invalid command decoded in USTL FF subchannel A"
+ },
+ "56": {
+ "desc": "Invalid command decoded in USTL FF subchannel B"
+ },
+ "57": {
+ "desc": "Fatal register parity error"
+ },
+ "58": {
+ "desc": "recov register parity error"
+ },
+ "59": {
+ "desc": "ChanA response invalid(dlength and/or dpart received)"
+ },
+ "60": {
+ "desc": "ChanB response invalid(dlength and/or dpart received)"
+ },
+ "61": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MC_USTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_mcd_fir.json b/chip_data/p10_20/node_mcd_fir.json
new file mode 100644
index 0000000..9ac6048
--- /dev/null
+++ b/chip_data/p10_20/node_mcd_fir.json
@@ -0,0 +1,169 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MCD_FIR": {
+ "instances": {
+ "0": "0x03010800"
+ }
+ },
+ "MCD_FIR_MASK": {
+ "instances": {
+ "0": "0x03010803"
+ }
+ },
+ "MCD_FIR_ACT0": {
+ "instances": {
+ "0": "0x03010806"
+ }
+ },
+ "MCD_FIR_ACT1": {
+ "instances": {
+ "0": "0x03010807"
+ }
+ },
+ "MCD_FIR_WOF": {
+ "instances": {
+ "0": "0x03010808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MCD_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCD_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "MCD array ECC correctable error"
+ },
+ "1": {
+ "desc": "MCD array ECC uncorrectable error"
+ },
+ "2": {
+ "desc": "MCD PowerBus address parity error"
+ },
+ "3": {
+ "desc": "MCD invalid state error"
+ },
+ "4": {
+ "desc": "Hang poll timer expired on cl_probe"
+ },
+ "5": {
+ "desc": "PowerBus address error cresp received"
+ },
+ "6": {
+ "desc": "MCD received a unsolicited CRESP"
+ },
+ "7": {
+ "desc": "MCD powerbus ttag parity error"
+ },
+ "8": {
+ "desc": "MCD scom register update error"
+ },
+ "9": {
+ "desc": "MCD received a ack_dead_cresp"
+ },
+ "10": {
+ "desc": "MCD configuration register had a parity error"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_n0_local_fir.json b/chip_data/p10_20/node_n0_local_fir.json
new file mode 100644
index 0000000..5d45ada
--- /dev/null
+++ b/chip_data/p10_20/node_n0_local_fir.json
@@ -0,0 +1,427 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "N0_LOCAL_FIR": {
+ "instances": {
+ "0": "0x02040100"
+ }
+ },
+ "N0_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x02040103"
+ }
+ },
+ "N0_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x02040106"
+ }
+ },
+ "N0_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x02040107"
+ }
+ },
+ "N0_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x02040109"
+ }
+ },
+ "N0_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x02040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "N0_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N0_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_n1_local_fir.json b/chip_data/p10_20/node_n1_local_fir.json
new file mode 100644
index 0000000..ce7f45a
--- /dev/null
+++ b/chip_data/p10_20/node_n1_local_fir.json
@@ -0,0 +1,427 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "N1_LOCAL_FIR": {
+ "instances": {
+ "0": "0x03040100"
+ }
+ },
+ "N1_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x03040103"
+ }
+ },
+ "N1_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x03040106"
+ }
+ },
+ "N1_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x03040107"
+ }
+ },
+ "N1_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x03040109"
+ }
+ },
+ "N1_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x03040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "N1_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "N1_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "Firmware signaled power bus quiesce failed"
+ },
+ "57": {
+ "desc": "Firmware signaled power bus system quiesce failed"
+ },
+ "58": {
+ "desc": "Firmware signaled deadman timer tigger occurred"
+ },
+ "59": {
+ "desc": "Fimware signaled power bus chip quiesce failed"
+ },
+ "60": {
+ "desc": "Hypervisor / Hostboot / OPAL initiated Terminate Immediate"
+ },
+ "61": {
+ "desc": "Host detected LPC timeout"
+ },
+ "62": {
+ "desc": "reserved for software use"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_nmmu_cq_fir.json b/chip_data/p10_20/node_nmmu_cq_fir.json
new file mode 100644
index 0000000..b036004
--- /dev/null
+++ b/chip_data/p10_20/node_nmmu_cq_fir.json
@@ -0,0 +1,207 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "NMMU_CQ_FIR": {
+ "instances": {
+ "0": "0x02010C00",
+ "1": "0x03010C00"
+ }
+ },
+ "NMMU_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02010C03",
+ "1": "0x03010C03"
+ }
+ },
+ "NMMU_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010C06",
+ "1": "0x03010C06"
+ }
+ },
+ "NMMU_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010C07",
+ "1": "0x03010C07"
+ }
+ },
+ "NMMU_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02010C08",
+ "1": "0x03010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NMMU_CQ_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PBI internal parity error"
+ },
+ "1": {
+ "desc": "PowerBus command hang error"
+ },
+ "2": {
+ "desc": "PowerBus read address error"
+ },
+ "3": {
+ "desc": "PowerBus write address error"
+ },
+ "4": {
+ "desc": "PowerBus miscellaneous error"
+ },
+ "5": {
+ "desc": "Reserved"
+ },
+ "6": {
+ "desc": "PowerBus Xlate UE error"
+ },
+ "7": {
+ "desc": "PowerBus Xlate SUE error"
+ },
+ "8": {
+ "desc": "PowerBus CE error"
+ },
+ "9": {
+ "desc": "PowerBus UE error"
+ },
+ "10": {
+ "desc": "PowerBus SUE error"
+ },
+ "11": {
+ "desc": "Inbound LCO_ARRAY CE error"
+ },
+ "12": {
+ "desc": "Inbound LCO_ARRAY UE error"
+ },
+ "13": {
+ "desc": "Inbound LCO_ARRAY SUE error"
+ },
+ "14": {
+ "desc": "Inbound array CE error"
+ },
+ "15": {
+ "desc": "Inbound array UE error"
+ },
+ "16": {
+ "desc": "internal state error"
+ },
+ "17": {
+ "desc": "ACK_DEAD cresp received by read command"
+ },
+ "18": {
+ "desc": "ACK_DEAD cresp received by write command"
+ },
+ "19": {
+ "desc": "Link check aborted while waiting on data"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NMMU_CQ_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_nmmu_fir.json b/chip_data/p10_20/node_nmmu_fir.json
new file mode 100644
index 0000000..5e542dc
--- /dev/null
+++ b/chip_data/p10_20/node_nmmu_fir.json
@@ -0,0 +1,276 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "NMMU_FIR": {
+ "instances": {
+ "0": "0x02010C40",
+ "1": "0x03010C40"
+ }
+ },
+ "NMMU_FIR_MASK": {
+ "instances": {
+ "0": "0x02010C43",
+ "1": "0x03010C43"
+ }
+ },
+ "NMMU_FIR_ACT0": {
+ "instances": {
+ "0": "0x02010C46",
+ "1": "0x03010C46"
+ }
+ },
+ "NMMU_FIR_ACT1": {
+ "instances": {
+ "0": "0x02010C47",
+ "1": "0x03010C47"
+ }
+ },
+ "NMMU_FIR_WOF": {
+ "instances": {
+ "0": "0x02010C48",
+ "1": "0x03010C48"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NMMU_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NMMU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Fabric DIn xlat array CE error detected"
+ },
+ "1": {
+ "desc": "Fabric DIn xlat array UE error detected"
+ },
+ "2": {
+ "desc": "Fabric DIn xlat array SUE error detected"
+ },
+ "3": {
+ "desc": "Fabric mst rd array CE error detected"
+ },
+ "4": {
+ "desc": "Fabric mst rd array UE error detected"
+ },
+ "5": {
+ "desc": "Fabric mst rd array SUE error detected"
+ },
+ "6": {
+ "desc": "Fabric xlat protocol error detected"
+ },
+ "7": {
+ "desc": "Fabric xlat op timeout detected"
+ },
+ "8": {
+ "desc": "SLB directory parity error detected"
+ },
+ "9": {
+ "desc": "SLB cache parity error detected"
+ },
+ "10": {
+ "desc": "SLB lru parity error detected"
+ },
+ "11": {
+ "desc": "SLB multi-hit error detected"
+ },
+ "12": {
+ "desc": "TLB directory parity error detected"
+ },
+ "13": {
+ "desc": "TLB cache parity error detected"
+ },
+ "14": {
+ "desc": "TLB lru parity error detected"
+ },
+ "15": {
+ "desc": "TLB multi-hit error detected"
+ },
+ "16": {
+ "desc": "Segment fault detected"
+ },
+ "17": {
+ "desc": "Page fault detected due to no matching pte"
+ },
+ "18": {
+ "desc": "Page fault detected due to basic prot chk fail"
+ },
+ "19": {
+ "desc": "Page fault detected due to virt prot chk fail"
+ },
+ "20": {
+ "desc": "Page fault detected due to seid mismatch"
+ },
+ "21": {
+ "desc": "Address error cresp detected by twsm for read"
+ },
+ "22": {
+ "desc": "PTE update fail due to armwf mismatch"
+ },
+ "23": {
+ "desc": "Address error cresp detected by twsm for write"
+ },
+ "24": {
+ "desc": "Unsupported radix cfg for guest-side"
+ },
+ "25": {
+ "desc": "Unsupported radix cfg for host-side"
+ },
+ "26": {
+ "desc": "Invalid wimg setting detected"
+ },
+ "27": {
+ "desc": "Invalid radix quad access detected"
+ },
+ "28": {
+ "desc": "Unexpected access to foreign address space"
+ },
+ "29": {
+ "desc": "Prefetch abort/fail detected"
+ },
+ "30": {
+ "desc": "Context cache array parity error detected"
+ },
+ "31": {
+ "desc": "Radix pwc array parity error detected"
+ },
+ "32": {
+ "desc": "Tablewalk sm control error detected"
+ },
+ "33": {
+ "desc": "Castout sm control error detected"
+ },
+ "34": {
+ "desc": "Check-in sm control error detected"
+ },
+ "35": {
+ "desc": "Invalidate sm control error detected"
+ },
+ "36": {
+ "desc": "Tablewalk sm timeout error detected"
+ },
+ "37": {
+ "desc": "Castout sm timeout error detected"
+ },
+ "38": {
+ "desc": "Check-in sm timeout error detected"
+ },
+ "39": {
+ "desc": "Invalidate sm timeout error detected"
+ },
+ "40": {
+ "desc": "NX local checkstop error detected"
+ },
+ "41": {
+ "desc": "fbc snoop invalidate filter parity error"
+ },
+ "42": {
+ "desc": "fabric purge threshold exceeded"
+ },
+ "43": {
+ "desc": "NPU local checkstop error detected"
+ },
+ "44": {
+ "desc": "FBC local checkstop error detected"
+ },
+ "45": {
+ "desc": "FBC local checkstop error detected"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_nx_cq_fir.json b/chip_data/p10_20/node_nx_cq_fir.json
new file mode 100644
index 0000000..d53da37
--- /dev/null
+++ b/chip_data/p10_20/node_nx_cq_fir.json
@@ -0,0 +1,267 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "NX_CQ_FIR": {
+ "instances": {
+ "0": "0x02011080"
+ }
+ },
+ "NX_CQ_FIR_MASK": {
+ "instances": {
+ "0": "0x02011083"
+ }
+ },
+ "NX_CQ_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011086"
+ }
+ },
+ "NX_CQ_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011087"
+ }
+ },
+ "NX_CQ_FIR_WOF": {
+ "instances": {
+ "0": "0x02011088"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NX_CQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_CQ_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PBI internal parity error"
+ },
+ "1": {
+ "desc": "PowerBus CE error"
+ },
+ "2": {
+ "desc": "PowerBus UE error"
+ },
+ "3": {
+ "desc": "PowerBus SUE error"
+ },
+ "4": {
+ "desc": "Inbound array CE error"
+ },
+ "5": {
+ "desc": "Inbound array UE error"
+ },
+ "6": {
+ "desc": "Paste request rejected"
+ },
+ "7": {
+ "desc": "PowerBus command hang error"
+ },
+ "8": {
+ "desc": "PowerBus read address error"
+ },
+ "9": {
+ "desc": "PowerBus write address error"
+ },
+ "10": {
+ "desc": "PowerBus miscellaneous error"
+ },
+ "11": {
+ "desc": "MMIO BAR parity error"
+ },
+ "12": {
+ "desc": "UMAC detected SUE on WC Interrupt"
+ },
+ "13": {
+ "desc": "ACK_DEAD cresp received by read command"
+ },
+ "14": {
+ "desc": "ACK_DEAD cresp received by write command"
+ },
+ "15": {
+ "desc": "Reserved. Used to be PowerBus Link Abort in P9"
+ },
+ "16": {
+ "desc": "Hang poll time expired on internal transfer"
+ },
+ "17": {
+ "desc": "Parity error on ERAT arrays"
+ },
+ "18": {
+ "desc": "Correctable error on ERAT arrays"
+ },
+ "19": {
+ "desc": "Uncorrectable error on ERAT arrays"
+ },
+ "20": {
+ "desc": "Special uncorrectable error on ERAT arrays"
+ },
+ "21": {
+ "desc": "Hang on checkin/checkout request to NMMU"
+ },
+ "22": {
+ "desc": "ERAT control logic error"
+ },
+ "23": {
+ "desc": "Uncorrectable error on the Powerbus data for xlate"
+ },
+ "24": {
+ "desc": "Special uncorrectable error on the Powerbus data for xlate"
+ },
+ "25": {
+ "desc": "ACK_DEAD cresp received by UMAC read command"
+ },
+ "26": {
+ "desc": "Link check aborted while waiting on UMAC data"
+ },
+ "27": {
+ "desc": "Uncorrectable error on CRB QW0/4"
+ },
+ "28": {
+ "desc": "Special uncorrectable error on CRB QW0/4"
+ },
+ "29": {
+ "desc": "UMAC has detected a control logic error"
+ },
+ "30": {
+ "desc": "Other SCOM satellite parity error"
+ },
+ "31": {
+ "desc": "SCOM write to RNG when not allowed"
+ },
+ "32": {
+ "desc": "A first noise source in the RNG has failed"
+ },
+ "33": {
+ "desc": "A second noise source in the RNG has failed"
+ },
+ "34": {
+ "desc": "RNG has detected a control logic error"
+ },
+ "35": {
+ "desc": "NMMU has signaled local checkstop"
+ },
+ "36": {
+ "desc": "VAS has signaled local checkstop"
+ },
+ "37": {
+ "desc": "PBCQ has detected a control logic error"
+ },
+ "38": {
+ "desc": "PBCQ has detected a failed link on an interrupt"
+ },
+ "39": {
+ "desc": "UMAC has detected an SUE on interrupt address"
+ },
+ "40": {
+ "desc": "SMF error"
+ },
+ "41": {
+ "desc": "Topology index error detected in NX"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NX_CQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_nx_dma_eng_fir.json b/chip_data/p10_20/node_nx_dma_eng_fir.json
new file mode 100644
index 0000000..01f38b2
--- /dev/null
+++ b/chip_data/p10_20/node_nx_dma_eng_fir.json
@@ -0,0 +1,285 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "NX_DMA_ENG_FIR": {
+ "instances": {
+ "0": "0x02011100"
+ }
+ },
+ "NX_DMA_ENG_FIR_MASK": {
+ "instances": {
+ "0": "0x02011103"
+ }
+ },
+ "NX_DMA_ENG_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011106"
+ }
+ },
+ "NX_DMA_ENG_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011107"
+ }
+ },
+ "NX_DMA_ENG_FIR_WOF": {
+ "instances": {
+ "0": "0x02011108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "NX_DMA_ENG_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "NX_DMA_ENG_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "DMA hang timer expired"
+ },
+ "1": {
+ "desc": "SHM invalid state"
+ },
+ "2": {
+ "desc": "reserved"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "Channel 0 842 engine ECC CE"
+ },
+ "5": {
+ "desc": "Channel 0 842 engine ECC UE"
+ },
+ "6": {
+ "desc": "Channel 1 842 engine ECC CE"
+ },
+ "7": {
+ "desc": "Channel 1 842 engine ECC UE"
+ },
+ "8": {
+ "desc": "DMA Non-zero CSB CC detected"
+ },
+ "9": {
+ "desc": "DMA array ECC CE"
+ },
+ "10": {
+ "desc": "DMA outbound write/inbound read ECC CE"
+ },
+ "11": {
+ "desc": "Channel 4 GZIP ECC CE"
+ },
+ "12": {
+ "desc": "Channel 4 GZIP ECC UE"
+ },
+ "13": {
+ "desc": "Channel 4 GZIP ECC PE"
+ },
+ "14": {
+ "desc": "Error from other SCOM satellites"
+ },
+ "15": {
+ "desc": "DMA invalid state error (unrecoverable)"
+ },
+ "16": {
+ "desc": "DMA invalid state error (unrecoverable)"
+ },
+ "17": {
+ "desc": "DMA array ECC UE"
+ },
+ "18": {
+ "desc": "DMA outbound write/inbound read ECC UE"
+ },
+ "19": {
+ "desc": "DMA inbound read error"
+ },
+ "20": {
+ "desc": "Channel 0 842 invalid state error"
+ },
+ "21": {
+ "desc": "Channel 1 842 invalid state error"
+ },
+ "22": {
+ "desc": "Channel 2 SYM invalid state error"
+ },
+ "23": {
+ "desc": "Channel 3 SYM invalid state error"
+ },
+ "24": {
+ "desc": "Channel 4 GZIP invalid state error"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "reserved"
+ },
+ "27": {
+ "desc": "reserved"
+ },
+ "28": {
+ "desc": "reserved"
+ },
+ "29": {
+ "desc": "reserved"
+ },
+ "30": {
+ "desc": "reserved"
+ },
+ "31": {
+ "desc": "UE error on CRB QW0 or QW4"
+ },
+ "32": {
+ "desc": "SUE error on CRB QW0 or QW4"
+ },
+ "33": {
+ "desc": "SUE error on something other than CRB QW0 or QW4"
+ },
+ "34": {
+ "desc": "Channel 0 842 watchdog timer expired"
+ },
+ "35": {
+ "desc": "Channel 1 842 watchdog timer expired"
+ },
+ "36": {
+ "desc": "Channel 2 SYM watchdog timer expired"
+ },
+ "37": {
+ "desc": "Channel 3 SYM watchdog timer expired"
+ },
+ "38": {
+ "desc": "Hypervisor local checkstop"
+ },
+ "39": {
+ "desc": "Channel 4 Gzip watchdog timer expired"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "reserved"
+ },
+ "43": {
+ "desc": "reserved"
+ },
+ "44": {
+ "desc": "reserved"
+ },
+ "45": {
+ "desc": "reserved"
+ },
+ "46": {
+ "desc": "reserved"
+ },
+ "47": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "NX_DMA_ENG_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_occ_fir.json b/chip_data/p10_20/node_occ_fir.json
new file mode 100644
index 0000000..4f81969
--- /dev/null
+++ b/chip_data/p10_20/node_occ_fir.json
@@ -0,0 +1,294 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "OCC_FIR": {
+ "instances": {
+ "0": "0x01010800"
+ }
+ },
+ "OCC_FIR_MASK": {
+ "instances": {
+ "0": "0x01010803"
+ }
+ },
+ "OCC_FIR_ACT0": {
+ "instances": {
+ "0": "0x01010806"
+ }
+ },
+ "OCC_FIR_ACT1": {
+ "instances": {
+ "0": "0x01010807"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OCC_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCC_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OCC_FW0"
+ },
+ "1": {
+ "desc": "OCC_FW1"
+ },
+ "2": {
+ "desc": "OCC_QME_ERROR_NOTIFY"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "OCC Heartbeat Error"
+ },
+ "5": {
+ "desc": "GPE0 asserted a watchdog timeout condition"
+ },
+ "6": {
+ "desc": "GPE1 asserted a watchdog timeout condition"
+ },
+ "7": {
+ "desc": "GPE2 asserted a watchdog timeout condition"
+ },
+ "8": {
+ "desc": "GPE3 asserted a watchdog timeout condition"
+ },
+ "9": {
+ "desc": "GPE0 asserted an error condition that caused it to halt."
+ },
+ "10": {
+ "desc": "GPE1 asserted an error condition that caused it to halt."
+ },
+ "11": {
+ "desc": "GPE2 asserted an error condition that caused it to halt."
+ },
+ "12": {
+ "desc": "GPE3 asserted an error condition that caused it to halt."
+ },
+ "13": {
+ "desc": "OCB Error to PM Hcode for PM Complex Restart"
+ },
+ "14": {
+ "desc": "SRAM UE to PM Hcode for PM Complex Restart"
+ },
+ "15": {
+ "desc": "SRAM CE"
+ },
+ "16": {
+ "desc": "GPE0 asserted a halt condition"
+ },
+ "17": {
+ "desc": "GPE1 asserted a halt condition"
+ },
+ "18": {
+ "desc": "GPE2 asserted a halt condition"
+ },
+ "19": {
+ "desc": "GPE3 asserted a halt condition"
+ },
+ "20": {
+ "desc": "GPE0 attempted to write outside the region defined in GPESWPR"
+ },
+ "21": {
+ "desc": "GPE1 attempted to write outside the region defined in GPESWPR"
+ },
+ "22": {
+ "desc": "GPE2 attempted to write outside the region defined in GPESWPR"
+ },
+ "23": {
+ "desc": "GPE3 attempted to write outside the region defined in GPESWPR"
+ },
+ "24": {
+ "desc": "Safe Mode for debug use"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "EXTERNAL_TRAP"
+ },
+ "27": {
+ "desc": "PPC405 Core Reset Output asserted (OCC firmware)"
+ },
+ "28": {
+ "desc": "PPC405 Chip Reset Output asserted (OCC firmware)"
+ },
+ "29": {
+ "desc": "PPC405 System Reset Output asserted (OCC firmware)"
+ },
+ "30": {
+ "desc": "PPC405 Wait State asserted (OCC firmware)"
+ },
+ "31": {
+ "desc": "PPC405 Stop Ack output asserted"
+ },
+ "32": {
+ "desc": "OCB Direct Bridge Error"
+ },
+ "33": {
+ "desc": "OCB PIB Address Parity Error"
+ },
+ "34": {
+ "desc": "Indirect Channel Error"
+ },
+ "35": {
+ "desc": "Parity error detected on OPIT interrupt bus"
+ },
+ "36": {
+ "desc": "OPIT interrupt state machine error occurred"
+ },
+ "37": {
+ "desc": "reserved"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "JTAG accelerator error"
+ },
+ "43": {
+ "desc": "Any OCI Slave error occurreds"
+ },
+ "44": {
+ "desc": "PPC405 cache UE"
+ },
+ "45": {
+ "desc": "PPC405 cache CE"
+ },
+ "46": {
+ "desc": "PPC405 Machine Check"
+ },
+ "47": {
+ "desc": "SRAM spare direct error Summary"
+ },
+ "48": {
+ "desc": "Read, write, or parity error in the SRAM tank controller"
+ },
+ "49": {
+ "desc": "reserved"
+ },
+ "50": {
+ "desc": "reserved"
+ },
+ "51": {
+ "desc": "OCI slave error for GPE0"
+ },
+ "52": {
+ "desc": "OCI slave error for GPE1"
+ },
+ "53": {
+ "desc": "OCI slave error for GPE2"
+ },
+ "54": {
+ "desc": "OCI slave error for GPE3"
+ },
+ "55": {
+ "desc": "PPC405 ICU timeout on OCI request"
+ },
+ "56": {
+ "desc": "PPC405 DCU timeout on OCI request"
+ },
+ "57": {
+ "desc": "OCC fault occurred (to achieve safe mode)"
+ },
+ "58": {
+ "desc": "Read by HYP as part of the communication of a Power Management fault"
+ },
+ "59": {
+ "desc": "reserved"
+ },
+ "60": {
+ "desc": "reserved"
+ },
+ "61": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "OCC_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_fir_0.json b/chip_data/p10_20/node_pau_fir_0.json
new file mode 100644
index 0000000..e3ca798
--- /dev/null
+++ b/chip_data/p10_20/node_pau_fir_0.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_FIR_0": {
+ "instances": {
+ "0": "0x10010C00",
+ "3": "0x11010C00",
+ "4": "0x12010C00",
+ "5": "0x12011400",
+ "6": "0x13010C00",
+ "7": "0x13011400"
+ }
+ },
+ "PAU_FIR_0_MASK": {
+ "instances": {
+ "0": "0x10010C03",
+ "3": "0x11010C03",
+ "4": "0x12010C03",
+ "5": "0x12011403",
+ "6": "0x13010C03",
+ "7": "0x13011403"
+ }
+ },
+ "PAU_FIR_0_ACT0": {
+ "instances": {
+ "0": "0x10010C06",
+ "3": "0x11010C06",
+ "4": "0x12010C06",
+ "5": "0x12011406",
+ "6": "0x13010C06",
+ "7": "0x13011406"
+ }
+ },
+ "PAU_FIR_0_ACT1": {
+ "instances": {
+ "0": "0x10010C07",
+ "3": "0x11010C07",
+ "4": "0x12010C07",
+ "5": "0x12011407",
+ "6": "0x13010C07",
+ "7": "0x13011407"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_0": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_0_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NTL array CE"
+ },
+ "1": {
+ "desc": "NTL header array UE"
+ },
+ "2": {
+ "desc": "NTL data array UE"
+ },
+ "3": {
+ "desc": "NTL NVLInk Control/Header/AE Parity error"
+ },
+ "4": {
+ "desc": "NTL NVLink Data Parity error"
+ },
+ "5": {
+ "desc": "NTL NVLink Malformed Packet"
+ },
+ "6": {
+ "desc": "NTL NVLink Unsupported Packet"
+ },
+ "7": {
+ "desc": "NTL NVLink Config errors"
+ },
+ "8": {
+ "desc": "NTL NVLink CRC errors or LMD=Stomp"
+ },
+ "9": {
+ "desc": "NTL PRI errors"
+ },
+ "10": {
+ "desc": "NTL logic error"
+ },
+ "11": {
+ "desc": "NTL LMD=Data Poison"
+ },
+ "12": {
+ "desc": "NTL data array SUE"
+ },
+ "13": {
+ "desc": "CQ CTL/SM ASBE Array single-bit correctable error"
+ },
+ "14": {
+ "desc": "CQ CTL/SM PBR PowerBus Recoverable"
+ },
+ "15": {
+ "desc": "CQ CTL/SM REG Register ring error"
+ },
+ "16": {
+ "desc": "CQ CTL/SM DUE Data Uncorrectable error for MMIO store data"
+ },
+ "17": {
+ "desc": "CQ CTL/SM UT=1 to frozen PE"
+ },
+ "18": {
+ "desc": "CQ CTL/SM NCF NVLink configuration error"
+ },
+ "19": {
+ "desc": "CQ CTL/SM NVF NVLink fatal"
+ },
+ "20": {
+ "desc": "CQ CTL/SM OCR OpenCAPI Recoverable, Command failed, and brick not fenced."
+ },
+ "21": {
+ "desc": "CQ CTL/SM AUE Array uncorrectable error"
+ },
+ "22": {
+ "desc": "CQ CTL/SM PBP PowerBus parity error"
+ },
+ "23": {
+ "desc": "CQ CTL/SM PBF PowerBus Fatal"
+ },
+ "24": {
+ "desc": "CQ CTL/SM PBC PowerBus configuration error"
+ },
+ "25": {
+ "desc": "CQ CTL/SM FWD Forward-Progress"
+ },
+ "26": {
+ "desc": "CQ CTL/SM NLG PAU Logic error"
+ },
+ "27": {
+ "desc": "Cresp=Addr_Error received for a load command"
+ },
+ "28": {
+ "desc": "Cresp=Addr_Error received for a store command"
+ },
+ "29": {
+ "desc": "CQ DAT ECC UE on data/BE arrays"
+ },
+ "30": {
+ "desc": "CQ DAT ECC CE on data/BE arrays"
+ },
+ "31": {
+ "desc": "CQ DAT parity error on data/BE latches"
+ },
+ "32": {
+ "desc": "CQ DAT parity errors on configuration registers"
+ },
+ "33": {
+ "desc": "CQ DAT parity errors on received PowerBus rtag"
+ },
+ "34": {
+ "desc": "CQ DAT parity errors on internal state latches"
+ },
+ "35": {
+ "desc": "CQ DAT logic error"
+ },
+ "36": {
+ "desc": "CQ DAT ECC SUE on data/BE arrays"
+ },
+ "37": {
+ "desc": "CQ DAT ECC SUE on PB receive data"
+ },
+ "38": {
+ "desc": "CQ DAT Reserved, macro bit 9"
+ },
+ "39": {
+ "desc": "CQ DAT Reserved, macro bit 10"
+ },
+ "40": {
+ "desc": "XTS internal logic error"
+ },
+ "41": {
+ "desc": "XTS correctable errors in XTS internal SRAM"
+ },
+ "42": {
+ "desc": "XTS uncorrectable errors in XTS internal SRAM"
+ },
+ "43": {
+ "desc": "XTS correctable error on incoming stack transactions"
+ },
+ "44": {
+ "desc": "XTS uncorrectable/protocol errors on incoming stack transaction"
+ },
+ "45": {
+ "desc": "XTS protocol errors on incoming PBUS transaction"
+ },
+ "46": {
+ "desc": "XTS Translate Request Fail"
+ },
+ "47": {
+ "desc": "XTS informational fir that is set when the snooper retries a rpt_hang.check or rpt_hang.poll command."
+ },
+ "48": {
+ "desc": "XTS Reserved, macro bit 8"
+ },
+ "49": {
+ "desc": "XTS Reserved, macro bit 9"
+ },
+ "50": {
+ "desc": "XTS Reserved, macro bit 10"
+ },
+ "51": {
+ "desc": "XTS Reserved, macro bit 11"
+ },
+ "52": {
+ "desc": "XTS Reserved, macro bit 12"
+ },
+ "53": {
+ "desc": "XTS Reserved, macro bit 13"
+ },
+ "54": {
+ "desc": "XTS Reserved, macro bit 14"
+ },
+ "55": {
+ "desc": "XTS Reserved, macro bit 15"
+ },
+ "56": {
+ "desc": "XTS Reserved, macro bit 16"
+ },
+ "57": {
+ "desc": "XTS Reserved, macro bit 17"
+ },
+ "58": {
+ "desc": "XTS Reserved, macro bit 18"
+ },
+ "59": {
+ "desc": "AME Reserved, interrupt"
+ },
+ "60": {
+ "desc": "AME data ECC UE"
+ },
+ "61": {
+ "desc": "AME data SUE"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_fir_1.json b/chip_data/p10_20/node_pau_fir_1.json
new file mode 100644
index 0000000..2f129d1
--- /dev/null
+++ b/chip_data/p10_20/node_pau_fir_1.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_FIR_1": {
+ "instances": {
+ "0": "0x10010C40",
+ "3": "0x11010C40",
+ "4": "0x12010C40",
+ "5": "0x12011440",
+ "6": "0x13010C40",
+ "7": "0x13011440"
+ }
+ },
+ "PAU_FIR_1_MASK": {
+ "instances": {
+ "0": "0x10010C43",
+ "3": "0x11010C43",
+ "4": "0x12010C43",
+ "5": "0x12011443",
+ "6": "0x13010C43",
+ "7": "0x13011443"
+ }
+ },
+ "PAU_FIR_1_ACT0": {
+ "instances": {
+ "0": "0x10010C46",
+ "3": "0x11010C46",
+ "4": "0x12010C46",
+ "5": "0x12011446",
+ "6": "0x13010C46",
+ "7": "0x13011446"
+ }
+ },
+ "PAU_FIR_1_ACT1": {
+ "instances": {
+ "0": "0x10010C47",
+ "3": "0x11010C47",
+ "4": "0x12010C47",
+ "5": "0x12011447",
+ "6": "0x13010C47",
+ "7": "0x13011447"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_1": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_1_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "NDL Brick0 stall"
+ },
+ "1": {
+ "desc": "NDL Brick0 nostall"
+ },
+ "2": {
+ "desc": "NDL Brick1 stall"
+ },
+ "3": {
+ "desc": "NDL Brick1 nostall"
+ },
+ "4": {
+ "desc": "NDL Brick2 stall"
+ },
+ "5": {
+ "desc": "NDL Brick2 nostall"
+ },
+ "6": {
+ "desc": "NDL Brick3 stall"
+ },
+ "7": {
+ "desc": "NDL Brick3 nostall"
+ },
+ "8": {
+ "desc": "NDL Brick4 stall"
+ },
+ "9": {
+ "desc": "NDL Brick4 nostall"
+ },
+ "10": {
+ "desc": "NDL Brick5 stall"
+ },
+ "11": {
+ "desc": "NDL Brick5 nostall"
+ },
+ "12": {
+ "desc": "MISC Register ring error"
+ },
+ "13": {
+ "desc": "MISC Parity error from interrupt base real address register"
+ },
+ "14": {
+ "desc": "MISC Parity error on Indirect SCOM Address register"
+ },
+ "15": {
+ "desc": "MISC Parity error on MISC Control register"
+ },
+ "16": {
+ "desc": "FIR1 Reserved, bit 16"
+ },
+ "17": {
+ "desc": "ATS Invalid TVT entry"
+ },
+ "18": {
+ "desc": "ATS TVT Address range error"
+ },
+ "19": {
+ "desc": "ATS TCE Page access error during TCE cache lookup"
+ },
+ "20": {
+ "desc": "ATS Effective Address hit multiple TCE cache entries"
+ },
+ "21": {
+ "desc": "ATS TCE Page access error during TCE table-walk"
+ },
+ "22": {
+ "desc": "ATS Timeout on TCE tree walk"
+ },
+ "23": {
+ "desc": "ATS Parity error on TCE cache directory array"
+ },
+ "24": {
+ "desc": "ATS Parity error on TCE cache data array"
+ },
+ "25": {
+ "desc": "ATS ECC UE on Effective Address array"
+ },
+ "26": {
+ "desc": "ATS ECC CE on Effective Address array"
+ },
+ "27": {
+ "desc": "ATS ECC UE on TDRmem array"
+ },
+ "28": {
+ "desc": "ATS ECC CE on TDRmem array"
+ },
+ "29": {
+ "desc": "ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk"
+ },
+ "30": {
+ "desc": "ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk"
+ },
+ "31": {
+ "desc": "ATS Parity error on TVT entry"
+ },
+ "32": {
+ "desc": "ATS Parity error on IODA Address Register"
+ },
+ "33": {
+ "desc": "ATS Parity error on ATS Control Register"
+ },
+ "34": {
+ "desc": "ATS Parity error on ATS Timeout Control register"
+ },
+ "35": {
+ "desc": "ATS Invalid IODA Table Address Register Table Select entry"
+ },
+ "36": {
+ "desc": "ATS Reserved, macro bit 19"
+ },
+ "37": {
+ "desc": "kill xlate epoch timeout."
+ },
+ "38": {
+ "desc": "XSL Reserved, macro bit 19."
+ },
+ "39": {
+ "desc": "XSL Reserved, macro bit 20."
+ },
+ "40": {
+ "desc": "XSL Reserved, macro bit 21."
+ },
+ "41": {
+ "desc": "XSL Reserved, macro bit 22."
+ },
+ "42": {
+ "desc": "XSL Reserved, macro bit 23."
+ },
+ "43": {
+ "desc": "XSL Reserved, macro bit 24."
+ },
+ "44": {
+ "desc": "XSL Reserved, macro bit 25."
+ },
+ "45": {
+ "desc": "XSL Reserved, macro bit 26."
+ },
+ "46": {
+ "desc": "XSL Reserved, macro bit 27."
+ },
+ "47": {
+ "desc": "NDL Brick6 stall"
+ },
+ "48": {
+ "desc": "NDL Brick6 nostall"
+ },
+ "49": {
+ "desc": "NDL Brick7 stall"
+ },
+ "50": {
+ "desc": "NDL Brick7 nostall"
+ },
+ "51": {
+ "desc": "NDL Brick8 stall"
+ },
+ "52": {
+ "desc": "NDL Brick8 nostall"
+ },
+ "53": {
+ "desc": "NDL Brick9 stall"
+ },
+ "54": {
+ "desc": "NDL Brick9 nostall"
+ },
+ "55": {
+ "desc": "NDL Brick10 stall"
+ },
+ "56": {
+ "desc": "NDL Brick10 nostall"
+ },
+ "57": {
+ "desc": "NDL Brick11 stall"
+ },
+ "58": {
+ "desc": "NDL Brick11 nostall"
+ },
+ "59": {
+ "desc": "AME ECC CE"
+ },
+ "60": {
+ "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 0)"
+ },
+ "61": {
+ "desc": "MISC Pervasive SCOM satellite signaled internal FSM error (ring 0, sat 1)"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_fir_2.json b/chip_data/p10_20/node_pau_fir_2.json
new file mode 100644
index 0000000..a7d2e00
--- /dev/null
+++ b/chip_data/p10_20/node_pau_fir_2.json
@@ -0,0 +1,340 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_FIR_2": {
+ "instances": {
+ "0": "0x10010C80",
+ "3": "0x11010C80",
+ "4": "0x12010C80",
+ "5": "0x12011480",
+ "6": "0x13010C80",
+ "7": "0x13011480"
+ }
+ },
+ "PAU_FIR_2_MASK": {
+ "instances": {
+ "0": "0x10010C83",
+ "3": "0x11010C83",
+ "4": "0x12010C83",
+ "5": "0x12011483",
+ "6": "0x13010C83",
+ "7": "0x13011483"
+ }
+ },
+ "PAU_FIR_2_ACT0": {
+ "instances": {
+ "0": "0x10010C86",
+ "3": "0x11010C86",
+ "4": "0x12010C86",
+ "5": "0x12011486",
+ "6": "0x13010C86",
+ "7": "0x13011486"
+ }
+ },
+ "PAU_FIR_2_ACT1": {
+ "instances": {
+ "0": "0x10010C87",
+ "3": "0x11010C87",
+ "4": "0x12010C87",
+ "5": "0x12011487",
+ "6": "0x13010C87",
+ "7": "0x13011487"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_FIR_2": {
+ "instances": [0, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_FIR_2_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OTL Brick2 translation fault"
+ },
+ "1": {
+ "desc": "OTL Brick3 translation fault"
+ },
+ "2": {
+ "desc": "OTL Brick4 translation fault"
+ },
+ "3": {
+ "desc": "OTL Brick5 translation fault"
+ },
+ "4": {
+ "desc": "OTL TL credit counter overflow caused by return_tl_credits"
+ },
+ "5": {
+ "desc": "OTL RX acTag specified in a command is outside the configured specification set"
+ },
+ "6": {
+ "desc": "OTL RX acTag specified in the command points to an invalid entry"
+ },
+ "7": {
+ "desc": "OTL RX reserved opcode used"
+ },
+ "8": {
+ "desc": "OTL RX return_tl_credit command found outside slot0"
+ },
+ "9": {
+ "desc": "OTL RX bad opcode and template combination"
+ },
+ "10": {
+ "desc": "OTL RX unsupported template format"
+ },
+ "11": {
+ "desc": "OTL RX bad template x00 format"
+ },
+ "12": {
+ "desc": "OTL RX control flit overrun"
+ },
+ "13": {
+ "desc": "OTL RX unexpected data flit"
+ },
+ "14": {
+ "desc": "OTL RX DL link down"
+ },
+ "15": {
+ "desc": "OTL RX bad data received on command"
+ },
+ "16": {
+ "desc": "OTL RX bad data received on response"
+ },
+ "17": {
+ "desc": "OTL RX AP response not allowed (CAPPTag not recognized)"
+ },
+ "18": {
+ "desc": "OR of all OTL parity errors"
+ },
+ "19": {
+ "desc": "OR of all OTL ECC CE errors"
+ },
+ "20": {
+ "desc": "OR of all OTL ECC UE errors"
+ },
+ "21": {
+ "desc": "RXO OP Errors"
+ },
+ "22": {
+ "desc": "RXO Internal Errors"
+ },
+ "23": {
+ "desc": "OTL RXI fifo overrun"
+ },
+ "24": {
+ "desc": "OTL RXI control flit data run length invalid"
+ },
+ "25": {
+ "desc": "OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL"
+ },
+ "26": {
+ "desc": "OTL RXI bad data received vc2"
+ },
+ "27": {
+ "desc": "OTL RXI dcp2 fifo overrun"
+ },
+ "28": {
+ "desc": "OTL RXI vc1 fifo overrun"
+ },
+ "29": {
+ "desc": "OTL RXI vc2 fifo overrun"
+ },
+ "30": {
+ "desc": "Opcode data length not supported"
+ },
+ "31": {
+ "desc": "OTL TXI opcode error"
+ },
+ "32": {
+ "desc": "malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2)"
+ },
+ "33": {
+ "desc": "OTL Happi no bar match"
+ },
+ "34": {
+ "desc": "OTL Reserved, macro bit 30"
+ },
+ "35": {
+ "desc": "OTL Reserved, macro bit 31"
+ },
+ "36": {
+ "desc": "MMIO invalidate requested while one is in progress"
+ },
+ "37": {
+ "desc": "Unexpected ITAG returned on itag completion port 0"
+ },
+ "38": {
+ "desc": "Unexpected ITAG returned on itag completion port 1"
+ },
+ "39": {
+ "desc": "Unexpected Read PEE completion"
+ },
+ "40": {
+ "desc": "Unexpected Checkout response"
+ },
+ "41": {
+ "desc": "Translation request while SPAP is invalid"
+ },
+ "42": {
+ "desc": "Read a PEE which was not valid"
+ },
+ "43": {
+ "desc": "Bloom filter protection error"
+ },
+ "44": {
+ "desc": "Translation request to non-valid TA"
+ },
+ "45": {
+ "desc": "TA Translation request to an invalid TA"
+ },
+ "46": {
+ "desc": "correctable array error (SBE)"
+ },
+ "47": {
+ "desc": "uncorrectable array error (UE or parity)"
+ },
+ "48": {
+ "desc": "S/TLBI buffer overflow"
+ },
+ "49": {
+ "desc": "SBE correctable error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "50": {
+ "desc": "UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "51": {
+ "desc": "SUE error on Powerbus checkout response data or Powerbus PEE read data"
+ },
+ "52": {
+ "desc": "PA mem_hit when bar mode is nonzero"
+ },
+ "53": {
+ "desc": "XSL Reserved, macro bit 17"
+ },
+ "54": {
+ "desc": "OTL Brick0 translation fault"
+ },
+ "55": {
+ "desc": "OTL Brick1 translation fault"
+ },
+ "56": {
+ "desc": "AME ECC UE on control information or state bit errors that are contained within AME and ATL"
+ },
+ "57": {
+ "desc": "AME ECC UE on control information or state bit errors that can affect correctness of external logic such as XSL castout"
+ },
+ "58": {
+ "desc": "AME Logic errors that are contained within AME and ATL"
+ },
+ "59": {
+ "desc": "AME Logic errors that can affect correctness of external logic such as XSL castout"
+ },
+ "60": {
+ "desc": "AME firmware-detected fatal error conditions"
+ },
+ "61": {
+ "desc": "AME Reserved"
+ },
+ "62": {
+ "desc": "Unused FIR"
+ },
+ "63": {
+ "desc": "Unused FIR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_local_fir.json b/chip_data/p10_20/node_pau_local_fir.json
new file mode 100644
index 0000000..7999ea1
--- /dev/null
+++ b/chip_data/p10_20/node_pau_local_fir.json
@@ -0,0 +1,445 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_LOCAL_FIR": {
+ "instances": {
+ "0": "0x10040100",
+ "1": "0x11040100",
+ "2": "0x12040100",
+ "3": "0x13040100"
+ }
+ },
+ "PAU_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x10040103",
+ "1": "0x11040103",
+ "2": "0x12040103",
+ "3": "0x13040103"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x10040106",
+ "1": "0x11040106",
+ "2": "0x12040106",
+ "3": "0x13040106"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x10040107",
+ "1": "0x11040107",
+ "2": "0x12040107",
+ "3": "0x13040107"
+ }
+ },
+ "PAU_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x10040109",
+ "1": "0x11040109",
+ "2": "0x12040109",
+ "3": "0x13040109"
+ }
+ },
+ "PAU_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x10040108",
+ "1": "0x11040108",
+ "2": "0x12040108",
+ "3": "0x13040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_LOCAL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_phy_fir.json b/chip_data/p10_20/node_pau_phy_fir.json
new file mode 100644
index 0000000..e367d6f
--- /dev/null
+++ b/chip_data/p10_20/node_pau_phy_fir.json
@@ -0,0 +1,260 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_PHY_FIR": {
+ "instances": {
+ "0": "0x10012C00",
+ "1": "0x11012C00",
+ "2": "0x12012C00",
+ "3": "0x13012C00"
+ }
+ },
+ "PAU_PHY_FIR_MASK": {
+ "instances": {
+ "0": "0x10012C03",
+ "1": "0x11012C03",
+ "2": "0x12012C03",
+ "3": "0x13012C03"
+ }
+ },
+ "PAU_PHY_FIR_ACT0": {
+ "instances": {
+ "0": "0x10012C06",
+ "1": "0x11012C06",
+ "2": "0x12012C06",
+ "3": "0x13012C06"
+ }
+ },
+ "PAU_PHY_FIR_ACT1": {
+ "instances": {
+ "0": "0x10012C07",
+ "1": "0x11012C07",
+ "2": "0x12012C07",
+ "3": "0x13012C07"
+ }
+ },
+ "PAU_PHY_FIR_WOF": {
+ "instances": {
+ "0": "0x10012C08",
+ "1": "0x11012C08",
+ "2": "0x12012C08",
+ "3": "0x13012C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_PHY_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PHY_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "1": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "2": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "3": {
+ "desc": "FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "4": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0)."
+ },
+ "5": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1)."
+ },
+ "6": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0)."
+ },
+ "7": {
+ "desc": "FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1)."
+ },
+ "8": {
+ "desc": "FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred."
+ },
+ "9": {
+ "desc": "FIR Register - A PPE internal error has occurred."
+ },
+ "10": {
+ "desc": "FIR Register - A PPE external error has occurred."
+ },
+ "11": {
+ "desc": "FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred."
+ },
+ "12": {
+ "desc": "FIR Register - A PPE Halt due to Debug has occurred."
+ },
+ "13": {
+ "desc": "FIR Register - PPE Halted."
+ },
+ "14": {
+ "desc": "FIR Register - A PPE Watchdog Timeout has occurred."
+ },
+ "15": {
+ "desc": "FIR Register - A PPE Array Scrub was missed."
+ },
+ "16": {
+ "desc": "FIR Register - A PPE Array uncorrectable error has occurred."
+ },
+ "17": {
+ "desc": "FIR Register - A PPE Array correctable error has occurred."
+ },
+ "18": {
+ "desc": "FIR Register - A PPE Code Recal Abort has occurred."
+ },
+ "19": {
+ "desc": "FIR Register - A PPE Code Fatal Error has occurred."
+ },
+ "20": {
+ "desc": "FIR Register - A PPE Code Warning has occurred."
+ },
+ "21": {
+ "desc": "FIR Register - A PPE Code DFT Error has occurred."
+ },
+ "22": {
+ "desc": "FIR Register - A PPE Code Recal Not Run has occurred."
+ },
+ "23": {
+ "desc": "FIR Register - A PPE Code Thread Locked has occurred."
+ },
+ "24": {
+ "desc": "FIR Register - A PPE Code FIR 6 has occurred."
+ },
+ "25": {
+ "desc": "FIR Register - A PPE Code FIR 7 has occurred."
+ },
+ "26": {
+ "desc": "FIR Register- A SCOM FSM or FIR register parity error has occurred."
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pau_ptl_fir.json b/chip_data/p10_20/node_pau_ptl_fir.json
new file mode 100644
index 0000000..6548c70
--- /dev/null
+++ b/chip_data/p10_20/node_pau_ptl_fir.json
@@ -0,0 +1,390 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PAU_PTL_FIR": {
+ "instances": {
+ "0": "0x10011800",
+ "1": "0x11011800",
+ "2": "0x12011800",
+ "3": "0x13011800"
+ }
+ },
+ "PAU_PTL_FIR_MASK": {
+ "instances": {
+ "0": "0x10011803",
+ "1": "0x11011803",
+ "2": "0x12011803",
+ "3": "0x13011803"
+ }
+ },
+ "PAU_PTL_FIR_ACT0": {
+ "instances": {
+ "0": "0x10011806",
+ "1": "0x11011806",
+ "2": "0x12011806",
+ "3": "0x13011806"
+ }
+ },
+ "PAU_PTL_FIR_ACT1": {
+ "instances": {
+ "0": "0x10011807",
+ "1": "0x11011807",
+ "2": "0x12011807",
+ "3": "0x13011807"
+ }
+ },
+ "PAU_PTL_FIR_WOF": {
+ "instances": {
+ "0": "0x10011808",
+ "1": "0x11011808",
+ "2": "0x12011808",
+ "3": "0x13011808"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PAU_PTL_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PAU_PTL_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "fmr00 trained. Even PTL, even half."
+ },
+ "1": {
+ "desc": "fmr01 trained. Even PTL, odd half."
+ },
+ "2": {
+ "desc": "fmr02 trained. Odd PTL, even half."
+ },
+ "3": {
+ "desc": "fmr03 trained. Odd PTL, odd half."
+ },
+ "4": {
+ "desc": "dob01 ue"
+ },
+ "5": {
+ "desc": "dob01 ce"
+ },
+ "6": {
+ "desc": "dob01 sue"
+ },
+ "7": {
+ "desc": "data outbound switch internal error - even PTL.",
+ "child_node": {
+ "name": "PB_DOB01_DIB01_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "8": {
+ "desc": "dob23 ue"
+ },
+ "9": {
+ "desc": "dob23 ce"
+ },
+ "10": {
+ "desc": "dob23 sue"
+ },
+ "11": {
+ "desc": "data outbound switch internal error - odd PTL.",
+ "child_node": {
+ "name": "PB_DOB23_DIB23_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "12": {
+ "desc": "Even PTL, even framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "13": {
+ "desc": "Even PTL, outbound switch cmd/presp/cresp internal error"
+ },
+ "14": {
+ "desc": "Even PTL, odd framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "15": {
+ "desc": "Odd PTL, even framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "16": {
+ "desc": "Odd PTL, outbound switch cmd/presp/cresp internal error"
+ },
+ "17": {
+ "desc": "Odd PTL, odd framer internal error",
+ "child_node": {
+ "name": "PB_FM0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "18": {
+ "desc": "Even PTL, even parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "19": {
+ "desc": "Even PTL, odd parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "20": {
+ "desc": "Odd PTL, even parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "21": {
+ "desc": "Odd PTL, odd parser internal error",
+ "child_node": {
+ "name": "PB_PR0123_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "22": {
+ "desc": "Even PTL, even link down"
+ },
+ "23": {
+ "desc": "Even PTL, odd link down"
+ },
+ "24": {
+ "desc": "Odd PTL, even link down"
+ },
+ "25": {
+ "desc": "Odd PTL, odd link down"
+ },
+ "26": {
+ "desc": "Even PTL data inbound switch internal error",
+ "child_node": {
+ "name": "PB_DOB01_DIB01_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "27": {
+ "desc": "Odd PTL data inbound switch internal error",
+ "child_node": {
+ "name": "PB_DOB23_DIB23_INT_ERR",
+ "inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ },
+ "28": {
+ "desc": "mailbox 00 special attention"
+ },
+ "29": {
+ "desc": "mailbox 01 special attention"
+ },
+ "30": {
+ "desc": "mailbox 10 special attention"
+ },
+ "31": {
+ "desc": "mailbox 11 special attention"
+ },
+ "32": {
+ "desc": "mailbox 20 special attention"
+ },
+ "33": {
+ "desc": "mailbox 21 special attention"
+ },
+ "34": {
+ "desc": "mailbox 30 special attention"
+ },
+ "35": {
+ "desc": "mailbox 31 special attention"
+ },
+ "36": {
+ "desc": "ptl0 spare"
+ },
+ "37": {
+ "desc": "ptl1 spare"
+ },
+ "38": {
+ "desc": "ptl2 spare"
+ },
+ "39": {
+ "desc": "ptl3 spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PAU_PTL_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_ext_fir.json b/chip_data/p10_20/node_pb_ext_fir.json
new file mode 100644
index 0000000..821a572
--- /dev/null
+++ b/chip_data/p10_20/node_pb_ext_fir.json
@@ -0,0 +1,93 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_EXT_FIR": {
+ "instances": {
+ "0": "0x030113AE"
+ }
+ },
+ "PB_EXT_FIR_MASK": {
+ "instances": {
+ "0": "0x030113B1"
+ }
+ },
+ "PB_EXT_FIR_ACT0": {
+ "instances": {
+ "0": "0x030113B4"
+ }
+ },
+ "PB_EXT_FIR_ACT1": {
+ "instances": {
+ "0": "0x030113B5"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_EXT_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_EXT_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "pb_x0_fir_err"
+ },
+ "1": {
+ "desc": "pb_x1_fir_err"
+ },
+ "2": {
+ "desc": "pb_x2_fir_err"
+ },
+ "3": {
+ "desc": "pb_x3_fir_err"
+ },
+ "4": {
+ "desc": "pb_x4_fir_err"
+ },
+ "5": {
+ "desc": "pb_x5_fir_err"
+ },
+ "6": {
+ "desc": "pb_x6_fir_err"
+ },
+ "7": {
+ "desc": "pb_x7_fir_err"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_en1.json b/chip_data/p10_20/node_pb_station_fir_en1.json
new file mode 100644
index 0000000..ce80135
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_en1.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_EN1": {
+ "instances": {
+ "0": "0x03011200"
+ }
+ },
+ "PB_STATION_FIR_EN1_MASK": {
+ "instances": {
+ "0": "0x03011203"
+ }
+ },
+ "PB_STATION_FIR_EN1_ACT0": {
+ "instances": {
+ "0": "0x03011206"
+ }
+ },
+ "PB_STATION_FIR_EN1_ACT1": {
+ "instances": {
+ "0": "0x03011207"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN1": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN1_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN1",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_en2.json b/chip_data/p10_20/node_pb_station_fir_en2.json
new file mode 100644
index 0000000..405ed71
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_en2.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_EN2": {
+ "instances": {
+ "0": "0x03011240"
+ }
+ },
+ "PB_STATION_FIR_EN2_MASK": {
+ "instances": {
+ "0": "0x03011243"
+ }
+ },
+ "PB_STATION_FIR_EN2_ACT0": {
+ "instances": {
+ "0": "0x03011246"
+ }
+ },
+ "PB_STATION_FIR_EN2_ACT1": {
+ "instances": {
+ "0": "0x03011247"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN2": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN2_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN2",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_en3.json b/chip_data/p10_20/node_pb_station_fir_en3.json
new file mode 100644
index 0000000..7ea9b44
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_en3.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_EN3": {
+ "instances": {
+ "0": "0x03011280"
+ }
+ },
+ "PB_STATION_FIR_EN3_MASK": {
+ "instances": {
+ "0": "0x03011283"
+ }
+ },
+ "PB_STATION_FIR_EN3_ACT0": {
+ "instances": {
+ "0": "0x03011286"
+ }
+ },
+ "PB_STATION_FIR_EN3_ACT1": {
+ "instances": {
+ "0": "0x03011287"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN3": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN3_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN3",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_en4.json b/chip_data/p10_20/node_pb_station_fir_en4.json
new file mode 100644
index 0000000..6e3996f
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_en4.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_EN4": {
+ "instances": {
+ "0": "0x030112C0"
+ }
+ },
+ "PB_STATION_FIR_EN4_MASK": {
+ "instances": {
+ "0": "0x030112C3"
+ }
+ },
+ "PB_STATION_FIR_EN4_ACT0": {
+ "instances": {
+ "0": "0x030112C6"
+ }
+ },
+ "PB_STATION_FIR_EN4_ACT1": {
+ "instances": {
+ "0": "0x030112C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EN4": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EN4_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EN4",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_eq.json b/chip_data/p10_20/node_pb_station_fir_eq.json
new file mode 100644
index 0000000..aa8cead
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_eq.json
@@ -0,0 +1,240 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_EQ": {
+ "instances": {
+ "0": "0x03011000",
+ "1": "0x03011040",
+ "2": "0x03011080",
+ "3": "0x030110C0",
+ "4": "0x03011100",
+ "5": "0x03011140",
+ "6": "0x03011180",
+ "7": "0x030111C0"
+ }
+ },
+ "PB_STATION_FIR_EQ_MASK": {
+ "instances": {
+ "0": "0x03011003",
+ "1": "0x03011043",
+ "2": "0x03011083",
+ "3": "0x030110C3",
+ "4": "0x03011103",
+ "5": "0x03011143",
+ "6": "0x03011183",
+ "7": "0x030111C3"
+ }
+ },
+ "PB_STATION_FIR_EQ_ACT0": {
+ "instances": {
+ "0": "0x03011006",
+ "1": "0x03011046",
+ "2": "0x03011086",
+ "3": "0x030110C6",
+ "4": "0x03011106",
+ "5": "0x03011146",
+ "6": "0x03011186",
+ "7": "0x030111C6"
+ }
+ },
+ "PB_STATION_FIR_EQ_ACT1": {
+ "instances": {
+ "0": "0x03011007",
+ "1": "0x03011047",
+ "2": "0x03011087",
+ "3": "0x030110C7",
+ "4": "0x03011107",
+ "5": "0x03011147",
+ "6": "0x03011187",
+ "7": "0x030111C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_EQ": {
+ "instances": [0, 1, 2, 3, 4, 5, 6, 7],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3, 4, 5, 6, 7],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_EQ_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_EQ",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_es1.json b/chip_data/p10_20/node_pb_station_fir_es1.json
new file mode 100644
index 0000000..7e6b6fc
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_es1.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_ES1": {
+ "instances": {
+ "0": "0x03011300"
+ }
+ },
+ "PB_STATION_FIR_ES1_MASK": {
+ "instances": {
+ "0": "0x03011303"
+ }
+ },
+ "PB_STATION_FIR_ES1_ACT0": {
+ "instances": {
+ "0": "0x03011306"
+ }
+ },
+ "PB_STATION_FIR_ES1_ACT1": {
+ "instances": {
+ "0": "0x03011307"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES1": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES1_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES1",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_es2.json b/chip_data/p10_20/node_pb_station_fir_es2.json
new file mode 100644
index 0000000..9c71bcb
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_es2.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_ES2": {
+ "instances": {
+ "0": "0x03011340"
+ }
+ },
+ "PB_STATION_FIR_ES2_MASK": {
+ "instances": {
+ "0": "0x03011343"
+ }
+ },
+ "PB_STATION_FIR_ES2_ACT0": {
+ "instances": {
+ "0": "0x03011346"
+ }
+ },
+ "PB_STATION_FIR_ES2_ACT1": {
+ "instances": {
+ "0": "0x03011347"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES2": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES2_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES2",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_es3.json b/chip_data/p10_20/node_pb_station_fir_es3.json
new file mode 100644
index 0000000..336622e
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_es3.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_ES3": {
+ "instances": {
+ "0": "0x03011380"
+ }
+ },
+ "PB_STATION_FIR_ES3_MASK": {
+ "instances": {
+ "0": "0x03011383"
+ }
+ },
+ "PB_STATION_FIR_ES3_ACT0": {
+ "instances": {
+ "0": "0x03011386"
+ }
+ },
+ "PB_STATION_FIR_ES3_ACT1": {
+ "instances": {
+ "0": "0x03011387"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES3": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES3_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "inactive_link_error"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "active_link_error"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES3",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pb_station_fir_es4.json b/chip_data/p10_20/node_pb_station_fir_es4.json
new file mode 100644
index 0000000..e09ceaa
--- /dev/null
+++ b/chip_data/p10_20/node_pb_station_fir_es4.json
@@ -0,0 +1,205 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_STATION_FIR_ES4": {
+ "instances": {
+ "0": "0x030113C0"
+ }
+ },
+ "PB_STATION_FIR_ES4_MASK": {
+ "instances": {
+ "0": "0x030113C3"
+ }
+ },
+ "PB_STATION_FIR_ES4_ACT0": {
+ "instances": {
+ "0": "0x030113C6"
+ }
+ },
+ "PB_STATION_FIR_ES4_ACT1": {
+ "instances": {
+ "0": "0x030113C7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_STATION_FIR_ES4": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_STATION_FIR_ES4_ACT1"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "protocol_error"
+ },
+ "1": {
+ "desc": "overflow_error"
+ },
+ "2": {
+ "desc": "hw_parity_error"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "coherency_error"
+ },
+ "5": {
+ "desc": "cresp_addr_error"
+ },
+ "6": {
+ "desc": "cresp_error"
+ },
+ "7": {
+ "desc": "hang_recovery_limit_error"
+ },
+ "8": {
+ "desc": "spare"
+ },
+ "9": {
+ "desc": "hang_recovery_gte_level1"
+ },
+ "10": {
+ "desc": "force_mp_ipl"
+ },
+ "11": {
+ "desc": "pb_cmd_snooper_error"
+ },
+ "12": {
+ "desc": "data_overflow_error"
+ },
+ "13": {
+ "desc": "data_protocol_error"
+ },
+ "14": {
+ "desc": "data_route_error"
+ },
+ "15": {
+ "desc": "fir_compab_trigger"
+ },
+ "16": {
+ "desc": "link0_protocol_error"
+ },
+ "17": {
+ "desc": "link0_overflow_error"
+ },
+ "18": {
+ "desc": "link0_hw_parity_error"
+ },
+ "19": {
+ "desc": "link1_protocol_error"
+ },
+ "20": {
+ "desc": "link1_overflow_error"
+ },
+ "21": {
+ "desc": "link1_hw_parity_error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PB_STATION_FIR_ES4",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pbaf_fir.json b/chip_data/p10_20/node_pbaf_fir.json
new file mode 100644
index 0000000..cd9864f
--- /dev/null
+++ b/chip_data/p10_20/node_pbaf_fir.json
@@ -0,0 +1,228 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PBAF_FIR": {
+ "instances": {
+ "0": "0x03011DC0"
+ }
+ },
+ "PBAF_FIR_MASK": {
+ "instances": {
+ "0": "0x03011DC3"
+ }
+ },
+ "PBAF_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011DC6"
+ }
+ },
+ "PBAF_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011DC7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PBAF_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAF_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PB CRESP Addr Error Received for Forwarded Read Request"
+ },
+ "1": {
+ "desc": "PB Read Data Timeout for Forwarded Request"
+ },
+ "2": {
+ "desc": "PB Read Data SUE Error for Forwarded Request"
+ },
+ "3": {
+ "desc": "PB Read Data UE Error for Forwarded Request"
+ },
+ "4": {
+ "desc": "PB Read Data CE Error for Forwarded Request"
+ },
+ "5": {
+ "desc": "PB Unexpected CRESP"
+ },
+ "6": {
+ "desc": "PB Unexpected Data"
+ },
+ "7": {
+ "desc": "PB Tag parity Error Detected"
+ },
+ "8": {
+ "desc": "PB CRESP Addr Error Received for Forwarded Write Request"
+ },
+ "9": {
+ "desc": "PB Invalid CRESP"
+ },
+ "10": {
+ "desc": "PB CRESP ACK Dead response received for Forwarded Read request"
+ },
+ "11": {
+ "desc": "PB OPERATIONAL Timeout detected"
+ },
+ "12": {
+ "desc": "BCUE PowerBus Link Dead"
+ },
+ "13": {
+ "desc": "PB CRESP Addr Error Received for BCUE Write Request"
+ },
+ "14": {
+ "desc": "BCDE PowerBus Link Dead"
+ },
+ "15": {
+ "desc": "PB CRESP Addr Error Received for BCDE Read Request"
+ },
+ "16": {
+ "desc": "PB Read Data Timeout for BCDE Request"
+ },
+ "17": {
+ "desc": "PB Read Data SUE Error for BCDE Request"
+ },
+ "18": {
+ "desc": "PB Read Data UE Error for BCDE Request"
+ },
+ "19": {
+ "desc": "PB Read Data CE Error for BCDE Request"
+ },
+ "20": {
+ "desc": "Internal Logic Error"
+ },
+ "21": {
+ "desc": "Byte count is less than full cache line"
+ },
+ "22": {
+ "desc": "PBAXRCV Low data before High Data"
+ },
+ "23": {
+ "desc": "PBAXRCV Low data timeout"
+ },
+ "24": {
+ "desc": "PBAXRCV Reservation data timeout"
+ },
+ "25": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "26": {
+ "desc": "PBAXSND engine retry threshold reached sending Phase 1"
+ },
+ "27": {
+ "desc": "PBAXSND engine retry threshold reached sending Phase 2"
+ },
+ "28": {
+ "desc": "PBAXSND Reservation Timeout"
+ },
+ "29": {
+ "desc": "PB CRESP ACK Dead response received"
+ },
+ "30": {
+ "desc": "PBAXIRCV Low data before High Data"
+ },
+ "31": {
+ "desc": "PBAXIRCV Low data timeout"
+ },
+ "32": {
+ "desc": "PBAXIRCV Reservation data timeout"
+ },
+ "33": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "34": {
+ "desc": "PBAXISND engine retry threshold reached sending Phase 1"
+ },
+ "35": {
+ "desc": "PBAXISND engine retry threshold reached sending Phase 2"
+ },
+ "36": {
+ "desc": "PBAXISND Reservation Timeout"
+ },
+ "37": {
+ "desc": "spare"
+ },
+ "38": {
+ "desc": "spare"
+ },
+ "39": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PBAF_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pbao_fir.json b/chip_data/p10_20/node_pbao_fir.json
new file mode 100644
index 0000000..2d5fc9d
--- /dev/null
+++ b/chip_data/p10_20/node_pbao_fir.json
@@ -0,0 +1,168 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PBAO_FIR": {
+ "instances": {
+ "0": "0x01010CC0"
+ }
+ },
+ "PBAO_FIR_MASK": {
+ "instances": {
+ "0": "0x01010CC3"
+ }
+ },
+ "PBAO_FIR_ACT0": {
+ "instances": {
+ "0": "0x01010CC6"
+ }
+ },
+ "PBAO_FIR_ACT1": {
+ "instances": {
+ "0": "0x01010CC7"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PBAO_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PBAO_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "OCI Address Parity Error Det"
+ },
+ "1": {
+ "desc": "PBA OCI Slave Initialization Error"
+ },
+ "2": {
+ "desc": "OCI Write Data Parity Error Detected"
+ },
+ "3": {
+ "desc": "spare"
+ },
+ "4": {
+ "desc": "BCUE Setup Error"
+ },
+ "5": {
+ "desc": "BCUE Read Data Parity Error OR MRDERR Asserted"
+ },
+ "6": {
+ "desc": "BCDE Setup Error"
+ },
+ "7": {
+ "desc": "BCDE Write Data error indicated by OCI Slave"
+ },
+ "8": {
+ "desc": "Internal Logic Error"
+ },
+ "9": {
+ "desc": "Illegal access to OCI Register"
+ },
+ "10": {
+ "desc": "Push Write Error"
+ },
+ "11": {
+ "desc": "Push Write Error"
+ },
+ "12": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "13": {
+ "desc": "Illegal PBAX Flow"
+ },
+ "14": {
+ "desc": "PBAXSND Reservation Error"
+ },
+ "15": {
+ "desc": "PBAXISND Reservation Error"
+ },
+ "16": {
+ "desc": "htm fifo interface fequency variation error"
+ },
+ "17": {
+ "desc": "Invalide PB topology translate table entry"
+ },
+ "18": {
+ "desc": "spare"
+ },
+ "19": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PBAO_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pci_etu_fir.json b/chip_data/p10_20/node_pci_etu_fir.json
new file mode 100644
index 0000000..9530d14
--- /dev/null
+++ b/chip_data/p10_20/node_pci_etu_fir.json
@@ -0,0 +1,322 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PCI_ETU_FIR": {
+ "instances": {
+ "0": "0x08010908",
+ "1": "0x08010948",
+ "2": "0x08010988",
+ "3": "0x09010908",
+ "4": "0x09010948",
+ "5": "0x09010988"
+ }
+ },
+ "PCI_ETU_FIR_MASK": {
+ "instances": {
+ "0": "0x0801090B",
+ "1": "0x0801094B",
+ "2": "0x0801098B",
+ "3": "0x0901090B",
+ "4": "0x0901094B",
+ "5": "0x0901098B"
+ }
+ },
+ "PCI_ETU_FIR_ACT0": {
+ "instances": {
+ "0": "0x0801090E",
+ "1": "0x0801094E",
+ "2": "0x0801098E",
+ "3": "0x0901090E",
+ "4": "0x0901094E",
+ "5": "0x0901098E"
+ }
+ },
+ "PCI_ETU_FIR_ACT1": {
+ "instances": {
+ "0": "0x0801090F",
+ "1": "0x0801094F",
+ "2": "0x0801098F",
+ "3": "0x0901090F",
+ "4": "0x0901094F",
+ "5": "0x0901098F"
+ }
+ },
+ "PCI_ETU_FIR_WOF": {
+ "instances": {
+ "0": "0x08010910",
+ "1": "0x08010950",
+ "2": "0x08010990",
+ "3": "0x09010910",
+ "4": "0x09010950",
+ "5": "0x09010990"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_ETU_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_ETU_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "AIB_COMMAND_INVALID"
+ },
+ "1": {
+ "desc": "AIB_ADDRESS_INVALID"
+ },
+ "2": {
+ "desc": "AIB_ACCESS_ERROR"
+ },
+ "3": {
+ "desc": "PAPR_OUTBOUND_INJECT_ERROR"
+ },
+ "4": {
+ "desc": "AIB_FATAL_CLASS_ERROR"
+ },
+ "5": {
+ "desc": "AIB_INF_CLASS_ERROR"
+ },
+ "6": {
+ "desc": "spare"
+ },
+ "7": {
+ "desc": "PE_STOP_STATE_SIGNALED"
+ },
+ "8": {
+ "desc": "OUT_COMMON_ARRAY_FATAL_ERROR"
+ },
+ "9": {
+ "desc": "OUT_COMMON_LATCH_FATAL_ERROR"
+ },
+ "10": {
+ "desc": "OUT_COMMON_LOGIC_FATAL_ERROR"
+ },
+ "11": {
+ "desc": "BLIF_OUT_INTERFACE_PARITY_ERROR"
+ },
+ "12": {
+ "desc": "CFG_WRITE_CA_OR_UR_RESPONSE"
+ },
+ "13": {
+ "desc": "MMIO_REQUEST_TIMEOUT"
+ },
+ "14": {
+ "desc": "OUT_RRB_SOURCED_ERROR"
+ },
+ "15": {
+ "desc": "CFG_LOGIC_SIGNALED_ERROR"
+ },
+ "16": {
+ "desc": "RSB_REG_REQUEST_ADDRESS_ERROR"
+ },
+ "17": {
+ "desc": "RSB_FDA_FATAL_ERROR"
+ },
+ "18": {
+ "desc": "RSB_FDA_INF_ERROR"
+ },
+ "19": {
+ "desc": "RSB_FDB_FATAL_ERROR"
+ },
+ "20": {
+ "desc": "RSB_FDB_INF_ERROR"
+ },
+ "21": {
+ "desc": "RSB_ERR_FATAL_ERROR"
+ },
+ "22": {
+ "desc": "RSB_ERR_INF_ERROR"
+ },
+ "23": {
+ "desc": "RSB_DBG_FATAL_ERROR"
+ },
+ "24": {
+ "desc": "RSB_DBG_INF_ERROR"
+ },
+ "25": {
+ "desc": "PCIE_REQUEST_ACCESS_ERROR"
+ },
+ "26": {
+ "desc": "RSB_BUS_LOGIC_ERROR"
+ },
+ "27": {
+ "desc": "RSB_UVI_FATAL_ERROR"
+ },
+ "28": {
+ "desc": "RSB_UVI_INF_ERROR"
+ },
+ "29": {
+ "desc": "SCOM_FATAL_ERROR"
+ },
+ "30": {
+ "desc": "SCOM_INF_ERROR"
+ },
+ "31": {
+ "desc": "PCIE_MACRO_ERROR_ACTIVE_STATUS"
+ },
+ "32": {
+ "desc": "ARB_IODA_FATAL_ERROR"
+ },
+ "33": {
+ "desc": "ARB_MSI_PE_MATCH_ERROR"
+ },
+ "34": {
+ "desc": "ARB_MSI_ADDRESS_ERROR"
+ },
+ "35": {
+ "desc": "ARB_TVT_ERROR"
+ },
+ "36": {
+ "desc": "ARB_RCVD_FATAL_ERROR_MSG"
+ },
+ "37": {
+ "desc": "ARB_RCVD_NONFATAL_ERROR_MSG"
+ },
+ "38": {
+ "desc": "ARB_RCVD_CORRECTIBLE_ERROR_MSG"
+ },
+ "39": {
+ "desc": "PAPR_INBOUND_INJECT_ERROR"
+ },
+ "40": {
+ "desc": "ARB_COMMON_FATAL_ERROR"
+ },
+ "41": {
+ "desc": "ARB_TABLE_BAR_DISABLED_ERROR"
+ },
+ "42": {
+ "desc": "ARB_BLIF_COMPLETION_ERROR"
+ },
+ "43": {
+ "desc": "ARB_PCT_TIMEOUT_ERROR"
+ },
+ "44": {
+ "desc": "ARB_ECC_CORRECTABLE_ERROR"
+ },
+ "45": {
+ "desc": "ARB_ECC_UNCORRECTABLE_ERROR"
+ },
+ "46": {
+ "desc": "ARB_TLP_POISON_SIGNALED"
+ },
+ "47": {
+ "desc": "ARB_RTT_PENUM_INVALID_ERROR"
+ },
+ "48": {
+ "desc": "MRG_COMMON_FATAL_ERROR"
+ },
+ "49": {
+ "desc": "MRG_TABLE_BAR_DISABLED_ERROR"
+ },
+ "50": {
+ "desc": "MRG_ECC_CORRECTABLE_ERROR"
+ },
+ "51": {
+ "desc": "MRG_ECC_UNCORRECTABLE_ERROR"
+ },
+ "52": {
+ "desc": "MRG_AIB2_TX_TIMEOUT_ERROR"
+ },
+ "53": {
+ "desc": "MRG_MRT_ERROR"
+ },
+ "54": {
+ "desc": "spare"
+ },
+ "55": {
+ "desc": "spare"
+ },
+ "56": {
+ "desc": "TCE_IODA_PAGE_ACCESS_ERROR"
+ },
+ "57": {
+ "desc": "TCE_REQUEST_TIMEOUT_ERROR"
+ },
+ "58": {
+ "desc": "TCE_UNEXPECTED_RESPONSE_ERROR"
+ },
+ "59": {
+ "desc": "TCE_COMMON_FATAL_ERROR"
+ },
+ "60": {
+ "desc": "TCE_ECC_CORRECTABLE_ERROR"
+ },
+ "61": {
+ "desc": "TCE_ECC_UNCORRECTABLE_ERROR"
+ },
+ "62": {
+ "desc": "spare"
+ },
+ "63": {
+ "desc": "FIR_INTERNAL_PARITY_ERROR"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pci_fir.json b/chip_data/p10_20/node_pci_fir.json
new file mode 100644
index 0000000..4568823
--- /dev/null
+++ b/chip_data/p10_20/node_pci_fir.json
@@ -0,0 +1,161 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PCI_FIR": {
+ "instances": {
+ "0": "0x08010840",
+ "1": "0x08010880",
+ "2": "0x080108C0",
+ "3": "0x09010840",
+ "4": "0x09010880",
+ "5": "0x090108C0"
+ }
+ },
+ "PCI_FIR_MASK": {
+ "instances": {
+ "0": "0x08010843",
+ "1": "0x08010883",
+ "2": "0x080108C3",
+ "3": "0x09010843",
+ "4": "0x09010883",
+ "5": "0x090108C3"
+ }
+ },
+ "PCI_FIR_ACT0": {
+ "instances": {
+ "0": "0x08010846",
+ "1": "0x08010886",
+ "2": "0x080108C6",
+ "3": "0x09010846",
+ "4": "0x09010886",
+ "5": "0x090108C6"
+ }
+ },
+ "PCI_FIR_ACT1": {
+ "instances": {
+ "0": "0x08010847",
+ "1": "0x08010887",
+ "2": "0x080108C7",
+ "3": "0x09010847",
+ "4": "0x09010887",
+ "5": "0x090108C7"
+ }
+ },
+ "PCI_FIR_WOF": {
+ "instances": {
+ "0": "0x08010848",
+ "1": "0x08010888",
+ "2": "0x080108C8",
+ "3": "0x09010848",
+ "4": "0x09010888",
+ "5": "0x090108C8"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "register parity error"
+ },
+ "1": {
+ "desc": "hardware error"
+ },
+ "2": {
+ "desc": "AIB interface error"
+ },
+ "3": {
+ "desc": "ETU reset error"
+ },
+ "4": {
+ "desc": "PEC SCOM error"
+ },
+ "5": {
+ "desc": "spare"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PCI_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pci_iop_fir.json b/chip_data/p10_20/node_pci_iop_fir.json
new file mode 100644
index 0000000..0455296
--- /dev/null
+++ b/chip_data/p10_20/node_pci_iop_fir.json
@@ -0,0 +1,176 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PCI_IOP_FIR": {
+ "instances": {
+ "0": "0x08011100",
+ "1": "0x08011500",
+ "2": "0x09011100",
+ "3": "0x09011500"
+ }
+ },
+ "PCI_IOP_FIR_MASK": {
+ "instances": {
+ "0": "0x08011103",
+ "1": "0x08011503",
+ "2": "0x09011103",
+ "3": "0x09011503"
+ }
+ },
+ "PCI_IOP_FIR_ACT0": {
+ "instances": {
+ "0": "0x08011106",
+ "1": "0x08011506",
+ "2": "0x09011106",
+ "3": "0x09011506"
+ }
+ },
+ "PCI_IOP_FIR_ACT1": {
+ "instances": {
+ "0": "0x08011107",
+ "1": "0x08011507",
+ "2": "0x09011107",
+ "3": "0x09011507"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_IOP_FIR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_IOP_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Correctable error in PH0 arrays"
+ },
+ "1": {
+ "desc": "Uncorrectable error in PH0 arrays"
+ },
+ "2": {
+ "desc": "Correctable error in PH1 arrays"
+ },
+ "3": {
+ "desc": "Uncorrectable error in PH1 arrays"
+ },
+ "4": {
+ "desc": "Correctable error from SCOM in WRAP0"
+ },
+ "5": {
+ "desc": "Uncorrectable error from SCOM in WRAP0"
+ },
+ "6": {
+ "desc": "Correctable error from SCOM in WRAP1"
+ },
+ "7": {
+ "desc": "Uncorrectable error from SCOM in WRAP1"
+ },
+ "8": {
+ "desc": "Correctable error from SCRUB in WRAP0"
+ },
+ "9": {
+ "desc": "Uncorrectable error from SCRUB in WRAP0"
+ },
+ "10": {
+ "desc": "Correctable error from SCRUB in WRAP1"
+ },
+ "11": {
+ "desc": "Uncorrectable error from SCRUB in WRAP1"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pci_local_fir.json b/chip_data/p10_20/node_pci_local_fir.json
new file mode 100644
index 0000000..6ee9a16
--- /dev/null
+++ b/chip_data/p10_20/node_pci_local_fir.json
@@ -0,0 +1,433 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PCI_LOCAL_FIR": {
+ "instances": {
+ "0": "0x08040100",
+ "1": "0x09040100"
+ }
+ },
+ "PCI_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x08040103",
+ "1": "0x09040103"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x08040106",
+ "1": "0x09040106"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x08040107",
+ "1": "0x09040107"
+ }
+ },
+ "PCI_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x08040109",
+ "1": "0x09040109"
+ }
+ },
+ "PCI_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x08040108",
+ "1": "0x09040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_LOCAL_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "Trace01 - scom parity err"
+ },
+ "22": {
+ "desc": "unused"
+ },
+ "23": {
+ "desc": "unused"
+ },
+ "24": {
+ "desc": "unused"
+ },
+ "25": {
+ "desc": "unused"
+ },
+ "26": {
+ "desc": "unused"
+ },
+ "27": {
+ "desc": "unused"
+ },
+ "28": {
+ "desc": "unused"
+ },
+ "29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "unused"
+ },
+ "31": {
+ "desc": "unused"
+ },
+ "32": {
+ "desc": "unused"
+ },
+ "33": {
+ "desc": "unused"
+ },
+ "34": {
+ "desc": "unused"
+ },
+ "35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "unused"
+ },
+ "37": {
+ "desc": "unused"
+ },
+ "38": {
+ "desc": "unused"
+ },
+ "39": {
+ "desc": "unused"
+ },
+ "40": {
+ "desc": "unused"
+ },
+ "41": {
+ "desc": "unused"
+ },
+ "42": {
+ "desc": "unused"
+ },
+ "43": {
+ "desc": "unused"
+ },
+ "44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "unused"
+ },
+ "46": {
+ "desc": "unused"
+ },
+ "47": {
+ "desc": "unused"
+ },
+ "48": {
+ "desc": "unused"
+ },
+ "49": {
+ "desc": "unused"
+ },
+ "50": {
+ "desc": "unused"
+ },
+ "51": {
+ "desc": "unused"
+ },
+ "52": {
+ "desc": "unused"
+ },
+ "53": {
+ "desc": "unused"
+ },
+ "54": {
+ "desc": "unused"
+ },
+ "55": {
+ "desc": "unused"
+ },
+ "56": {
+ "desc": "unused"
+ },
+ "57": {
+ "desc": "unused"
+ },
+ "58": {
+ "desc": "unused"
+ },
+ "59": {
+ "desc": "unused"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_pci_nest_fir.json b/chip_data/p10_20/node_pci_nest_fir.json
new file mode 100644
index 0000000..09bb7db
--- /dev/null
+++ b/chip_data/p10_20/node_pci_nest_fir.json
@@ -0,0 +1,227 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PCI_NEST_FIR": {
+ "instances": {
+ "0": "0x03011840",
+ "1": "0x03011880",
+ "2": "0x030118C0",
+ "3": "0x02011840",
+ "4": "0x02011880",
+ "5": "0x020118C0"
+ }
+ },
+ "PCI_NEST_FIR_MASK": {
+ "instances": {
+ "0": "0x03011843",
+ "1": "0x03011883",
+ "2": "0x030118C3",
+ "3": "0x02011843",
+ "4": "0x02011883",
+ "5": "0x020118C3"
+ }
+ },
+ "PCI_NEST_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011846",
+ "1": "0x03011886",
+ "2": "0x030118C6",
+ "3": "0x02011846",
+ "4": "0x02011886",
+ "5": "0x020118C6"
+ }
+ },
+ "PCI_NEST_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011847",
+ "1": "0x03011887",
+ "2": "0x030118C7",
+ "3": "0x02011847",
+ "4": "0x02011887",
+ "5": "0x020118C7"
+ }
+ },
+ "PCI_NEST_FIR_WOF": {
+ "instances": {
+ "0": "0x03011848",
+ "1": "0x03011888",
+ "2": "0x030118C8",
+ "3": "0x02011848",
+ "4": "0x02011888",
+ "5": "0x020118C8"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PCI_NEST_FIR": {
+ "instances": [0, 1, 2, 3, 4, 5],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3, 4, 5],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PCI_NEST_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "BAR Parity Error"
+ },
+ "1": {
+ "desc": "Non-BAR Parity Error"
+ },
+ "2": {
+ "desc": "Power Bus to PEC CE"
+ },
+ "3": {
+ "desc": "Power Bus to PEC UE"
+ },
+ "4": {
+ "desc": "Power Bus to PEC SUE"
+ },
+ "5": {
+ "desc": "Array CE"
+ },
+ "6": {
+ "desc": "Array UE"
+ },
+ "7": {
+ "desc": "Array SUE"
+ },
+ "8": {
+ "desc": "Register Array Parity Error"
+ },
+ "9": {
+ "desc": "Power Bus Interface Parity Error"
+ },
+ "10": {
+ "desc": "Power Bus Data Hang"
+ },
+ "11": {
+ "desc": "Power Bus Hang Error"
+ },
+ "12": {
+ "desc": "RD ARE Error"
+ },
+ "13": {
+ "desc": "Non-Rd ARE Error"
+ },
+ "14": {
+ "desc": "PCI Hang Error"
+ },
+ "15": {
+ "desc": "PCI Clock Error"
+ },
+ "16": {
+ "desc": "AIB Fence"
+ },
+ "17": {
+ "desc": "Hardware Error"
+ },
+ "18": {
+ "desc": "Unsolicited Power Bus Data"
+ },
+ "19": {
+ "desc": "Unexpected Combined Response"
+ },
+ "20": {
+ "desc": "Invalid Combined Response"
+ },
+ "21": {
+ "desc": "Power Bus Unsupported Size"
+ },
+ "22": {
+ "desc": "Power Bus Unsupported Command"
+ },
+ "23": {
+ "desc": "reserved"
+ },
+ "24": {
+ "desc": "reserved"
+ },
+ "25": {
+ "desc": "reserved"
+ },
+ "26": {
+ "desc": "Software Defined"
+ },
+ "27": {
+ "desc": "PEC SCOM Engine Error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "PCI_NEST_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_psihb_fir.json b/chip_data/p10_20/node_psihb_fir.json
new file mode 100644
index 0000000..70f2a2e
--- /dev/null
+++ b/chip_data/p10_20/node_psihb_fir.json
@@ -0,0 +1,184 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PSIHB_FIR": {
+ "instances": {
+ "0": "0x03011D00"
+ }
+ },
+ "PSIHB_FIR_MASK": {
+ "instances": {
+ "0": "0x03011D03"
+ }
+ },
+ "PSIHB_FIR_ACT0": {
+ "instances": {
+ "0": "0x03011D06"
+ }
+ },
+ "PSIHB_FIR_ACT1": {
+ "instances": {
+ "0": "0x03011D07"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PSIHB_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "PSIHB_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CE from PowerBus data"
+ },
+ "1": {
+ "desc": "UE from PowerBus data"
+ },
+ "2": {
+ "desc": "SUE from PowerBus data"
+ },
+ "3": {
+ "desc": "Interrupt Condition present in PSIHB"
+ },
+ "4": {
+ "desc": "Interrupt from FSP is being processed"
+ },
+ "5": {
+ "desc": "CE from PSILL data"
+ },
+ "6": {
+ "desc": "UE from PSILL data"
+ },
+ "7": {
+ "desc": "Error bit set, ignores the interrupt mask"
+ },
+ "8": {
+ "desc": "Invalid TType Hit on PHB or FSP bar"
+ },
+ "9": {
+ "desc": "Invalid CResp returned to command issued by PSIHB"
+ },
+ "10": {
+ "desc": "PowerBus time out waiting for data grant"
+ },
+ "11": {
+ "desc": "PB parity error"
+ },
+ "12": {
+ "desc": "FSP tried access to trusted space"
+ },
+ "13": {
+ "desc": "Unexpected PB CRESP or DATA"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "reserved"
+ },
+ "21": {
+ "desc": "PSI global error bit 0"
+ },
+ "22": {
+ "desc": "PSI global error bit 1"
+ },
+ "23": {
+ "desc": "Upstream error"
+ },
+ "24": {
+ "desc": "spare"
+ },
+ "25": {
+ "desc": "spare"
+ },
+ "26": {
+ "desc": "spare"
+ },
+ "27": {
+ "desc": "fir parity Error"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_tp_local_fir.json b/chip_data/p10_20/node_tp_local_fir.json
new file mode 100644
index 0000000..1d35875
--- /dev/null
+++ b/chip_data/p10_20/node_tp_local_fir.json
@@ -0,0 +1,447 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "TP_LOCAL_FIR": {
+ "instances": {
+ "0": "0x01040100"
+ }
+ },
+ "TP_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x01040103"
+ }
+ },
+ "TP_LOCAL_FIR_ACT0": {
+ "instances": {
+ "0": "0x01040106"
+ }
+ },
+ "TP_LOCAL_FIR_ACT1": {
+ "instances": {
+ "0": "0x01040107"
+ }
+ },
+ "TP_LOCAL_FIR_ACT2": {
+ "instances": {
+ "0": "0x01040109"
+ }
+ },
+ "TP_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x01040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TP_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT1"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_ACT2"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR - Parity or PCB access error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - Clock Control Error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM access error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - internal error"
+ },
+ "7": {
+ "desc": "THERM - pcb error"
+ },
+ "8": {
+ "desc": "THERMTRIP - Critical temperature indicator"
+ },
+ "9": {
+ "desc": "THERMTRIP - Fatal temperature indicator"
+ },
+ "10": {
+ "desc": "VOLTTRIP - Voltage sense error"
+ },
+ "11": {
+ "desc": "DBG - scom parity fail"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "reserved"
+ },
+ "14": {
+ "desc": "reserved"
+ },
+ "15": {
+ "desc": "reserved"
+ },
+ "16": {
+ "desc": "reserved"
+ },
+ "17": {
+ "desc": "reserved"
+ },
+ "18": {
+ "desc": "reserved"
+ },
+ "19": {
+ "desc": "reserved"
+ },
+ "20": {
+ "desc": "Trace00 - scom parity err"
+ },
+ "21": {
+ "desc": "ITR - FMU error"
+ },
+ "22": {
+ "desc": "ITR - PCB error"
+ },
+ "23": {
+ "desc": "PCB Master - timeout"
+ },
+ "24": {
+ "desc": "I2CM - Parity errors"
+ },
+ "25": {
+ "desc": "TOD - any error",
+ "child_node": {
+ "name": "TOD_ERROR"
+ }
+ },
+ "26": {
+ "desc": "TOD - access error PIB"
+ },
+ "27": {
+ "desc": "TOD - Error reported from PHYP"
+ },
+ "28": {
+ "desc": "PCB slave error",
+ "child_node": {
+ "name": "PLL_UNLOCK"
+ }
+ },
+ "29": {
+ "desc": "SBE - PPE int hardware error"
+ },
+ "30": {
+ "desc": "SBE - PPE ext hardware error"
+ },
+ "31": {
+ "desc": "SBE - PPE code error"
+ },
+ "32": {
+ "desc": "SBE - PPE debug code breakpoint"
+ },
+ "33": {
+ "desc": "SBE - PPE in halted state"
+ },
+ "34": {
+ "desc": "SBE - PPE watchdog timeout"
+ },
+ "35": {
+ "desc": "SBE - unused"
+ },
+ "36": {
+ "desc": "SBE - unused"
+ },
+ "37": {
+ "desc": "SBE - PPE triggers DBG"
+ },
+ "38": {
+ "desc": "OTP - SCOM access errors and single ecc correctable"
+ },
+ "39": {
+ "desc": "TPIO External Trigger"
+ },
+ "40": {
+ "desc": "PCB Master - Multicast group member count underrun (MC misconfig)"
+ },
+ "41": {
+ "desc": "PCB Master - Parity ERR"
+ },
+ "42": {
+ "desc": "RCS OSC error on clk A"
+ },
+ "43": {
+ "desc": "RCS OSC error on clk B"
+ },
+ "44": {
+ "desc": "RCS - Up/down counter A unlock"
+ },
+ "45": {
+ "desc": "RCS - Up/down counter B unlock"
+ },
+ "46": {
+ "desc": "PIBMEM"
+ },
+ "47": {
+ "desc": "PIBMEM"
+ },
+ "48": {
+ "desc": "OTP - ECC UE or CE count overflow"
+ },
+ "49": {
+ "desc": "Nest DPLL: DCO empty"
+ },
+ "50": {
+ "desc": "Nest DPLL: DCO full"
+ },
+ "51": {
+ "desc": "Nest DPLL: internal error"
+ },
+ "52": {
+ "desc": "PAU DPLL: DCO empty"
+ },
+ "53": {
+ "desc": "PAU DPLL: DCO full"
+ },
+ "54": {
+ "desc": "PAU DPLL: internal error"
+ },
+ "55": {
+ "desc": "SPI Master 0 Err"
+ },
+ "56": {
+ "desc": "SPI Master 1 Err"
+ },
+ "57": {
+ "desc": "SPI Master 2 Err"
+ },
+ "58": {
+ "desc": "SPI Master 3 Err"
+ },
+ "59": {
+ "desc": "SPI Master 4 Err"
+ },
+ "60": {
+ "desc": "unused"
+ },
+ "61": {
+ "desc": "unused"
+ },
+ "62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "ext_local_xstop"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "TOD_ERROR",
+ "group_inst": {
+ "0": 0
+ }
+ },
+ {
+ "group_name": "RCS_PLL",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ }
+}
diff --git a/chip_data/p10_20/node_vas_fir.json b/chip_data/p10_20/node_vas_fir.json
new file mode 100644
index 0000000..d4b03a2
--- /dev/null
+++ b/chip_data/p10_20/node_vas_fir.json
@@ -0,0 +1,289 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "VAS_FIR": {
+ "instances": {
+ "0": "0x02011400"
+ }
+ },
+ "VAS_FIR_MASK": {
+ "instances": {
+ "0": "0x02011403"
+ }
+ },
+ "VAS_FIR_ACT0": {
+ "instances": {
+ "0": "0x02011406"
+ }
+ },
+ "VAS_FIR_ACT1": {
+ "instances": {
+ "0": "0x02011407"
+ }
+ },
+ "VAS_FIR_WOF": {
+ "instances": {
+ "0": "0x02011408"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "VAS_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT0"
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "VAS_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Hardware error detected in Egress logic"
+ },
+ "1": {
+ "desc": "Hardware error detected in Ingress logic"
+ },
+ "2": {
+ "desc": "Hardware error detected in CQ logic"
+ },
+ "3": {
+ "desc": "Hardware error detected in WC logic"
+ },
+ "4": {
+ "desc": "Hardware error detected in RG logic"
+ },
+ "5": {
+ "desc": "PowerBus parity error detected on CQ logic interface"
+ },
+ "6": {
+ "desc": "CQ logic detected PowerBus address error on CRESP from a read operation"
+ },
+ "7": {
+ "desc": "CQ logic detected PowerBus address error on CRESP from a write operation"
+ },
+ "8": {
+ "desc": "Correctable ECC error detected in Egress logic"
+ },
+ "9": {
+ "desc": "Correctable ECC error detected in Ingress logic"
+ },
+ "10": {
+ "desc": "Correctable ECC error detected in CQ logic"
+ },
+ "11": {
+ "desc": "Correctable ECC error detected in WC logic"
+ },
+ "12": {
+ "desc": "Correctable ECC error detected in RG logic"
+ },
+ "13": {
+ "desc": "ECC Correctable Error detected on CQ outbound PowerBus interface"
+ },
+ "14": {
+ "desc": "ECC Uncorrectable Error detected on CQ outbound PowerBus interface"
+ },
+ "15": {
+ "desc": "PowerBus state machine hang detected in CQ logic"
+ },
+ "16": {
+ "desc": "Uncorrectable ECC error detected in Egress logic"
+ },
+ "17": {
+ "desc": "Uncorrectable ECC error detected in Ingress logic"
+ },
+ "18": {
+ "desc": "Uncorrectable ECC error detected in CQ logic"
+ },
+ "19": {
+ "desc": "Uncorrectable ECC error detected in WC logic"
+ },
+ "20": {
+ "desc": "Uncorrectable ECC error detected in RG logic"
+ },
+ "21": {
+ "desc": "Parity error detected in Ingress logic"
+ },
+ "22": {
+ "desc": "Software cast error detected in Ingress logic"
+ },
+ "23": {
+ "desc": "reserved"
+ },
+ "24": {
+ "desc": "ECC sue error detected in Egress logic"
+ },
+ "25": {
+ "desc": "ECC sue error detected in Ingress logic"
+ },
+ "26": {
+ "desc": "ECC sue error detected in CQ logic"
+ },
+ "27": {
+ "desc": "ECC sue error detected in WC logic"
+ },
+ "28": {
+ "desc": "ECC sue error detected in RG logic"
+ },
+ "29": {
+ "desc": "PowerBus link error detected on read operation in CQ logic"
+ },
+ "30": {
+ "desc": "PowerBus link error detected on write operation in CQ logic"
+ },
+ "31": {
+ "desc": "PowerBus link abort operation received in CQ logic"
+ },
+ "32": {
+ "desc": "Address error detected on hypervisor MMIO read"
+ },
+ "33": {
+ "desc": "Address error detected on OS MMIO read"
+ },
+ "34": {
+ "desc": "Address error detected on hypervisor MMIO write"
+ },
+ "35": {
+ "desc": "Address error detected on OS MMIO write"
+ },
+ "36": {
+ "desc": "non-8-Byte MMIO detected by hypervisor"
+ },
+ "37": {
+ "desc": "non-8-Byte MMIO detected by user or OS"
+ },
+ "38": {
+ "desc": "reserved"
+ },
+ "39": {
+ "desc": "reserved"
+ },
+ "40": {
+ "desc": "reserved"
+ },
+ "41": {
+ "desc": "reserved"
+ },
+ "42": {
+ "desc": "ASB_Notify sent but not claimed and interrupts were disabled in window context"
+ },
+ "43": {
+ "desc": "reserved"
+ },
+ "44": {
+ "desc": "VAS rejected a PB paste command"
+ },
+ "45": {
+ "desc": "VAS hung waiting for data from PowerBus"
+ },
+ "46": {
+ "desc": "Incoming PowerBus parity error"
+ },
+ "47": {
+ "desc": "HW error from SCOM Satellite 1"
+ },
+ "48": {
+ "desc": "NX Local Checkstop"
+ },
+ "49": {
+ "desc": "SCOM MMIO address offset error"
+ },
+ "50": {
+ "desc": "TopoID Error Bit"
+ },
+ "51": {
+ "desc": "spare"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/pau_pb0123_pr_err.json b/chip_data/p10_20/pau_pb0123_pr_err.json
new file mode 100644
index 0000000..e0a07ff
--- /dev/null
+++ b/chip_data/p10_20/pau_pb0123_pr_err.json
@@ -0,0 +1,215 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_PR0123_ERR": {
+ "instances": {
+ "0": "0x10011829",
+ "1": "0x11011829",
+ "2": "0x12011829",
+ "3": "0x13011829"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_PR0123_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_PR0123_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "prs0_address_pty"
+ },
+ "1": {
+ "desc": "prs0_atag_pty"
+ },
+ "2": {
+ "desc": "prs0_cc0_crediterr"
+ },
+ "3": {
+ "desc": "prs0_cc1_crediterr"
+ },
+ "4": {
+ "desc": "prs0_cc2_crediterr"
+ },
+ "5": {
+ "desc": "prs0_cc3_crediterr"
+ },
+ "6": {
+ "desc": "prs0_control_error"
+ },
+ "7": {
+ "desc": "prs0_data_pty_err"
+ },
+ "8": {
+ "desc": "prs0_rtag_misc_pty"
+ },
+ "9": {
+ "desc": "prs0_rtag_pty"
+ },
+ "10": {
+ "desc": "prs0_ttag_pty"
+ },
+ "11": {
+ "desc": "prs0_vc0_crediterr"
+ },
+ "12": {
+ "desc": "prs0_vc1_crediterr"
+ },
+ "13": {
+ "desc": "prs0_link_down"
+ },
+ "16": {
+ "desc": "prs1_address_pty"
+ },
+ "17": {
+ "desc": "prs1_atag_pty"
+ },
+ "18": {
+ "desc": "prs1_cc0_crediterr"
+ },
+ "19": {
+ "desc": "prs1_cc1_crediterr"
+ },
+ "20": {
+ "desc": "prs1_cc2_crediterr"
+ },
+ "21": {
+ "desc": "prs1_cc3_crediterr"
+ },
+ "22": {
+ "desc": "prs1_control_error"
+ },
+ "23": {
+ "desc": "prs1_data_pty_err"
+ },
+ "24": {
+ "desc": "prs1_rtag_misc_pty"
+ },
+ "25": {
+ "desc": "prs1_rtag_pty"
+ },
+ "26": {
+ "desc": "prs1_ttag_pty"
+ },
+ "27": {
+ "desc": "prs1_vc0_crediterr"
+ },
+ "28": {
+ "desc": "prs1_vc1_crediterr"
+ },
+ "29": {
+ "desc": "prs1_link_down"
+ },
+ "32": {
+ "desc": "prs2_address_pty"
+ },
+ "33": {
+ "desc": "prs2_atag_pty"
+ },
+ "34": {
+ "desc": "prs2_cc0_crediterr"
+ },
+ "35": {
+ "desc": "prs2_cc1_crediterr"
+ },
+ "36": {
+ "desc": "prs2_cc2_crediterr"
+ },
+ "37": {
+ "desc": "prs2_cc3_crediterr"
+ },
+ "38": {
+ "desc": "prs2_control_error"
+ },
+ "39": {
+ "desc": "prs2_data_pty_err"
+ },
+ "40": {
+ "desc": "prs2_rtag_misc_pty"
+ },
+ "41": {
+ "desc": "prs2_rtag_pty"
+ },
+ "42": {
+ "desc": "prs2_ttag_pty"
+ },
+ "43": {
+ "desc": "prs2_vc0_crediterr"
+ },
+ "44": {
+ "desc": "prs2_vc1_crediterr"
+ },
+ "45": {
+ "desc": "prs2_link_down"
+ },
+ "48": {
+ "desc": "prs3_address_pty"
+ },
+ "49": {
+ "desc": "prs3_atag_pty"
+ },
+ "50": {
+ "desc": "prs3_cc0_crediterr"
+ },
+ "51": {
+ "desc": "prs3_cc1_crediterr"
+ },
+ "52": {
+ "desc": "prs3_cc2_crediterr"
+ },
+ "53": {
+ "desc": "prs3_cc3_crediterr"
+ },
+ "54": {
+ "desc": "prs3_control_error"
+ },
+ "55": {
+ "desc": "prs3_data_pty_err"
+ },
+ "56": {
+ "desc": "prs3_rtag_misc_pty"
+ },
+ "57": {
+ "desc": "prs3_rtag_pty"
+ },
+ "58": {
+ "desc": "prs3_ttag_pty"
+ },
+ "59": {
+ "desc": "prs3_vc0_crediterr"
+ },
+ "60": {
+ "desc": "prs3_vc1_crediterr"
+ },
+ "61": {
+ "desc": "prs3_link_down"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/pau_pb_dob01_dib01_int_err.json b/chip_data/p10_20/pau_pb_dob01_dib01_int_err.json
new file mode 100644
index 0000000..215e451
--- /dev/null
+++ b/chip_data/p10_20/pau_pb_dob01_dib01_int_err.json
@@ -0,0 +1,203 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_DOB01_DIB01_INT_ERR": {
+ "instances": {
+ "0": "0x10011828",
+ "1": "0x11011828",
+ "2": "0x12011828",
+ "3": "0x13011828"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_DOB01_DIB01_INT_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB01_DIB01_INT_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "dob01_rtag_pbiterr"
+ },
+ "1": {
+ "desc": "dob01_rtag_perr"
+ },
+ "2": {
+ "desc": "dob01_misc_perr"
+ },
+ "3": {
+ "desc": "dob01_f0vc0_evenperr"
+ },
+ "4": {
+ "desc": "dob01_f0vc0_oddperr"
+ },
+ "5": {
+ "desc": "dob01_f0vc1_evenperr"
+ },
+ "6": {
+ "desc": "dob01_f0vc1_oddperr"
+ },
+ "7": {
+ "desc": "dob01_f1vc0_evenperr"
+ },
+ "8": {
+ "desc": "dob01_f1vc0_oddperr"
+ },
+ "9": {
+ "desc": "dob01_f1vc1_evenperr"
+ },
+ "10": {
+ "desc": "dob01_f1vc1_oddperr"
+ },
+ "11": {
+ "desc": "dob01_f0_underflow"
+ },
+ "12": {
+ "desc": "dob01_f0_overflow"
+ },
+ "13": {
+ "desc": "dob01_f1_underflow"
+ },
+ "14": {
+ "desc": "dob01_f1_overflow"
+ },
+ "15": {
+ "desc": "dob01_vc0_underflow"
+ },
+ "16": {
+ "desc": "dob01_vc0_overflow"
+ },
+ "17": {
+ "desc": "dob01_vc1_underflow"
+ },
+ "18": {
+ "desc": "dob01_vc1_overflow"
+ },
+ "19": {
+ "desc": "dob01_f0vc0_underflow"
+ },
+ "20": {
+ "desc": "dob01_f0vc0_overflow"
+ },
+ "21": {
+ "desc": "dob01_f0vc1_underflow"
+ },
+ "22": {
+ "desc": "dob01_f0vc1_overflow"
+ },
+ "23": {
+ "desc": "dob01_f1vc0_underflow"
+ },
+ "24": {
+ "desc": "dob01_f1vc0_overflow"
+ },
+ "25": {
+ "desc": "dob01_f1vc1_underflow"
+ },
+ "26": {
+ "desc": "dob01_f1vc1_overflow"
+ },
+ "27": {
+ "desc": "dob01_vc0_prefetch_overflow"
+ },
+ "28": {
+ "desc": "dob01_vc1_prefetch_overflow"
+ },
+ "29": {
+ "desc": "dib01_evn0_underflow"
+ },
+ "30": {
+ "desc": "dib01_evn0_overflow"
+ },
+ "31": {
+ "desc": "dib01_evn1_underflow"
+ },
+ "32": {
+ "desc": "dib01_evn1_overflow"
+ },
+ "33": {
+ "desc": "dib01_rtag_pbiterr"
+ },
+ "34": {
+ "desc": "dib01_rtag_perr"
+ },
+ "35": {
+ "desc": "dib01_misc_perr"
+ },
+ "36": {
+ "desc": "dib01_odd0_underflow"
+ },
+ "37": {
+ "desc": "dib01_odd0_overflow"
+ },
+ "38": {
+ "desc": "dib01_odd1_underflow"
+ },
+ "39": {
+ "desc": "dib01_odd1_overflow"
+ },
+ "40": {
+ "desc": "dib01_rtag_underflow"
+ },
+ "41": {
+ "desc": "dib01_rtag_overflow"
+ },
+ "42": {
+ "desc": "dib01_data_underflow"
+ },
+ "43": {
+ "desc": "dib01_data_overflow"
+ },
+ "44": {
+ "desc": "dib01_vc0_underflow"
+ },
+ "45": {
+ "desc": "dib01_vc0_overflow"
+ },
+ "46": {
+ "desc": "dib01_vc1_underflow"
+ },
+ "47": {
+ "desc": "dib01_vc1_overflow"
+ },
+ "48": {
+ "desc": "dib01_f0vc0_over_underflow"
+ },
+ "49": {
+ "desc": "dib01_f0vc1_over_underflow"
+ },
+ "50": {
+ "desc": "dib01_f1vc0_over_underflow"
+ },
+ "51": {
+ "desc": "dib01_f1vc1_over_underflow"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/pau_pb_dob23_dib23_int_err.json b/chip_data/p10_20/pau_pb_dob23_dib23_int_err.json
new file mode 100644
index 0000000..81bf3a2
--- /dev/null
+++ b/chip_data/p10_20/pau_pb_dob23_dib23_int_err.json
@@ -0,0 +1,203 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_DOB23_DIB23_INT_ERR": {
+ "instances": {
+ "0": "0x1001182A",
+ "1": "0x1101182A",
+ "2": "0x1201182A",
+ "3": "0x1301182A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_DOB23_DIB23_INT_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_DOB23_DIB23_INT_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "dob23_rtag_pbiterr"
+ },
+ "1": {
+ "desc": "dob23_rtag_perr"
+ },
+ "2": {
+ "desc": "dob23_misc_perr"
+ },
+ "3": {
+ "desc": "dob23_f0vc0_evenperr"
+ },
+ "4": {
+ "desc": "dob23_f0vc0_oddperr"
+ },
+ "5": {
+ "desc": "dob23_f0vc1_evenperr"
+ },
+ "6": {
+ "desc": "dob23_f0vc1_oddperr"
+ },
+ "7": {
+ "desc": "dob23_f1vc0_evenperr"
+ },
+ "8": {
+ "desc": "dob23_f1vc0_oddperr"
+ },
+ "9": {
+ "desc": "dob23_f1vc1_evenperr"
+ },
+ "10": {
+ "desc": "dob23_f1vc1_oddperr"
+ },
+ "11": {
+ "desc": "dob23_f0_underflow"
+ },
+ "12": {
+ "desc": "dob23_f0_overflow"
+ },
+ "13": {
+ "desc": "dob23_f1_underflow"
+ },
+ "14": {
+ "desc": "dob23_f1_overflow"
+ },
+ "15": {
+ "desc": "dob23_vc0_underflow"
+ },
+ "16": {
+ "desc": "dob23_vc0_overflow"
+ },
+ "17": {
+ "desc": "dob23_vc1_underflow"
+ },
+ "18": {
+ "desc": "dob23_vc1_overflow"
+ },
+ "19": {
+ "desc": "dob23_f0vc0_underflow"
+ },
+ "20": {
+ "desc": "dob23_f0vc0_overflow"
+ },
+ "21": {
+ "desc": "dob23_f0vc1_underflow"
+ },
+ "22": {
+ "desc": "dob23_f0vc1_overflow"
+ },
+ "23": {
+ "desc": "dob23_f1vc0_underflow"
+ },
+ "24": {
+ "desc": "dob23_f1vc0_overflow"
+ },
+ "25": {
+ "desc": "dob23_f1vc1_underflow"
+ },
+ "26": {
+ "desc": "dob23_f1vc1_overflow"
+ },
+ "27": {
+ "desc": "dob23_vc0_prefetch_overflow"
+ },
+ "28": {
+ "desc": "dob23_vc1_prefetch_overflow"
+ },
+ "29": {
+ "desc": "dib23_evn0_underflow"
+ },
+ "30": {
+ "desc": "dib23_evn0_overflow"
+ },
+ "31": {
+ "desc": "dib23_evn1_underflow"
+ },
+ "32": {
+ "desc": "dib23_evn1_overflow"
+ },
+ "33": {
+ "desc": "dib23_rtag_pbiterr"
+ },
+ "34": {
+ "desc": "dib23_rtag_perr"
+ },
+ "35": {
+ "desc": "dib23_misc_perr"
+ },
+ "36": {
+ "desc": "dib23_odd0_underflow"
+ },
+ "37": {
+ "desc": "dib23_odd0_overflow"
+ },
+ "38": {
+ "desc": "dib23_odd1_underflow"
+ },
+ "39": {
+ "desc": "dib23_odd1_overflow"
+ },
+ "40": {
+ "desc": "dib23_rtag_underflow"
+ },
+ "41": {
+ "desc": "dib23_rtag_overflow"
+ },
+ "42": {
+ "desc": "dib23_data_underflow"
+ },
+ "43": {
+ "desc": "dib23_data_overflow"
+ },
+ "44": {
+ "desc": "dib23_vc0_underflow"
+ },
+ "45": {
+ "desc": "dib23_vc0_overflow"
+ },
+ "46": {
+ "desc": "dib23_vc1_underflow"
+ },
+ "47": {
+ "desc": "dib23_vc1_overflow"
+ },
+ "48": {
+ "desc": "dib23_f0vc0_over_underflow"
+ },
+ "49": {
+ "desc": "dib23_f0vc1_over_underflow"
+ },
+ "50": {
+ "desc": "dib23_f1vc0_over_underflow"
+ },
+ "51": {
+ "desc": "dib23_f1vc1_over_underflow"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/pau_pb_fm0123_err.json b/chip_data/p10_20/pau_pb_fm0123_err.json
new file mode 100644
index 0000000..5e9cdad
--- /dev/null
+++ b/chip_data/p10_20/pau_pb_fm0123_err.json
@@ -0,0 +1,239 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "PB_FM0123_ERR": {
+ "instances": {
+ "0": "0x10011827",
+ "1": "0x11011827",
+ "2": "0x12011827",
+ "3": "0x13011827"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PB_FM0123_ERR": {
+ "instances": [0, 1, 2, 3],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1, 2, 3],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "PB_FM0123_ERR"
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "fmr0_control_error"
+ },
+ "1": {
+ "desc": "fmr0_addr_perr"
+ },
+ "2": {
+ "desc": "fmr0_cc0_crediterr"
+ },
+ "3": {
+ "desc": "fmr0_cc1_crediterr"
+ },
+ "4": {
+ "desc": "fmr0_cc2_crediterr"
+ },
+ "5": {
+ "desc": "fmr0_cc3_crediterr"
+ },
+ "6": {
+ "desc": "fmr0_dat_hi_perr"
+ },
+ "7": {
+ "desc": "fmr0_dat_lo_perr"
+ },
+ "8": {
+ "desc": "fmr0_frame_crediterr"
+ },
+ "9": {
+ "desc": "fmr0_internal_err"
+ },
+ "10": {
+ "desc": "fmr0_prsp_ptyerr"
+ },
+ "11": {
+ "desc": "fmr0_ttag_perr"
+ },
+ "12": {
+ "desc": "fmr0_vc0_crediterr"
+ },
+ "13": {
+ "desc": "fmr0_vc1_crediterr"
+ },
+ "14": {
+ "desc": "fmr0_rtag_ptyerr"
+ },
+ "15": {
+ "desc": "fmr0_rtag_misc_pty"
+ },
+ "16": {
+ "desc": "fmr1_control_error"
+ },
+ "17": {
+ "desc": "fmr1_addr_perr"
+ },
+ "18": {
+ "desc": "fmr1_cc0_crediterr"
+ },
+ "19": {
+ "desc": "fmr1_cc1_crediterr"
+ },
+ "20": {
+ "desc": "fmr1_cc2_crediterr"
+ },
+ "21": {
+ "desc": "fmr1_cc3_crediterr"
+ },
+ "22": {
+ "desc": "fmr1_dat_hi_perr"
+ },
+ "23": {
+ "desc": "fmr1_dat_lo_perr"
+ },
+ "24": {
+ "desc": "fmr1_frame_crediterr"
+ },
+ "25": {
+ "desc": "fmr1_internal_err"
+ },
+ "26": {
+ "desc": "fmr1_prsp_ptyerr"
+ },
+ "27": {
+ "desc": "fmr1_ttag_perr"
+ },
+ "28": {
+ "desc": "fmr1_vc0_crediterr"
+ },
+ "29": {
+ "desc": "fmr1_vc1_crediterr"
+ },
+ "30": {
+ "desc": "fmr1_rtag_ptyerr"
+ },
+ "31": {
+ "desc": "fmr1_rtag_misc_pty"
+ },
+ "32": {
+ "desc": "fmr2_control_error"
+ },
+ "33": {
+ "desc": "fmr2_addr_perr"
+ },
+ "34": {
+ "desc": "fmr2_cc0_crediterr"
+ },
+ "35": {
+ "desc": "fmr2_cc1_crediterr"
+ },
+ "36": {
+ "desc": "fmr2_cc2_crediterr"
+ },
+ "37": {
+ "desc": "fmr2_cc3_crediterr"
+ },
+ "38": {
+ "desc": "fmr2_dat_hi_perr"
+ },
+ "39": {
+ "desc": "fmr2_dat_lo_perr"
+ },
+ "40": {
+ "desc": "fmr2_frame_crediterr"
+ },
+ "41": {
+ "desc": "fmr2_internal_err"
+ },
+ "42": {
+ "desc": "fmr2_prsp_ptyerr"
+ },
+ "43": {
+ "desc": "fmr2_ttag_perr"
+ },
+ "44": {
+ "desc": "fmr2_vc0_crediterr"
+ },
+ "45": {
+ "desc": "fmr2_vc1_crediterr"
+ },
+ "46": {
+ "desc": "fmr2_rtag_ptyerr"
+ },
+ "47": {
+ "desc": "fmr2_rtag_misc_pty"
+ },
+ "48": {
+ "desc": "fmr3_control_error"
+ },
+ "49": {
+ "desc": "fmr3_addr_perr"
+ },
+ "50": {
+ "desc": "fmr3_cc0_crediterr"
+ },
+ "51": {
+ "desc": "fmr3_cc1_crediterr"
+ },
+ "52": {
+ "desc": "fmr3_cc2_crediterr"
+ },
+ "53": {
+ "desc": "fmr3_cc3_crediterr"
+ },
+ "54": {
+ "desc": "fmr3_dat_hi_perr"
+ },
+ "55": {
+ "desc": "fmr3_dat_lo_perr"
+ },
+ "56": {
+ "desc": "fmr3_frame_crediterr"
+ },
+ "57": {
+ "desc": "fmr3_internal_err"
+ },
+ "58": {
+ "desc": "fmr3_prsp_ptyerr"
+ },
+ "59": {
+ "desc": "fmr3_ttag_perr"
+ },
+ "60": {
+ "desc": "fmr3_vc0_crediterr"
+ },
+ "61": {
+ "desc": "fmr3_vc1_crediterr"
+ },
+ "62": {
+ "desc": "fmr3_rtag_ptyerr"
+ },
+ "63": {
+ "desc": "fmr3_rtag_misc_pty"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/p10_20/rcs_pll.json b/chip_data/p10_20/rcs_pll.json
new file mode 100644
index 0000000..07b40b9
--- /dev/null
+++ b/chip_data/p10_20/rcs_pll.json
@@ -0,0 +1,1452 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "ROOT_CTRL0": {
+ "instances": {
+ "0": "0x00050010"
+ }
+ },
+ "ROOT_CTRL3": {
+ "instances": {
+ "0": "0x00050013"
+ }
+ },
+ "ROOT_CTRL4": {
+ "instances": {
+ "0": "0x00050014"
+ }
+ },
+ "ROOT_CTRL5": {
+ "instances": {
+ "0": "0x00050015"
+ }
+ },
+ "ROOT_CTRL6": {
+ "instances": {
+ "0": "0x00050016"
+ }
+ },
+ "RCS_SENSE_1": {
+ "instances": {
+ "0": "0x0005001D"
+ }
+ },
+ "RCS_SENSE_2": {
+ "instances": {
+ "0": "0x0005001E"
+ }
+ },
+ "BC_OR_PCBSLV_ERROR": {
+ "instances": {
+ "0": "0x470F001F"
+ }
+ },
+ "PCBSLV_CONFIG": {
+ "instances": {
+ "1": "0x010F001E",
+ "2": "0x020F001E",
+ "3": "0x030F001E",
+ "8": "0x080F001E",
+ "9": "0x090F001E",
+ "12": "0x0C0F001E",
+ "13": "0x0D0F001E",
+ "14": "0x0E0F001E",
+ "15": "0x0F0F001E",
+ "16": "0x100F001E",
+ "17": "0x110F001E",
+ "18": "0x120F001E",
+ "19": "0x130F001E",
+ "24": "0x180F001E",
+ "25": "0x190F001E",
+ "26": "0x1A0F001E",
+ "27": "0x1B0F001E",
+ "28": "0x1C0F001E",
+ "29": "0x1D0F001E",
+ "30": "0x1E0F001E",
+ "31": "0x1F0F001E",
+ "32": "0x200F001E",
+ "33": "0x210F001E",
+ "34": "0x220F001E",
+ "35": "0x230F001E",
+ "36": "0x240F001E",
+ "37": "0x250F001E",
+ "38": "0x260F001E",
+ "39": "0x270F001E"
+ }
+ },
+ "PCBSLV_ERROR": {
+ "instances": {
+ "1": "0x010F001F",
+ "2": "0x020F001F",
+ "3": "0x030F001F",
+ "8": "0x080F001F",
+ "9": "0x090F001F",
+ "12": "0x0C0F001F",
+ "13": "0x0D0F001F",
+ "14": "0x0E0F001F",
+ "15": "0x0F0F001F",
+ "16": "0x100F001F",
+ "17": "0x110F001F",
+ "18": "0x120F001F",
+ "19": "0x130F001F",
+ "24": "0x180F001F",
+ "25": "0x190F001F",
+ "26": "0x1A0F001F",
+ "27": "0x1B0F001F",
+ "28": "0x1C0F001F",
+ "29": "0x1D0F001F",
+ "30": "0x1E0F001F",
+ "31": "0x1F0F001F",
+ "32": "0x200F001F",
+ "33": "0x210F001F",
+ "34": "0x220F001F",
+ "35": "0x230F001F",
+ "36": "0x240F001F",
+ "37": "0x250F001F",
+ "38": "0x260F001F",
+ "39": "0x270F001F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "PLL_UNLOCK": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 12
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 13
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ "shift_value": 1
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 12
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 13
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ "shift_value": 1
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 12
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 13
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ "shift_value": 1
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 12
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 13
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ "shift_value": 1
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 12
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ {
+ "expr_type": "rshift",
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RCS_SENSE_1"
+ },
+ "shift_value": 13
+ },
+ {
+ "expr_type": "or",
+ "exprs": [
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 24
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 25
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 26
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 27
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 28
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 29
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 30
+ },
+ {
+ "expr_type": "lshift",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "BC_OR_PCBSLV_ERROR"
+ },
+ "shift_value": 31
+ }
+ ]
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x8000000000000000"
+ }
+ ]
+ },
+ "shift_value": 1
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "PLL unlock on clk A"
+ },
+ "1": {
+ "desc": "PLL unlock on clk B"
+ }
+ }
+ }
+ },
+ "capture_groups": {
+ "RCS_PLL": [
+ {
+ "reg_name": "ROOT_CTRL0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ROOT_CTRL3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ROOT_CTRL4",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ROOT_CTRL5",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "ROOT_CTRL6",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RCS_SENSE_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "RCS_SENSE_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 8
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 9
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 12
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 13
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 14
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 15
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 16
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 17
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 18
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 19
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 24
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 25
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 26
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 27
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 28
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 29
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 30
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 31
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 32
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 33
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 34
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 35
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 36
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 37
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 38
+ }
+ },
+ {
+ "reg_name": "PCBSLV_CONFIG",
+ "reg_inst": {
+ "0": 39
+ }
+ },
+ {
+ "reg_name": "BC_OR_PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 1
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 2
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 3
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 8
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 9
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 12
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 13
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 14
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 15
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 16
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 17
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 18
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 19
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 24
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 25
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 26
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 27
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 28
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 29
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 30
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 31
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 32
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 33
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 34
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 35
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 36
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 37
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 38
+ }
+ },
+ {
+ "reg_name": "PCBSLV_ERROR",
+ "reg_inst": {
+ "0": 39
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/regs_eq.json b/chip_data/p10_20/regs_eq.json
new file mode 100644
index 0000000..b273d76
--- /dev/null
+++ b/chip_data/p10_20/regs_eq.json
@@ -0,0 +1,2790 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "HV_PR_STATE": {
+ "instances": {
+ "0": "0x2002840D",
+ "1": "0x2002440D",
+ "2": "0x2002240D",
+ "3": "0x2002140D",
+ "4": "0x2102840D",
+ "5": "0x2102440D",
+ "6": "0x2102240D",
+ "7": "0x2102140D",
+ "8": "0x2202840D",
+ "9": "0x2202440D",
+ "10": "0x2202240D",
+ "11": "0x2202140D",
+ "12": "0x2302840D",
+ "13": "0x2302440D",
+ "14": "0x2302240D",
+ "15": "0x2302140D",
+ "16": "0x2402840D",
+ "17": "0x2402440D",
+ "18": "0x2402240D",
+ "19": "0x2402140D",
+ "20": "0x2502840D",
+ "21": "0x2502440D",
+ "22": "0x2502240D",
+ "23": "0x2502140D",
+ "24": "0x2602840D",
+ "25": "0x2602440D",
+ "26": "0x2602240D",
+ "27": "0x2602140D",
+ "28": "0x2702840D",
+ "29": "0x2702440D",
+ "30": "0x2702240D",
+ "31": "0x2702140D"
+ }
+ },
+ "PC_FIR_HOLD_OUT": {
+ "instances": {
+ "0": "0x20028451",
+ "1": "0x20024451",
+ "2": "0x20022451",
+ "3": "0x20021451",
+ "4": "0x21028451",
+ "5": "0x21024451",
+ "6": "0x21022451",
+ "7": "0x21021451",
+ "8": "0x22028451",
+ "9": "0x22024451",
+ "10": "0x22022451",
+ "11": "0x22021451",
+ "12": "0x23028451",
+ "13": "0x23024451",
+ "14": "0x23022451",
+ "15": "0x23021451",
+ "16": "0x24028451",
+ "17": "0x24024451",
+ "18": "0x24022451",
+ "19": "0x24021451",
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+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG7",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG8",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG9",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG10",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG11",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG12",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "LSU_HOLD_OUT_REG13",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_L2_FIR": [
+ {
+ "reg_name": "L2_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "L2_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_L3_FIR": [
+ {
+ "reg_name": "L3_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ },
+ {
+ "reg_name": "L3_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ],
+ "EQ_NCU_FIR": [
+ {
+ "reg_name": "NCU_ERR_RPT_REG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/regs_mc.json b/chip_data/p10_20/regs_mc.json
new file mode 100644
index 0000000..fdba2ea
--- /dev/null
+++ b/chip_data/p10_20/regs_mc.json
@@ -0,0 +1,883 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "MC_OMI_DL_CONFIG0": {
+ "instances": {
+ "0": "0x0C011410",
+ "1": "0x0C011420",
+ "2": "0x0C011810",
+ "3": "0x0C011820",
+ "4": "0x0D011410",
+ "5": "0x0D011420",
+ "6": "0x0D011810",
+ "7": "0x0D011820",
+ "8": "0x0E011410",
+ "9": "0x0E011420",
+ "10": "0x0E011810",
+ "11": "0x0E011820",
+ "12": "0x0F011410",
+ "13": "0x0F011420",
+ "14": "0x0F011810",
+ "15": "0x0F011820"
+ }
+ },
+ "MC_OMI_DL_CONFIG1": {
+ "instances": {
+ "0": "0x0C011411",
+ "1": "0x0C011421",
+ "2": "0x0C011811",
+ "3": "0x0C011821",
+ "4": "0x0D011411",
+ "5": "0x0D011421",
+ "6": "0x0D011811",
+ "7": "0x0D011821",
+ "8": "0x0E011411",
+ "9": "0x0E011421",
+ "10": "0x0E011811",
+ "11": "0x0E011821",
+ "12": "0x0F011411",
+ "13": "0x0F011421",
+ "14": "0x0F011811",
+ "15": "0x0F011821"
+ }
+ },
+ "MC_OMI_DL_ERR_MASK": {
+ "instances": {
+ "0": "0x0C011412",
+ "1": "0x0C011422",
+ "2": "0x0C011812",
+ "3": "0x0C011822",
+ "4": "0x0D011412",
+ "5": "0x0D011422",
+ "6": "0x0D011812",
+ "7": "0x0D011822",
+ "8": "0x0E011412",
+ "9": "0x0E011422",
+ "10": "0x0E011812",
+ "11": "0x0E011822",
+ "12": "0x0F011412",
+ "13": "0x0F011422",
+ "14": "0x0F011812",
+ "15": "0x0F011822"
+ }
+ },
+ "MC_OMI_DL_ERR_RPT": {
+ "instances": {
+ "0": "0x0C011413",
+ "1": "0x0C011423",
+ "2": "0x0C011813",
+ "3": "0x0C011823",
+ "4": "0x0D011413",
+ "5": "0x0D011423",
+ "6": "0x0D011813",
+ "7": "0x0D011823",
+ "8": "0x0E011413",
+ "9": "0x0E011423",
+ "10": "0x0E011813",
+ "11": "0x0E011823",
+ "12": "0x0F011413",
+ "13": "0x0F011423",
+ "14": "0x0F011813",
+ "15": "0x0F011823"
+ }
+ },
+ "MC_OMI_DL_ERR_CAPTURE": {
+ "instances": {
+ "0": "0x0C011414",
+ "1": "0x0C011424",
+ "2": "0x0C011814",
+ "3": "0x0C011824",
+ "4": "0x0D011414",
+ "5": "0x0D011424",
+ "6": "0x0D011814",
+ "7": "0x0D011824",
+ "8": "0x0E011414",
+ "9": "0x0E011424",
+ "10": "0x0E011814",
+ "11": "0x0E011824",
+ "12": "0x0F011414",
+ "13": "0x0F011424",
+ "14": "0x0F011814",
+ "15": "0x0F011824"
+ }
+ },
+ "MC_OMI_DL_EDPL_MAX_COUNT": {
+ "instances": {
+ "0": "0x0C011415",
+ "1": "0x0C011425",
+ "2": "0x0C011815",
+ "3": "0x0C011825",
+ "4": "0x0D011415",
+ "5": "0x0D011425",
+ "6": "0x0D011815",
+ "7": "0x0D011825",
+ "8": "0x0E011415",
+ "9": "0x0E011425",
+ "10": "0x0E011815",
+ "11": "0x0E011825",
+ "12": "0x0F011415",
+ "13": "0x0F011425",
+ "14": "0x0F011815",
+ "15": "0x0F011825"
+ }
+ },
+ "MC_OMI_DL_STATUS": {
+ "instances": {
+ "0": "0x0C011416",
+ "1": "0x0C011426",
+ "2": "0x0C011816",
+ "3": "0x0C011826",
+ "4": "0x0D011416",
+ "5": "0x0D011426",
+ "6": "0x0D011816",
+ "7": "0x0D011826",
+ "8": "0x0E011416",
+ "9": "0x0E011426",
+ "10": "0x0E011816",
+ "11": "0x0E011826",
+ "12": "0x0F011416",
+ "13": "0x0F011426",
+ "14": "0x0F011816",
+ "15": "0x0F011826"
+ }
+ },
+ "MC_OMI_DL_TRAINING_STATUS": {
+ "instances": {
+ "0": "0x0C011417",
+ "1": "0x0C011427",
+ "2": "0x0C011817",
+ "3": "0x0C011827",
+ "4": "0x0D011417",
+ "5": "0x0D011427",
+ "6": "0x0D011817",
+ "7": "0x0D011827",
+ "8": "0x0E011417",
+ "9": "0x0E011427",
+ "10": "0x0E011817",
+ "11": "0x0E011827",
+ "12": "0x0F011417",
+ "13": "0x0F011427",
+ "14": "0x0F011817",
+ "15": "0x0F011827"
+ }
+ },
+ "MC_OMI_DL_DLX_CONFIG": {
+ "instances": {
+ "0": "0x0C011418",
+ "1": "0x0C011428",
+ "2": "0x0C011818",
+ "3": "0x0C011828",
+ "4": "0x0D011418",
+ "5": "0x0D011428",
+ "6": "0x0D011818",
+ "7": "0x0D011828",
+ "8": "0x0E011418",
+ "9": "0x0E011428",
+ "10": "0x0E011818",
+ "11": "0x0E011828",
+ "12": "0x0F011418",
+ "13": "0x0F011428",
+ "14": "0x0F011818",
+ "15": "0x0F011828"
+ }
+ },
+ "MC_OMI_DL_DLX_INFO": {
+ "instances": {
+ "0": "0x0C011419",
+ "1": "0x0C011429",
+ "2": "0x0C011819",
+ "3": "0x0C011829",
+ "4": "0x0D011419",
+ "5": "0x0D011429",
+ "6": "0x0D011819",
+ "7": "0x0D011829",
+ "8": "0x0E011419",
+ "9": "0x0E011429",
+ "10": "0x0E011819",
+ "11": "0x0E011829",
+ "12": "0x0F011419",
+ "13": "0x0F011429",
+ "14": "0x0F011819",
+ "15": "0x0F011829"
+ }
+ },
+ "MC_OMI_DL_ERR_ACTION": {
+ "instances": {
+ "0": "0x0C01141D",
+ "1": "0x0C01142D",
+ "2": "0x0C01181D",
+ "3": "0x0C01182D",
+ "4": "0x0D01141D",
+ "5": "0x0D01142D",
+ "6": "0x0D01181D",
+ "7": "0x0D01182D",
+ "8": "0x0E01141D",
+ "9": "0x0E01142D",
+ "10": "0x0E01181D",
+ "11": "0x0E01182D",
+ "12": "0x0F01141D",
+ "13": "0x0F01142D",
+ "14": "0x0F01181D",
+ "15": "0x0F01182D"
+ }
+ },
+ "MC_OMI_DL_DEBUG_AID": {
+ "instances": {
+ "0": "0x0C01141E",
+ "1": "0x0C01142E",
+ "2": "0x0C01181E",
+ "3": "0x0C01182E",
+ "4": "0x0D01141E",
+ "5": "0x0D01142E",
+ "6": "0x0D01181E",
+ "7": "0x0D01182E",
+ "8": "0x0E01141E",
+ "9": "0x0E01142E",
+ "10": "0x0E01181E",
+ "11": "0x0E01182E",
+ "12": "0x0F01141E",
+ "13": "0x0F01142E",
+ "14": "0x0F01181E",
+ "15": "0x0F01182E"
+ }
+ },
+ "MC_OMI_DL_CYA_BITS": {
+ "instances": {
+ "0": "0x0C01141F",
+ "1": "0x0C01142F",
+ "2": "0x0C01181F",
+ "3": "0x0C01182F",
+ "4": "0x0D01141F",
+ "5": "0x0D01142F",
+ "6": "0x0D01181F",
+ "7": "0x0D01182F",
+ "8": "0x0E01141F",
+ "9": "0x0E01142F",
+ "10": "0x0E01181F",
+ "11": "0x0E01182F",
+ "12": "0x0F01141F",
+ "13": "0x0F01142F",
+ "14": "0x0F01181F",
+ "15": "0x0F01182F"
+ }
+ },
+ "MC_DSTL_ERR_RPT": {
+ "instances": {
+ "0": "0x0C010D0C",
+ "1": "0x0C010D4C",
+ "2": "0x0D010D0C",
+ "3": "0x0D010D4C",
+ "4": "0x0E010D0C",
+ "5": "0x0E010D4C",
+ "6": "0x0F010D0C",
+ "7": "0x0F010D4C"
+ }
+ },
+ "MC_DSTL_CFG2": {
+ "instances": {
+ "0": "0x0C010D0E",
+ "1": "0x0C010D4E",
+ "2": "0x0D010D0E",
+ "3": "0x0D010D4E",
+ "4": "0x0E010D0E",
+ "5": "0x0E010D4E",
+ "6": "0x0F010D0E",
+ "7": "0x0F010D4E"
+ }
+ },
+ "MC_ERR_RPT0": {
+ "instances": {
+ "0": "0x0C010C1E",
+ "1": "0x0D010C1E",
+ "2": "0x0E010C1E",
+ "3": "0x0F010C1E"
+ }
+ },
+ "MC_ERR_RPT1": {
+ "instances": {
+ "0": "0x0C010C1F",
+ "1": "0x0D010C1F",
+ "2": "0x0E010C1F",
+ "3": "0x0F010C1F"
+ }
+ },
+ "MC_ERR_RPT2": {
+ "instances": {
+ "0": "0x0C010C1A",
+ "1": "0x0D010C1A",
+ "2": "0x0E010C1A",
+ "3": "0x0F010C1A"
+ }
+ },
+ "MC_MISC_ERR_RPT": {
+ "instances": {
+ "0": "0x0C010FE7",
+ "1": "0x0D010FE7",
+ "2": "0x0E010FE7",
+ "3": "0x0F010FE7"
+ }
+ },
+ "CMN_CONFIG": {
+ "instances": {
+ "0": "0x0C01140E",
+ "1": "0x0C01180E",
+ "2": "0x0D01140E",
+ "3": "0x0D01180E",
+ "4": "0x0E01140E",
+ "5": "0x0E01180E",
+ "6": "0x0F01140E",
+ "7": "0x0F01180E"
+ }
+ },
+ "PMU_CNTR": {
+ "instances": {
+ "0": "0x0C01140F",
+ "1": "0x0C01180F",
+ "2": "0x0D01140F",
+ "3": "0x0D01180F",
+ "4": "0x0E01140F",
+ "5": "0x0E01180F",
+ "6": "0x0F01140F",
+ "7": "0x0F01180F"
+ }
+ },
+ "MC_USTL_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0C010E0E",
+ "1": "0x0C010E4E",
+ "2": "0x0D010E0E",
+ "3": "0x0D010E4E",
+ "4": "0x0E010E0E",
+ "5": "0x0E010E4E",
+ "6": "0x0F010E0E",
+ "7": "0x0F010E4E"
+ }
+ },
+ "MC_USTL_LOL_DROP": {
+ "instances": {
+ "0": "0x0C010E11",
+ "1": "0x0C010E51",
+ "2": "0x0D010E11",
+ "3": "0x0D010E51",
+ "4": "0x0E010E11",
+ "5": "0x0E010E51",
+ "6": "0x0F010E11",
+ "7": "0x0F010E51"
+ }
+ },
+ "MC_USTL_LOL_MASK": {
+ "instances": {
+ "0": "0x0C010E12",
+ "1": "0x0C010E52",
+ "2": "0x0D010E12",
+ "3": "0x0D010E52",
+ "4": "0x0E010E12",
+ "5": "0x0E010E52",
+ "6": "0x0F010E12",
+ "7": "0x0F010E52"
+ }
+ },
+ "MC_USTL_FAIL_MASK": {
+ "instances": {
+ "0": "0x0C010E13",
+ "1": "0x0C010E53",
+ "2": "0x0D010E13",
+ "3": "0x0D010E53",
+ "4": "0x0E010E13",
+ "5": "0x0E010E53",
+ "6": "0x0F010E13",
+ "7": "0x0F010E53"
+ }
+ },
+ "MC_USTL_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0C010E16",
+ "1": "0x0C010E56",
+ "2": "0x0D010E16",
+ "3": "0x0D010E56",
+ "4": "0x0E010E16",
+ "5": "0x0E010E56",
+ "6": "0x0F010E16",
+ "7": "0x0F010E56"
+ }
+ }
+ },
+ "capture_groups": {
+ "MC_OMI_DL_FIR": [
+ {
+ "reg_name": "MC_OMI_DL_CONFIG0",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG0",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG1",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CONFIG1",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_MASK",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_RPT",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_CAPTURE",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_CAPTURE",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_STATUS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_CONFIG",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_CONFIG",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_INFO",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DLX_INFO",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_ACTION",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_ERR_ACTION",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DEBUG_AID",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_DEBUG_AID",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CYA_BITS",
+ "reg_inst": {
+ "0": 0,
+ "1": 2,
+ "2": 4,
+ "3": 6,
+ "4": 8,
+ "5": 10,
+ "6": 12,
+ "7": 14
+ }
+ },
+ {
+ "reg_name": "MC_OMI_DL_CYA_BITS",
+ "reg_inst": {
+ "0": 1,
+ "1": 3,
+ "2": 5,
+ "3": 7,
+ "4": 9,
+ "5": 11,
+ "6": 13,
+ "7": 15
+ }
+ }
+ ],
+ "MC_DSTL_FIR": [
+ {
+ "reg_name": "MC_DSTL_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_DSTL_CFG2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ],
+ "MC_FIR": [
+ {
+ "reg_name": "MC_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "MC_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "MC_ERR_RPT2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "MC_MISC_FIR": [
+ {
+ "reg_name": "MC_MISC_ERR_RPT",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "MC_USTL_FIR": [
+ {
+ "reg_name": "MC_USTL_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_LOL_DROP",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_LOL_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_FAIL_MASK",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ },
+ {
+ "reg_name": "MC_USTL_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/regs_other.json b/chip_data/p10_20/regs_other.json
new file mode 100644
index 0000000..db9c43b
--- /dev/null
+++ b/chip_data/p10_20/regs_other.json
@@ -0,0 +1,756 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "HCA_ERR_RPT_HOLD_REG": {
+ "instances": {
+ "0": "0x03011D56"
+ }
+ },
+ "INT_CQ_ERR_RPT_HOLD": {
+ "instances": {
+ "0": "0x02010839"
+ }
+ },
+ "INT_CQ_ERR_INFO1": {
+ "instances": {
+ "0": "0x0201083B"
+ }
+ },
+ "INT_CQ_ERR_INFO2": {
+ "instances": {
+ "0": "0x0201083C"
+ }
+ },
+ "INT_CQ_ERR_INFO3": {
+ "instances": {
+ "0": "0x0201083D"
+ }
+ },
+ "INT_PC_ERR0_WOF": {
+ "instances": {
+ "0": "0x02010AC2"
+ }
+ },
+ "INT_PC_ERR0_WOF_DETAIL": {
+ "instances": {
+ "0": "0x02010AC3"
+ }
+ },
+ "INT_PC_ERR0_FATAL": {
+ "instances": {
+ "0": "0x02010AC4"
+ }
+ },
+ "INT_PC_ERR0_RECOV": {
+ "instances": {
+ "0": "0x02010AC5"
+ }
+ },
+ "INT_PC_ERR0_INFO": {
+ "instances": {
+ "0": "0x02010AC6"
+ }
+ },
+ "INT_PC_ERR1_WOF": {
+ "instances": {
+ "0": "0x02010ACA"
+ }
+ },
+ "INT_PC_ERR1_WOF_DETAIL": {
+ "instances": {
+ "0": "0x02010ACB"
+ }
+ },
+ "INT_PC_ERR1_FATAL": {
+ "instances": {
+ "0": "0x02010ACC"
+ }
+ },
+ "INT_PC_ERR1_RECOV": {
+ "instances": {
+ "0": "0x02010ACD"
+ }
+ },
+ "INT_PC_ERR1_INFO": {
+ "instances": {
+ "0": "0x02010ACE"
+ }
+ },
+ "INT_PC_NXC_WOF_ERR": {
+ "instances": {
+ "0": "0x02010AD2"
+ }
+ },
+ "INT_PC_NXC_WOF_ERR_DETAIL": {
+ "instances": {
+ "0": "0x02010AD3"
+ }
+ },
+ "INT_PC_NXC_FATAL_ERR": {
+ "instances": {
+ "0": "0x02010AD4"
+ }
+ },
+ "INT_PC_NXC_RECOV_ERR": {
+ "instances": {
+ "0": "0x02010AD5"
+ }
+ },
+ "INT_PC_NXC_INFO_ERR": {
+ "instances": {
+ "0": "0x02010AD6"
+ }
+ },
+ "INT_VC_WOF_ERR_G0": {
+ "instances": {
+ "0": "0x020109C2"
+ }
+ },
+ "INT_VC_WOF_ERR_G0_DETAIL": {
+ "instances": {
+ "0": "0x020109C3"
+ }
+ },
+ "INT_VC_FATAL_ERR_G0": {
+ "instances": {
+ "0": "0x020109C4"
+ }
+ },
+ "INT_VC_RECOV_ERR_G0": {
+ "instances": {
+ "0": "0x020109C5"
+ }
+ },
+ "INT_VC_INFO_ERR_G0": {
+ "instances": {
+ "0": "0x020109C6"
+ }
+ },
+ "INT_VC_WOF_ERR_G1": {
+ "instances": {
+ "0": "0x020109CA"
+ }
+ },
+ "INT_VC_WOF_ERR_G1_DETAIL": {
+ "instances": {
+ "0": "0x020109CB"
+ }
+ },
+ "INT_VC_FATAL_ERR_G1": {
+ "instances": {
+ "0": "0x020109CC"
+ }
+ },
+ "INT_VC_RECOV_ERR_G1": {
+ "instances": {
+ "0": "0x020109CD"
+ }
+ },
+ "INT_VC_INFO_ERR_G1": {
+ "instances": {
+ "0": "0x020109CE"
+ }
+ },
+ "NMMU_CQ_ERR_RPT_0": {
+ "instances": {
+ "0": "0x02010C22",
+ "1": "0x03010C22"
+ }
+ },
+ "NX_CQ_ERR_RPT_0": {
+ "instances": {
+ "0": "0x020110A2"
+ }
+ },
+ "NX_CQ_ERR_RPT_1": {
+ "instances": {
+ "0": "0x020110A1"
+ }
+ },
+ "SU_DMA_ERROR_REPORT_0": {
+ "instances": {
+ "0": "0x02011057"
+ }
+ },
+ "SU_DMA_ERROR_REPORT_1": {
+ "instances": {
+ "0": "0x02011058"
+ }
+ },
+ "OCC_SCOM_ERR_RPT": {
+ "instances": {
+ "0": "0x0101080A"
+ }
+ },
+ "OCC_SCOM_ERR_RPT2": {
+ "instances": {
+ "0": "0x0101080B"
+ }
+ },
+ "PB_TL_LINK_SYN_01": {
+ "instances": {
+ "0": "0x10011812",
+ "1": "0x11011812",
+ "2": "0x12011812",
+ "3": "0x13011812"
+ }
+ },
+ "PB_TL_LINK_SYN_23": {
+ "instances": {
+ "0": "0x10011813",
+ "1": "0x11011813",
+ "2": "0x12011813",
+ "3": "0x13011813"
+ }
+ },
+ "PB_EN_DOB_ECC_ERR": {
+ "instances": {
+ "0": "0x10011818",
+ "1": "0x11011818",
+ "2": "0x12011818",
+ "3": "0x13011818"
+ }
+ },
+ "PB_MISC_CFG": {
+ "instances": {
+ "0": "0x10011825",
+ "1": "0x11011825",
+ "2": "0x12011825",
+ "3": "0x13011825"
+ }
+ },
+ "PB_STATION_MODE_EN1": {
+ "instances": {
+ "0": "0x0301120A"
+ }
+ },
+ "PB_STATION_MODE_EN2": {
+ "instances": {
+ "0": "0x0301124A"
+ }
+ },
+ "PB_STATION_MODE_EN3": {
+ "instances": {
+ "0": "0x0301128A"
+ }
+ },
+ "PB_STATION_MODE_EN4": {
+ "instances": {
+ "0": "0x030112CA"
+ }
+ },
+ "PB_STATION_MODE_EQ": {
+ "instances": {
+ "0": "0x0301100A",
+ "1": "0x0301104A",
+ "2": "0x0301108A",
+ "3": "0x030110CA",
+ "4": "0x0301110A",
+ "5": "0x0301114A",
+ "6": "0x0301118A",
+ "7": "0x030111CA"
+ }
+ },
+ "PB_STATION_MODE_ES1": {
+ "instances": {
+ "0": "0x0301130A"
+ }
+ },
+ "PB_STATION_MODE_ES2": {
+ "instances": {
+ "0": "0x0301134A"
+ }
+ },
+ "PB_STATION_MODE_ES3": {
+ "instances": {
+ "0": "0x0301138A"
+ }
+ },
+ "PB_STATION_MODE_ES4": {
+ "instances": {
+ "0": "0x030113CA"
+ }
+ },
+ "PBA_ERR_RPT0": {
+ "instances": {
+ "0": "0x03011DCC"
+ }
+ },
+ "PBA_ERR_RPT1": {
+ "instances": {
+ "0": "0x03011DCD"
+ }
+ },
+ "PBA_ERR_RPT2": {
+ "instances": {
+ "0": "0x03011DCE"
+ }
+ },
+ "PBAO_ERR_RPT_1": {
+ "instances": {
+ "0": "0x01010CCD"
+ }
+ },
+ "PBAO_ERR_RPT_2": {
+ "instances": {
+ "0": "0x01010CCE"
+ }
+ },
+ "PBAIB_CERR_RPT_REG": {
+ "instances": {
+ "0": "0x0801084B",
+ "1": "0x0801088B",
+ "2": "0x080108CB",
+ "3": "0x0901084B",
+ "4": "0x0901088B",
+ "5": "0x090108CB"
+ }
+ },
+ "PCI_NFIR_ERR_RPT0": {
+ "instances": {
+ "0": "0x0301184A",
+ "1": "0x0301188A",
+ "2": "0x030118CA",
+ "3": "0x0201184A",
+ "4": "0x0201188A",
+ "5": "0x020118CA"
+ }
+ },
+ "PCI_NFIR_ERR_RPT1": {
+ "instances": {
+ "0": "0x0301184B",
+ "1": "0x0301188B",
+ "2": "0x030118CB",
+ "3": "0x0201184B",
+ "4": "0x0201188B",
+ "5": "0x020118CB"
+ }
+ }
+ },
+ "capture_groups": {
+ "HCA_FIR": [
+ {
+ "reg_name": "HCA_ERR_RPT_HOLD_REG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "INT_CQ_FIR": [
+ {
+ "reg_name": "INT_CQ_ERR_RPT_HOLD",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_CQ_ERR_INFO3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_WOF",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_WOF_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_FATAL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_RECOV",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR0_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_WOF",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_WOF_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_FATAL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_RECOV",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_ERR1_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_WOF_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_WOF_ERR_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_FATAL_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_RECOV_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_PC_NXC_INFO_ERR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G0_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_FATAL_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_RECOV_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_INFO_ERR_G0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_WOF_ERR_G1_DETAIL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_FATAL_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_RECOV_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "INT_VC_INFO_ERR_G1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "NMMU_CQ_FIR": [
+ {
+ "reg_name": "NMMU_CQ_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ],
+ "NX_CQ_FIR": [
+ {
+ "reg_name": "NX_CQ_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "NX_CQ_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "NX_DMA_ENG_FIR": [
+ {
+ "reg_name": "SU_DMA_ERROR_REPORT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SU_DMA_ERROR_REPORT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "OCC_FIR": [
+ {
+ "reg_name": "OCC_SCOM_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "OCC_SCOM_ERR_RPT2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PAU_PTL_FIR": [
+ {
+ "reg_name": "PB_TL_LINK_SYN_01",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_TL_LINK_SYN_23",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_EN_DOB_ECC_ERR",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ },
+ {
+ "reg_name": "PB_MISC_CFG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN1": [
+ {
+ "reg_name": "PB_STATION_MODE_EN1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN2": [
+ {
+ "reg_name": "PB_STATION_MODE_EN2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN3": [
+ {
+ "reg_name": "PB_STATION_MODE_EN3",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EN4": [
+ {
+ "reg_name": "PB_STATION_MODE_EN4",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_EQ": [
+ {
+ "reg_name": "PB_STATION_MODE_EQ",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES1": [
+ {
+ "reg_name": "PB_STATION_MODE_ES1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES2": [
+ {
+ "reg_name": "PB_STATION_MODE_ES2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES3": [
+ {
+ "reg_name": "PB_STATION_MODE_ES3",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PB_STATION_FIR_ES4": [
+ {
+ "reg_name": "PB_STATION_MODE_ES4",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PBAF_FIR": [
+ {
+ "reg_name": "PBA_ERR_RPT0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBA_ERR_RPT1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBA_ERR_RPT2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PBAO_FIR": [
+ {
+ "reg_name": "PBAO_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PBAO_ERR_RPT_2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ],
+ "PCI_FIR": [
+ {
+ "reg_name": "PBAIB_CERR_RPT_REG",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ],
+ "PCI_NEST_FIR": [
+ {
+ "reg_name": "PCI_NFIR_ERR_RPT0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ },
+ {
+ "reg_name": "PCI_NFIR_ERR_RPT1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/p10_20/tod_error.json b/chip_data/p10_20/tod_error.json
new file mode 100644
index 0000000..384899f
--- /dev/null
+++ b/chip_data/p10_20/tod_error.json
@@ -0,0 +1,599 @@
+{
+ "version": 1,
+ "model_ec": ["P10_20"],
+ "registers": {
+ "TOD_M_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040000"
+ }
+ },
+ "TOD_PRI_PORT_0_CTRL": {
+ "instances": {
+ "0": "0x00040001"
+ }
+ },
+ "TOD_PRI_PORT_1_CTRL": {
+ "instances": {
+ "0": "0x00040002"
+ }
+ },
+ "TOD_SEC_PORT_0_CTRL": {
+ "instances": {
+ "0": "0x00040003"
+ }
+ },
+ "TOD_SEC_PORT_1_CTRL": {
+ "instances": {
+ "0": "0x00040004"
+ }
+ },
+ "TOD_S_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040005"
+ }
+ },
+ "TOD_I_PATH_CTRL": {
+ "instances": {
+ "0": "0x00040006"
+ }
+ },
+ "TOD_PSS_MSS_CTRL": {
+ "instances": {
+ "0": "0x00040007"
+ }
+ },
+ "TOD_PSS_MSS_STATUS": {
+ "instances": {
+ "0": "0x00040008"
+ }
+ },
+ "TOD_M_PATH_STATUS": {
+ "instances": {
+ "0": "0x00040009"
+ }
+ },
+ "TOD_S_PATH_STATUS": {
+ "instances": {
+ "0": "0x0004000A"
+ }
+ },
+ "TOD_M_PATH_0_STEP_STEER": {
+ "instances": {
+ "0": "0x0004000E"
+ }
+ },
+ "TOD_M_PATH_1_STEP_STEER": {
+ "instances": {
+ "0": "0x0004000F"
+ }
+ },
+ "TOD_CHIP_CTRL": {
+ "instances": {
+ "0": "0x00040010"
+ }
+ },
+ "TOD_TRACE_DATA_1": {
+ "instances": {
+ "0": "0x0004001D"
+ }
+ },
+ "TOD_TRACE_DATA_2": {
+ "instances": {
+ "0": "0x0004001E"
+ }
+ },
+ "TOD_TRACE_DATA_3": {
+ "instances": {
+ "0": "0x0004001F"
+ }
+ },
+ "TOD_FSM": {
+ "instances": {
+ "0": "0x00040024"
+ }
+ },
+ "TOD_TX_TTYPE_CTRL": {
+ "instances": {
+ "0": "0x00040027"
+ }
+ },
+ "TOD_RX_TTYPE_CTRL": {
+ "instances": {
+ "0": "0x00040029"
+ }
+ },
+ "TOD_ERROR": {
+ "instances": {
+ "0": "0x00040030"
+ }
+ },
+ "TOD_ERROR_MASK": {
+ "instances": {
+ "0": "0x00040032"
+ }
+ },
+ "TOD_ERROR_ROUTING": {
+ "instances": {
+ "0": "0x00040033"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TOD_ERROR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["HA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TOD_ERROR_ROUTING"
+ }
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "M_PATH_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "1": {
+ "desc": "M_PATH_0_PARITY_ERROR"
+ },
+ "2": {
+ "desc": "M_PATH_1_PARITY_ERROR"
+ },
+ "3": {
+ "desc": "PCRP0_DATA_PARITY_ERROR"
+ },
+ "4": {
+ "desc": "PCRP1_DATA_PARITY_ERROR"
+ },
+ "5": {
+ "desc": "SCRP0_DATA_PARITY_ERROR"
+ },
+ "6": {
+ "desc": "SCRP1_DATA_PARITY_ERROR"
+ },
+ "7": {
+ "desc": "SPCR_DATA_PARITY_ERROR"
+ },
+ "8": {
+ "desc": "IPCR_DATA_PARITY_ERROR"
+ },
+ "9": {
+ "desc": "PSMSCR_DATA_PARITY_ERROR"
+ },
+ "10": {
+ "desc": "S_PATH_0_PARITY_ERROr"
+ },
+ "11": {
+ "desc": "REG_0X08_DATA_PARITY_ERROR"
+ },
+ "12": {
+ "desc": "M_PATH_STATUS_REG_DATA_PARITY_ERROR"
+ },
+ "13": {
+ "desc": "S_PATH_STATUS_REG_DATA_PARITY_ERROR"
+ },
+ "14": {
+ "desc": "M_PATH_0_STEP_CHECK_ERROR"
+ },
+ "15": {
+ "desc": "M_PATH_1_STEP_CHECK_ERROR"
+ },
+ "16": {
+ "desc": "S_PATH_0_STEP_CHECK_ERROR"
+ },
+ "17": {
+ "desc": "I_PATH_STEP_CHECK_ERROR"
+ },
+ "18": {
+ "desc": "PSS HAMMING DISTANCE"
+ },
+ "19": {
+ "desc": "MISC_RESET_REG_DATA_PARITY_ERROR"
+ },
+ "20": {
+ "desc": "S_PATH_0_PARITY_ERROR"
+ },
+ "21": {
+ "desc": "S_PATH_1_STEP_CHECK_ERROR"
+ },
+ "22": {
+ "desc": "I_PATH_DELAY_STEP_CHECK_PARITY_ERROR"
+ },
+ "23": {
+ "desc": "REG_0X0C DATA_PARITY ERROR"
+ },
+ "24": {
+ "desc": "REG_0X11_0X12_0X13_0X14_0X15_0X16_DATA_PARITY_ERROR"
+ },
+ "25": {
+ "desc": "REG_0X17_0X18_0X21_0X22_DATA_PARITY_ERROR"
+ },
+ "26": {
+ "desc": "REG_0X1D_0X1E_0X1F_DATA_PARITY_ERROR"
+ },
+ "27": {
+ "desc": "TIMER_VALUE_REG_DATA_PARITY_ERROR"
+ },
+ "28": {
+ "desc": "LOW_ORDER_STEP_REG_DATA_PARITY_ERROR"
+ },
+ "29": {
+ "desc": "FSM_REG_DATA_PARITY_ERROR"
+ },
+ "30": {
+ "desc": "RX_TTYPE_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "31": {
+ "desc": "REG_0X30_0X31_0X32_0X33_DATA_PARITY_ERROR"
+ },
+ "32": {
+ "desc": "CHIP_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "33": {
+ "desc": "I_PATH_SYNC_CHECK_ERROR"
+ },
+ "34": {
+ "desc": "I_PATH_FSM_STATE_PARITY_ERROR"
+ },
+ "35": {
+ "desc": "I_PATH_TIME_REG_PARITY_ERROR"
+ },
+ "36": {
+ "desc": "I_PATH_TIME_REG_OVERFLOW"
+ },
+ "37": {
+ "desc": "WOF_LOW_ORDER_STEP_COUNTER_PARITY_ERROR"
+ },
+ "38": {
+ "desc": "RX_TTYPE_1"
+ },
+ "39": {
+ "desc": "RX_TTYPE_1"
+ },
+ "40": {
+ "desc": "RX_TTYPE_1"
+ },
+ "41": {
+ "desc": "RX_TTYPE_1"
+ },
+ "42": {
+ "desc": "RX_TTYPE_1"
+ },
+ "43": {
+ "desc": "RX_TTYPE_1"
+ },
+ "44": {
+ "desc": "PIB_SLAVE_ADDR_INVALID_ERROR"
+ },
+ "45": {
+ "desc": "PIB_SLAVE_WRITE_INVALID_ERROR"
+ },
+ "46": {
+ "desc": "PIB_SLAVE_READ_INVALID_ERROR"
+ },
+ "47": {
+ "desc": "PIB_SLAVE_ADDR_PARITY_ERROR"
+ },
+ "48": {
+ "desc": "PIB_SLAVE_DATA_PARITY_ERROR"
+ },
+ "49": {
+ "desc": "TTYPE_CONTROL_REG_DATA_PARITY_ERROR"
+ },
+ "50": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "51": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "52": {
+ "desc": "PIB_MASTER_RSP_INFO_ERROR"
+ },
+ "53": {
+ "desc": "RX_TTYPE_INVALID_ERROR"
+ },
+ "54": {
+ "desc": "RX_TTYPE_4_DATA_PARITY_ERROR"
+ },
+ "55": {
+ "desc": "PIB_MASTER_REQUEST_ERROR"
+ },
+ "56": {
+ "desc": "PIB_RESET_DURING_PIB_ACCESS_ERROR"
+ },
+ "57": {
+ "desc": "EXTERNAL_XSTOP_ERROR"
+ },
+ "58": {
+ "desc": "SPARE_ERROR"
+ },
+ "59": {
+ "desc": "SPARE_ERROR"
+ },
+ "60": {
+ "desc": "SPARE_ERROR"
+ },
+ "61": {
+ "desc": "SPARE_ERROR"
+ },
+ "62": {
+ "desc": "SPARE_ERROR"
+ },
+ "63": {
+ "desc": "SPARE_ERROR"
+ }
+ }
+ }
+ },
+ "capture_groups": {
+ "TOD_ERROR": [
+ {
+ "reg_name": "TOD_M_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PRI_PORT_0_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PRI_PORT_1_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_SEC_PORT_0_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_SEC_PORT_1_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_S_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_I_PATH_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PSS_MSS_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_PSS_MSS_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_S_PATH_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_0_STEP_STEER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_M_PATH_1_STEP_STEER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_CHIP_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TRACE_DATA_3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_FSM",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_TX_TTYPE_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_RX_TTYPE_CTRL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TOD_ERROR_ROUTING",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/schema/chip_data_schema_v01.json b/chip_data/schema/chip_data_schema_v01.json
new file mode 100644
index 0000000..7a47c07
--- /dev/null
+++ b/chip_data/schema/chip_data_schema_v01.json
@@ -0,0 +1,332 @@
+{
+ "$schema": "https://json-schema.org/draft/2020-12/schema",
+ "title": "Chip Data Schema",
+ "version": 1,
+ "type": "object",
+ "required": ["version", "model_ec"],
+ "additionalProperties": false,
+ "properties": {
+ "version": {
+ "type": "integer",
+ "minimum": 1,
+ "maximum": 1
+ },
+ "model_ec": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/model_ec" }
+ },
+ "registers": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^\\w+$": { "$ref": "#/$defs/register" }
+ }
+ },
+ "isolation_nodes": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^\\w+$": { "$ref": "#/$defs/isolation_node" }
+ }
+ },
+ "root_nodes": {
+ "type": "object",
+ "propertyNames": { "$ref": "#/$defs/attn_type" },
+ "patternProperties": {
+ "": { "$ref": "#/$defs/root_node" }
+ }
+ },
+ "capture_groups": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^\\w+$": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/capture_register" }
+ }
+ }
+ }
+ },
+ "$defs": {
+ "name": {
+ "type": "string",
+ "pattern": "^\\w+$"
+ },
+ "instance": {
+ "type": "integer",
+ "minimum": 0
+ },
+ "instance_array": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/instance" }
+ },
+ "instance_map": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^[0-9]+$": { "$ref": "#/$defs/instance" }
+ }
+ },
+ "hex_string": {
+ "type": "string",
+ "pattern": "^0x([0-9a-fA-F]{8}){1,2}$"
+ },
+ "model_ec": {
+ "type": "string",
+ "enum": [
+ "P10_10",
+ "P10_20",
+ "EXPLORER_11",
+ "EXPLORER_20",
+ "ODYSSEY_10",
+ "P11S_10",
+ "P11T_10"
+ ]
+ },
+ "attn_type": {
+ "type": "string",
+ "enum": ["CS", "UCS", "RE", "SPA", "HA"]
+ },
+ "reg_type": {
+ "type": "string",
+ "enum": ["SCOM", "IDSCOM"]
+ },
+ "access_type": {
+ "type": "string",
+ "enum": ["RO", "WO", "RW"]
+ },
+ "register": {
+ "type": "object",
+ "required": ["instances"],
+ "additionalProperties": false,
+ "properties": {
+ "reg_type": { "$ref": "#/$defs/reg_type" },
+ "access": { "$ref": "#/$defs/access_type" },
+ "instances": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^[0-9]+$": { "$ref": "#/$defs/hex_string" }
+ }
+ }
+ }
+ },
+ "isolation_node": {
+ "type": "object",
+ "required": ["instances", "rules", "bits"],
+ "additionalProperties": false,
+ "properties": {
+ "reg_type": { "$ref": "#/$defs/reg_type" },
+ "instances": { "$ref": "#/$defs/instance_array" },
+ "rules": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/isolation_rule" }
+ },
+ "bits": {
+ "type": "object",
+ "additionalProperties": false,
+ "patternProperties": {
+ "^[0-9]+(:[0-9]+)?$": {
+ "$ref": "#/$defs/isolation_bit"
+ }
+ }
+ },
+ "capture_groups": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/capture_group" }
+ }
+ }
+ },
+ "isolation_rule": {
+ "type": "object",
+ "required": ["attn_type", "node_inst", "expr"],
+ "additionalProperties": false,
+ "properties": {
+ "attn_type": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/attn_type" }
+ },
+ "node_inst": { "$ref": "#/$defs/instance_array" },
+ "expr": { "$ref": "#/$defs/isolation_rule_expression" }
+ }
+ },
+ "isolation_rule_expression": {
+ "type": "object",
+ "required": ["expr_type"],
+ "properties": {
+ "expr_type": {
+ "type": "string",
+ "enum": [
+ "reg",
+ "int",
+ "and",
+ "or",
+ "not",
+ "lshift",
+ "rshift"
+ ]
+ },
+ "reg_name": { "$ref": "#/$defs/name" },
+ "reg_inst": { "$ref": "#/$defs/instance_map" },
+ "int_value": { "$ref": "#/$defs/hex_string" },
+ "expr": { "$ref": "#/$defs/isolation_rule_expression" },
+ "exprs": {
+ "type": "array",
+ "minItems": 2,
+ "items": { "$ref": "#/$defs/isolation_rule_expression" }
+ },
+ "shift_value": {
+ "type": "integer",
+ "minimum": 0
+ }
+ },
+ "allOf": [
+ {
+ "if": { "properties": { "expr_type": { "const": "reg" } } },
+ "then": {
+ "required": ["reg_name"],
+ "not": {
+ "required": [
+ "int_value",
+ "shift_value",
+ "expr",
+ "exprs"
+ ]
+ }
+ }
+ },
+ {
+ "if": { "properties": { "expr_type": { "const": "int" } } },
+ "then": {
+ "required": ["int_value"],
+ "not": {
+ "required": [
+ "reg_name",
+ "reg_inst",
+ "shift_value",
+ "expr",
+ "exprs"
+ ]
+ }
+ }
+ },
+ {
+ "if": {
+ "properties": {
+ "expr_type": { "enum": ["and", "or"] }
+ }
+ },
+ "then": {
+ "required": ["exprs"],
+ "not": {
+ "required": [
+ "reg_name",
+ "reg_inst",
+ "int_value",
+ "shift_value",
+ "expr"
+ ]
+ }
+ }
+ },
+ {
+ "if": { "properties": { "expr_type": { "const": "not" } } },
+ "then": {
+ "required": ["expr"],
+ "not": {
+ "required": [
+ "reg_name",
+ "reg_inst",
+ "int_value",
+ "shift_value",
+ "exprs"
+ ]
+ }
+ }
+ },
+ {
+ "if": {
+ "properties": {
+ "expr_type": { "enum": ["lshift", "rshift"] }
+ }
+ },
+ "then": {
+ "required": ["expr", "shift_value"],
+ "not": {
+ "required": [
+ "reg_name",
+ "reg_inst",
+ "int_value",
+ "exprs"
+ ]
+ }
+ }
+ }
+ ]
+ },
+ "isolation_bit": {
+ "type": "object",
+ "required": ["desc"],
+ "additionalProperties": false,
+ "properties": {
+ "desc": {
+ "type": "string"
+ },
+ "child_node": {
+ "type": "object",
+ "required": ["name"],
+ "additionalProperties": false,
+ "properties": {
+ "name": { "$ref": "#/$defs/name" },
+ "inst": { "$ref": "#/$defs/instance_map" }
+ }
+ },
+ "capture_groups": {
+ "type": "array",
+ "minItems": 1,
+ "uniqueItems": true,
+ "items": { "$ref": "#/$defs/capture_group" }
+ }
+ }
+ },
+ "capture_group": {
+ "type": "object",
+ "required": ["group_name", "group_inst"],
+ "additionalProperties": false,
+ "properties": {
+ "group_name": { "$ref": "#/$defs/name" },
+ "group_inst": { "$ref": "#/$defs/instance_map" }
+ }
+ },
+ "root_node": {
+ "type": "object",
+ "required": ["name", "inst"],
+ "additionalProperties": false,
+ "properties": {
+ "name": { "$ref": "#/$defs/name" },
+ "inst": { "$ref": "#/$defs/instance" }
+ }
+ },
+ "capture_register": {
+ "type": "object",
+ "required": ["reg_name", "reg_inst"],
+ "additionalProperties": false,
+ "properties": {
+ "reg_name": { "$ref": "#/$defs/name" },
+ "reg_inst": { "$ref": "#/$defs/instance_map" }
+ }
+ }
+ }
+}