diff --git a/chip_data/explorer/chip_explorer.json b/chip_data/explorer/chip_explorer.json
new file mode 100644
index 0000000..98e3320
--- /dev/null
+++ b/chip_data/explorer/chip_explorer.json
@@ -0,0 +1,18 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "root_nodes": {
+        "CS": {
+            "name": "CHIPLET_OCMB_FIR",
+            "inst": 0
+        },
+        "RE": {
+            "name": "CHIPLET_OCMB_FIR",
+            "inst": 0
+        },
+        "SPA": {
+            "name": "CHIPLET_OCMB_SPA_FIR",
+            "inst": 0
+        }
+    }
+}
diff --git a/chip_data/explorer/node_chiplet_ocmb_fir.json b/chip_data/explorer/node_chiplet_ocmb_fir.json
new file mode 100644
index 0000000..1bd1910
--- /dev/null
+++ b/chip_data/explorer/node_chiplet_ocmb_fir.json
@@ -0,0 +1,124 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "CHIPLET_OCMB_CS_FIR": {
+            "instances": {
+                "0": "0x08040000"
+            }
+        },
+        "CHIPLET_OCMB_RE_FIR": {
+            "instances": {
+                "0": "0x08040001"
+            }
+        },
+        "CHIPLET_OCMB_FIR_MASK": {
+            "instances": {
+                "0": "0x08040002"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "CHIPLET_OCMB_FIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "CHIPLET_OCMB_CS_FIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x1FFFFFFFFFFFFFFF"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "rshift",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "CHIPLET_OCMB_RE_FIR"
+                                },
+                                "shift_value": 2
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "CHIPLET_OCMB_FIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x1FFFFFFFFFFFFFFF"
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "3": {
+                    "desc": "Attention from OCMB_LFIR",
+                    "child_node": {
+                        "name": "OCMB_LFIR"
+                    }
+                },
+                "4": {
+                    "desc": "Attention from MMIOFIR",
+                    "child_node": {
+                        "name": "MMIOFIR"
+                    }
+                },
+                "7": {
+                    "desc": "Attention from SRQFIR",
+                    "child_node": {
+                        "name": "SRQFIR"
+                    }
+                },
+                "8": {
+                    "desc": "Attention from MCBISTFIR",
+                    "child_node": {
+                        "name": "MCBISTFIR"
+                    }
+                },
+                "9": {
+                    "desc": "Attention from RDFFIR",
+                    "child_node": {
+                        "name": "RDFFIR"
+                    }
+                },
+                "11": {
+                    "desc": "Attention from TLXFIR",
+                    "child_node": {
+                        "name": "TLXFIR"
+                    }
+                },
+                "12": {
+                    "desc": "Attention from OMI_DL_FIR",
+                    "child_node": {
+                        "name": "OMI_DL_FIR"
+                    }
+                }
+            }
+        }
+    }
+}
diff --git a/chip_data/explorer/node_chiplet_ocmb_spa_fir.json b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
new file mode 100644
index 0000000..0865a6e
--- /dev/null
+++ b/chip_data/explorer/node_chiplet_ocmb_spa_fir.json
@@ -0,0 +1,81 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "CHIPLET_OCMB_SPA_FIR": {
+            "instances": {
+                "0": "0x08040004"
+            }
+        },
+        "CHIPLET_OCMB_SPA_FIR_MASK": {
+            "instances": {
+                "0": "0x08040007"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "CHIPLET_OCMB_SPA_FIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "CHIPLET_OCMB_SPA_FIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "CHIPLET_OCMB_SPA_FIR_MASK"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "1": {
+                    "desc": "Attention from MMIOFIR",
+                    "child_node": {
+                        "name": "MMIOFIR"
+                    }
+                },
+                "4": {
+                    "desc": "Attention from SRQFIR",
+                    "child_node": {
+                        "name": "SRQFIR"
+                    }
+                },
+                "5": {
+                    "desc": "Attention from MCBISTFIR",
+                    "child_node": {
+                        "name": "MCBISTFIR"
+                    }
+                },
+                "6": {
+                    "desc": "Attention from RDFFIR",
+                    "child_node": {
+                        "name": "RDFFIR"
+                    }
+                },
+                "8": {
+                    "desc": "Attention from TLXFIR",
+                    "child_node": {
+                        "name": "TLXFIR"
+                    }
+                },
+                "9": {
+                    "desc": "Attention from OMI_DL_FIR",
+                    "child_node": {
+                        "name": "OMI_DL_FIR"
+                    }
+                }
+            }
+        }
+    }
+}
diff --git a/chip_data/explorer/node_mcbistfir.json b/chip_data/explorer/node_mcbistfir.json
new file mode 100644
index 0000000..80dde58
--- /dev/null
+++ b/chip_data/explorer/node_mcbistfir.json
@@ -0,0 +1,227 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "MCBISTFIR": {
+            "instances": {
+                "0": "0x08011800"
+            }
+        },
+        "MCBISTFIR_MASK": {
+            "instances": {
+                "0": "0x08011803"
+            }
+        },
+        "MCBISTFIR_ACT0": {
+            "instances": {
+                "0": "0x08011806"
+            }
+        },
+        "MCBISTFIR_ACT1": {
+            "instances": {
+                "0": "0x08011807"
+            }
+        },
+        "MCBISTFIR_WOF": {
+            "instances": {
+                "0": "0x08011808"
+            }
+        },
+        "MCB_ERR_RPT_0": {
+            "instances": {
+                "0": "0x080118E7"
+            }
+        },
+        "MCB_ERR_RPT_1": {
+            "instances": {
+                "0": "0x080118EC"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "MCBISTFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MCBISTFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MCBISTFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MCBISTFIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MCBISTFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MCBISTFIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MCBISTFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "Invalid maint address"
+                },
+                "1": {
+                    "desc": "Command address timeout"
+                },
+                "2": {
+                    "desc": "Internal FSM error"
+                },
+                "3": {
+                    "desc": "MCBIST broadcast out of sync"
+                },
+                "4": {
+                    "desc": "MCBIST data error"
+                },
+                "5": {
+                    "desc": "Hard NCE ETE attn"
+                },
+                "6": {
+                    "desc": "Soft NCE ETE attn"
+                },
+                "7": {
+                    "desc": "Int NCE ETE attn"
+                },
+                "8": {
+                    "desc": "RCE ETE attn"
+                },
+                "9": {
+                    "desc": "ICE (IMPE) ETE attn"
+                },
+                "10": {
+                    "desc": "MCBIST program complete"
+                },
+                "11": {
+                    "desc": "MCBIST CCS subtest done"
+                },
+                "12": {
+                    "desc": "WAT debug bus attn"
+                },
+                "13": {
+                    "desc": "SCOM recoverable register parity error"
+                },
+                "14": {
+                    "desc": "SCOM fatal reg parity error"
+                },
+                "15": {
+                    "desc": "SCOM WAT and debug reg parity error"
+                },
+                "16:17": {
+                    "desc": "Reserved"
+                },
+                "18": {
+                    "desc": "Internal SCOM error"
+                },
+                "19": {
+                    "desc": "Internal SCOM error clone"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "MCBISTFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "MCBISTFIR": [
+            {
+                "reg_name": "MCB_ERR_RPT_0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCB_ERR_RPT_1",
+                "reg_inst": {
+                    "0": 0
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_mmiofir.json b/chip_data/explorer/node_mmiofir.json
new file mode 100644
index 0000000..300d1e2
--- /dev/null
+++ b/chip_data/explorer/node_mmiofir.json
@@ -0,0 +1,206 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "MMIOFIR": {
+            "instances": {
+                "0": "0x08010870"
+            }
+        },
+        "MMIOFIR_MASK": {
+            "instances": {
+                "0": "0x08010873"
+            }
+        },
+        "MMIOFIR_ACT0": {
+            "instances": {
+                "0": "0x08010876"
+            }
+        },
+        "MMIOFIR_ACT1": {
+            "instances": {
+                "0": "0x08010877"
+            }
+        },
+        "MMIOFIR_WOF": {
+            "instances": {
+                "0": "0x08010878"
+            }
+        },
+        "MMIO_ERR_RPT_0": {
+            "instances": {
+                "0": "0x0801087C"
+            }
+        },
+        "MMIO_ERR_RPT_1": {
+            "instances": {
+                "0": "0x0801087E"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "MMIOFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MMIOFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MMIOFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MMIOFIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MMIOFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "MMIOFIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "MMIOFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "AFU desc unimp"
+                },
+                "1": {
+                    "desc": "MMIO err"
+                },
+                "2": {
+                    "desc": "SCOM err"
+                },
+                "3": {
+                    "desc": "FSM perr"
+                },
+                "4": {
+                    "desc": "FIFO overflow"
+                },
+                "5": {
+                    "desc": "Ctl reg parity err"
+                },
+                "6": {
+                    "desc": "Info reg parity error"
+                },
+                "7": {
+                    "desc": "SNSC both starts err"
+                },
+                "8": {
+                    "desc": "SNSC mult seq parity err"
+                },
+                "9": {
+                    "desc": "SNSC FSM parity err"
+                },
+                "10": {
+                    "desc": "SNSC reg parity err"
+                },
+                "11": {
+                    "desc": "acTAG PASID cfg err"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "MMIOFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "MMIOFIR": [
+            {
+                "reg_name": "MMIO_ERR_RPT_0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MMIO_ERR_RPT_1",
+                "reg_inst": {
+                    "0": 0
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_ocmb_lfir.json b/chip_data/explorer/node_ocmb_lfir.json
new file mode 100644
index 0000000..fa784af
--- /dev/null
+++ b/chip_data/explorer/node_ocmb_lfir.json
@@ -0,0 +1,349 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "OCMB_LFIR": {
+            "instances": {
+                "0": "0x0804000A"
+            }
+        },
+        "OCMB_LFIR_MASK": {
+            "instances": {
+                "0": "0x0804000D"
+            }
+        },
+        "OCMB_LFIR_ACT0": {
+            "instances": {
+                "0": "0x08040010"
+            }
+        },
+        "OCMB_LFIR_ACT1": {
+            "instances": {
+                "0": "0x08040011"
+            }
+        },
+        "ADSP_PCBI": {
+            "instances": {
+                "0": "0x00200860",
+                "1": "0x00201860",
+                "2": "0x00202860",
+                "3": "0x00203860",
+                "4": "0x00204860",
+                "5": "0x00205860",
+                "6": "0x00206860",
+                "7": "0x00207860"
+            }
+        },
+        "CSU_PCBI": {
+            "instances": {
+                "0": "0x002000B0",
+                "1": "0x002010B0",
+                "2": "0x002020B0",
+                "3": "0x002030B0",
+                "4": "0x002040B0",
+                "5": "0x002050B0",
+                "6": "0x002060B0",
+                "7": "0x002070B0"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "OCMB_LFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OCMB_LFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OCMB_LFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OCMB_LFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OCMB_LFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OCMB_LFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OCMB_LFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OCMB_LFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OCMB_LFIR_ACT1"
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "CFIR access PCB error"
+                },
+                "1": {
+                    "desc": "CFIR internal parity error"
+                },
+                "2": {
+                    "desc": "LFIR internal parity error"
+                },
+                "3": {
+                    "desc": "Debug scom satellite error"
+                },
+                "4": {
+                    "desc": "PSCOM Logic: PCB Access Error"
+                },
+                "5": {
+                    "desc": "PSCOM Logic: Summarized internal errors"
+                },
+                "6": {
+                    "desc": "Trace Logic : Scom Satellite Error - Trace0"
+                },
+                "7": {
+                    "desc": "Trace Logic : Scom Satellite Error - Trace1"
+                },
+                "8": {
+                    "desc": "PIB2GIF parity error on FSM or Registers"
+                },
+                "9": {
+                    "desc": "MSG access PCB error"
+                },
+                "10:18": {
+                    "desc": "unused"
+                },
+                "19": {
+                    "desc": "DLL IRQ"
+                },
+                "20": {
+                    "desc": "Watchdog timer interrupt"
+                },
+                "21": {
+                    "desc": "internal temp sensor tripped a threshold"
+                },
+                "22": {
+                    "desc": "GPBC_FATAL_ERROR"
+                },
+                "23": {
+                    "desc": "GPBC_NON_FATAL_ERROR"
+                },
+                "24": {
+                    "desc": "early power off warning"
+                },
+                "25": {
+                    "desc": "TOP fatal interrupts"
+                },
+                "26": {
+                    "desc": "TOP non fatal interrupts"
+                },
+                "27:30": {
+                    "desc": "Interrupt from OPSe to OCMB"
+                },
+                "31": {
+                    "desc": "SerDes continuous calibration failure"
+                },
+                "32": {
+                    "desc": "Firmware Assert or CPU Exception"
+                },
+                "33": {
+                    "desc": "Extended error information ready"
+                },
+                "34": {
+                    "desc": "Interrupt from OPSe to OCMB"
+                },
+                "35": {
+                    "desc": "DDR thermal event"
+                },
+                "36": {
+                    "desc": "DDR4 PHY fatal"
+                },
+                "37": {
+                    "desc": "DDR4 PHY non fatal"
+                },
+                "38": {
+                    "desc": "DDR4 PHY interrupt"
+                },
+                "39": {
+                    "desc": "foxhound fatal lane 7"
+                },
+                "40": {
+                    "desc": "foxhound fatal lane 6"
+                },
+                "41": {
+                    "desc": "foxhound fatal lane 5"
+                },
+                "42": {
+                    "desc": "foxhound fatal lane 4"
+                },
+                "43": {
+                    "desc": "foxhound fatal lane 3"
+                },
+                "44": {
+                    "desc": "foxhound fatal lane 2"
+                },
+                "45": {
+                    "desc": "foxhound fatal lane 1"
+                },
+                "46": {
+                    "desc": "foxhound fatal lane 0"
+                },
+                "47:54": {
+                    "desc": "foxhound non fatal"
+                },
+                "55:62": {
+                    "desc": "foxhound serdes interrupt"
+                },
+                "63": {
+                    "desc": "GIF2PCB parity error on FSM or Registers"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "OCMB_LFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "OCMB_LFIR": [
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 1
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 2
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 3
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 4
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 5
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 6
+                }
+            },
+            {
+                "reg_name": "ADSP_PCBI",
+                "reg_inst": {
+                    "0": 7
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 1
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 2
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 3
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 4
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 5
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 6
+                }
+            },
+            {
+                "reg_name": "CSU_PCBI",
+                "reg_inst": {
+                    "0": 7
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_omi_dl_err_rpt.json b/chip_data/explorer/node_omi_dl_err_rpt.json
new file mode 100644
index 0000000..c2e38bf
--- /dev/null
+++ b/chip_data/explorer/node_omi_dl_err_rpt.json
@@ -0,0 +1,100 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "isolation_nodes": {
+        "OMI_DL_ERR_RPT": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_ERR_RPT"
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000000000FFF"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_ERR_RPT"
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000000000FFF"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_ERR_RPT"
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000000000FFF"
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "52": {
+                    "desc": "spare"
+                },
+                "53": {
+                    "desc": "spare"
+                },
+                "54": {
+                    "desc": "spare"
+                },
+                "55": {
+                    "desc": "RX receiving slow A"
+                },
+                "56": {
+                    "desc": "RX receiving illegal run length"
+                },
+                "57": {
+                    "desc": "control parity error"
+                },
+                "58": {
+                    "desc": "data parity error"
+                },
+                "59": {
+                    "desc": "truncated flit from TL"
+                },
+                "60": {
+                    "desc": "illegal run length from TL"
+                },
+                "61": {
+                    "desc": "Ack pointer overflow"
+                },
+                "62": {
+                    "desc": "UE on control flit replay buffer"
+                },
+                "63": {
+                    "desc": "UE on control flit frame buffer"
+                }
+            }
+        }
+    }
+}
diff --git a/chip_data/explorer/node_omi_dl_fir.json b/chip_data/explorer/node_omi_dl_fir.json
new file mode 100644
index 0000000..989a636
--- /dev/null
+++ b/chip_data/explorer/node_omi_dl_fir.json
@@ -0,0 +1,397 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "OMI_DL_FIR": {
+            "instances": {
+                "0": "0x08012800"
+            }
+        },
+        "OMI_DL_FIR_MASK": {
+            "instances": {
+                "0": "0x08012803"
+            }
+        },
+        "OMI_DL_FIR_ACT0": {
+            "instances": {
+                "0": "0x08012806"
+            }
+        },
+        "OMI_DL_FIR_ACT1": {
+            "instances": {
+                "0": "0x08012807"
+            }
+        },
+        "OMI_DL_FIR_WOF": {
+            "instances": {
+                "0": "0x08012808"
+            }
+        },
+        "CMN_CONFIG": {
+            "instances": {
+                "0": "0x0801280E"
+            }
+        },
+        "PMU_CNTR": {
+            "instances": {
+                "0": "0x0801280F"
+            }
+        },
+        "OMI_DL_CONFIG0": {
+            "instances": {
+                "0": "0x08012810"
+            }
+        },
+        "OMI_DL_CONFIG1": {
+            "instances": {
+                "0": "0x08012811"
+            }
+        },
+        "OMI_DL_ERR_MASK": {
+            "instances": {
+                "0": "0x08012812"
+            }
+        },
+        "OMI_DL_ERR_RPT": {
+            "instances": {
+                "0": "0x08012813"
+            }
+        },
+        "OMI_DL_ERR_CAPTURE": {
+            "instances": {
+                "0": "0x08012814"
+            }
+        },
+        "OMI_DL_EDPL_MAX_COUNT": {
+            "instances": {
+                "0": "0x08012815"
+            }
+        },
+        "OMI_DL_STATUS": {
+            "instances": {
+                "0": "0x08012816"
+            }
+        },
+        "OMI_DL_TRAINING_STATUS": {
+            "instances": {
+                "0": "0x08012817"
+            }
+        },
+        "OMI_DL_DLX_CONFIG": {
+            "instances": {
+                "0": "0x08012818"
+            }
+        },
+        "OMI_DL_DLX_INFO": {
+            "instances": {
+                "0": "0x08012819"
+            }
+        },
+        "OMI_DL_ERR_ACTION": {
+            "instances": {
+                "0": "0x0801281D"
+            }
+        },
+        "OMI_DL_DEBUG_AID": {
+            "instances": {
+                "0": "0x0801281E"
+            }
+        },
+        "OMI_DL_CYA_BITS": {
+            "instances": {
+                "0": "0x0801281F"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "OMI_DL_FIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_FIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_FIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_FIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_FIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "OMI_DL_FIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "OMI_DL_FIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "OMI-DL0 fatal error",
+                    "child_node": {
+                        "name": "OMI_DL_ERR_RPT",
+                        "inst": {
+                            "0": 0
+                        }
+                    }
+                },
+                "1": {
+                    "desc": "OMI-DL0 UE on data flit"
+                },
+                "2": {
+                    "desc": "OMI-DL0 CE on TL flit"
+                },
+                "3": {
+                    "desc": "OMI-DL0 detected a CRC error"
+                },
+                "4": {
+                    "desc": "OMI-DL0 received a nack"
+                },
+                "5": {
+                    "desc": "OMI-DL0 running in degraded mode"
+                },
+                "6": {
+                    "desc": "OMI-DL0 parity error detection on a lane"
+                },
+                "7": {
+                    "desc": "OMI-DL0 retrained due to no forward progress"
+                },
+                "8": {
+                    "desc": "OMI-DL0 remote side initiated a retrain"
+                },
+                "9": {
+                    "desc": "OMI-DL0 retrain due to internal error or software"
+                },
+                "10": {
+                    "desc": "OMI-DL0 threshold reached"
+                },
+                "11": {
+                    "desc": "OMI-DL0 trained"
+                },
+                "12": {
+                    "desc": "OMI-DL0 endpoint error bit 0"
+                },
+                "13": {
+                    "desc": "OMI-DL0 endpoint error bit 1"
+                },
+                "14": {
+                    "desc": "OMI-DL0 endpoint error bit 2"
+                },
+                "15": {
+                    "desc": "OMI-DL0 endpoint error bit 3"
+                },
+                "16": {
+                    "desc": "OMI-DL0 endpoint error bit 4"
+                },
+                "17": {
+                    "desc": "OMI-DL0 endpoint error bit 5"
+                },
+                "18": {
+                    "desc": "OMI-DL0 endpoint error bit 6"
+                },
+                "19": {
+                    "desc": "OMI-DL0 endpoint error bit 7"
+                },
+                "20:39": {
+                    "desc": "OMI-DL1"
+                },
+                "40:59": {
+                    "desc": "OMI-DL2"
+                },
+                "60": {
+                    "desc": "Performance monitor wrapped"
+                },
+                "61": {
+                    "desc": "reserved"
+                },
+                "62": {
+                    "desc": "LFIR internal parity error"
+                },
+                "63": {
+                    "desc": "SCOM Satellite Error"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "OMI_DL_FIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "OMI_DL_FIR": [
+            {
+                "reg_name": "CMN_CONFIG",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "PMU_CNTR",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_CONFIG0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_CONFIG1",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_ERR_MASK",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_ERR_RPT",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_ERR_CAPTURE",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_EDPL_MAX_COUNT",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_STATUS",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_TRAINING_STATUS",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_DLX_CONFIG",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_DLX_INFO",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_ERR_ACTION",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_DEBUG_AID",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "OMI_DL_CYA_BITS",
+                "reg_inst": {
+                    "0": 0
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_rdffir.json b/chip_data/explorer/node_rdffir.json
new file mode 100644
index 0000000..a597425
--- /dev/null
+++ b/chip_data/explorer/node_rdffir.json
@@ -0,0 +1,739 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "RDFFIR": {
+            "instances": {
+                "0": "0x08011C00"
+            }
+        },
+        "RDFFIR_MASK": {
+            "instances": {
+                "0": "0x08011C03"
+            }
+        },
+        "RDFFIR_ACT0": {
+            "instances": {
+                "0": "0x08011C06"
+            }
+        },
+        "RDFFIR_ACT1": {
+            "instances": {
+                "0": "0x08011C07"
+            }
+        },
+        "RDFFIR_WOF": {
+            "instances": {
+                "0": "0x08011C08"
+            }
+        },
+        "FARB0": {
+            "instances": {
+                "0": "0x08011415"
+            }
+        },
+        "MBSEC0": {
+            "instances": {
+                "0": "0x08011855"
+            }
+        },
+        "MBSEC1": {
+            "instances": {
+                "0": "0x08011856"
+            }
+        },
+        "MBSTR": {
+            "instances": {
+                "0": "0x08011857"
+            }
+        },
+        "MBSSYMEC": {
+            "instances": {
+                "0": "0x08011858",
+                "1": "0x08011859",
+                "2": "0x0801185A",
+                "3": "0x0801185B",
+                "4": "0x0801185C",
+                "5": "0x0801185D",
+                "6": "0x0801185E",
+                "7": "0x0801185F",
+                "8": "0x08011860"
+            }
+        },
+        "MBSMSEC": {
+            "instances": {
+                "0": "0x08011869"
+            }
+        },
+        "MBNCER": {
+            "instances": {
+                "0": "0x0801186A"
+            }
+        },
+        "MBRCER": {
+            "instances": {
+                "0": "0x0801186B"
+            }
+        },
+        "MBMPER": {
+            "instances": {
+                "0": "0x0801186C"
+            }
+        },
+        "MBUER": {
+            "instances": {
+                "0": "0x0801186D"
+            }
+        },
+        "MBAUER": {
+            "instances": {
+                "0": "0x0801186E"
+            }
+        },
+        "MC_ADDR_TRANS0": {
+            "instances": {
+                "0": "0x0801186F"
+            }
+        },
+        "MC_ADDR_TRANS1": {
+            "instances": {
+                "0": "0x08011870"
+            }
+        },
+        "MC_ADDR_TRANS2": {
+            "instances": {
+                "0": "0x08011871"
+            }
+        },
+        "MBSEVR0": {
+            "instances": {
+                "0": "0x0801187E"
+            }
+        },
+        "MCBAGRA": {
+            "instances": {
+                "0": "0x080118D6"
+            }
+        },
+        "MCBMCAT": {
+            "instances": {
+                "0": "0x080118D7"
+            }
+        },
+        "MCB_CNTL": {
+            "instances": {
+                "0": "0x080118DB"
+            }
+        },
+        "MCB_CNTLSTAT": {
+            "instances": {
+                "0": "0x080118DC"
+            }
+        },
+        "MCBCFG": {
+            "instances": {
+                "0": "0x080118E0"
+            }
+        },
+        "EXP_MSR": {
+            "instances": {
+                "0": "0x08011C0C"
+            }
+        },
+        "RDF_ERR_RPT_0": {
+            "instances": {
+                "0": "0x08011C0E"
+            }
+        },
+        "RDF_ERR_RPT_1": {
+            "instances": {
+                "0": "0x08011C0F"
+            }
+        },
+        "HW_MS": {
+            "instances": {
+                "0": "0x08011C10",
+                "1": "0x08011C11",
+                "2": "0x08011C12",
+                "3": "0x08011C13",
+                "4": "0x08011C14",
+                "5": "0x08011C15",
+                "6": "0x08011C16",
+                "7": "0x08011C17"
+            }
+        },
+        "FW_MS": {
+            "instances": {
+                "0": "0x08011C18",
+                "1": "0x08011C19",
+                "2": "0x08011C1A",
+                "3": "0x08011C1B",
+                "4": "0x08011C1C",
+                "5": "0x08011C1D",
+                "6": "0x08011C1E",
+                "7": "0x08011C1F"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "RDFFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "RDFFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "RDFFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "RDFFIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "RDFFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "RDFFIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "RDFFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "Mainline read MPE on rank 0"
+                },
+                "1": {
+                    "desc": "Mainline read MPE on rank 1"
+                },
+                "2": {
+                    "desc": "Mainline read MPE on rank 2"
+                },
+                "3": {
+                    "desc": "Mainline read MPE on rank 3"
+                },
+                "4": {
+                    "desc": "Mainline read MPE on rank 4"
+                },
+                "5": {
+                    "desc": "Mainline read MPE on rank 5"
+                },
+                "6": {
+                    "desc": "Mainline read MPE on rank 6"
+                },
+                "7": {
+                    "desc": "Mainline read MPE on rank 7"
+                },
+                "8": {
+                    "desc": "Mainline read NCE"
+                },
+                "9": {
+                    "desc": "Mainline read TCE"
+                },
+                "10": {
+                    "desc": "Mainline read SCE"
+                },
+                "11": {
+                    "desc": "Mainline read MCE"
+                },
+                "12": {
+                    "desc": "Mainline read SUE"
+                },
+                "13": {
+                    "desc": "Mainline read AUE"
+                },
+                "14": {
+                    "desc": "Mainline read UE"
+                },
+                "15": {
+                    "desc": "Mainline read RCD"
+                },
+                "16": {
+                    "desc": "Mainline read IAUE"
+                },
+                "17": {
+                    "desc": "Mainline read IUE"
+                },
+                "18": {
+                    "desc": "Mainline read IRCD"
+                },
+                "19": {
+                    "desc": "Mainline read IMPE"
+                },
+                "20": {
+                    "desc": "Maintenance MPE on rank 0"
+                },
+                "21": {
+                    "desc": "Maintenance MPE on rank 1"
+                },
+                "22": {
+                    "desc": "Maintenance MPE on rank 2"
+                },
+                "23": {
+                    "desc": "Maintenance MPE on rank 3"
+                },
+                "24": {
+                    "desc": "Maintenance MPE on rank 4"
+                },
+                "25": {
+                    "desc": "Maintenance MPE on rank 5"
+                },
+                "26": {
+                    "desc": "Maintenance MPE on rank 6"
+                },
+                "27": {
+                    "desc": "Maintenance MPE on rank 7"
+                },
+                "28": {
+                    "desc": "Maintenance NCE"
+                },
+                "29": {
+                    "desc": "Maintenance TCE"
+                },
+                "30": {
+                    "desc": "Maintenance SCE"
+                },
+                "31": {
+                    "desc": "Maintenance MCE"
+                },
+                "32": {
+                    "desc": "Maintenance SUE"
+                },
+                "33": {
+                    "desc": "Maintenance AUE"
+                },
+                "34": {
+                    "desc": "Maintenance UE"
+                },
+                "35": {
+                    "desc": "Maintenance RCD"
+                },
+                "36": {
+                    "desc": "Maintenance IAUE"
+                },
+                "37": {
+                    "desc": "Maintenance IUE"
+                },
+                "38": {
+                    "desc": "Maintenance IRCD"
+                },
+                "39": {
+                    "desc": "Maintenance IMPE"
+                },
+                "40": {
+                    "desc": "RDDATA valid error"
+                },
+                "41": {
+                    "desc": "SCOM status register parity error"
+                },
+                "42": {
+                    "desc": "SCOM recoverable register parity error"
+                },
+                "43": {
+                    "desc": "SCOM unrecoverable register parity error"
+                },
+                "44": {
+                    "desc": "ECC corrector internal parity error"
+                },
+                "45": {
+                    "desc": "Rd Buff ECC CHK Cor CE DW0 Detected"
+                },
+                "46": {
+                    "desc": "Rd Buff ECC CHK Cor CE DW1 Detected"
+                },
+                "47": {
+                    "desc": "Rd Buff ECC CHK Cor UE DW0 Detected"
+                },
+                "48": {
+                    "desc": "Rd Buff ECC CHK Cor UE DW1 Detected"
+                },
+                "49:59": {
+                    "desc": "Reserved"
+                },
+                "60": {
+                    "desc": "SCOM register parity error for debug/wat control"
+                },
+                "61": {
+                    "desc": "Reserved"
+                },
+                "62": {
+                    "desc": "Internal SCOM error"
+                },
+                "63": {
+                    "desc": "Internal SCOM error copy"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "RDFFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "RDFFIR": [
+            {
+                "reg_name": "FARB0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSEC0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSEC1",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSTR",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 1
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 2
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 3
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 4
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 5
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 6
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 7
+                }
+            },
+            {
+                "reg_name": "MBSSYMEC",
+                "reg_inst": {
+                    "0": 8
+                }
+            },
+            {
+                "reg_name": "MBSMSEC",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBNCER",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBRCER",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBMPER",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBUER",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBAUER",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MC_ADDR_TRANS0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MC_ADDR_TRANS1",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MC_ADDR_TRANS2",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MBSEVR0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCBAGRA",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCBMCAT",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCB_CNTL",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCB_CNTLSTAT",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "MCBCFG",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "EXP_MSR",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "RDF_ERR_RPT_0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "RDF_ERR_RPT_1",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 1
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 2
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 3
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 4
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 5
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 6
+                }
+            },
+            {
+                "reg_name": "HW_MS",
+                "reg_inst": {
+                    "0": 7
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 1
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 2
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 3
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 4
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 5
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 6
+                }
+            },
+            {
+                "reg_name": "FW_MS",
+                "reg_inst": {
+                    "0": 7
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_srqfir.json b/chip_data/explorer/node_srqfir.json
new file mode 100644
index 0000000..c3a3cc6
--- /dev/null
+++ b/chip_data/explorer/node_srqfir.json
@@ -0,0 +1,252 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "SRQFIR": {
+            "instances": {
+                "0": "0x08011400"
+            }
+        },
+        "SRQFIR_MASK": {
+            "instances": {
+                "0": "0x08011403"
+            }
+        },
+        "SRQFIR_ACT0": {
+            "instances": {
+                "0": "0x08011406"
+            }
+        },
+        "SRQFIR_ACT1": {
+            "instances": {
+                "0": "0x08011407"
+            }
+        },
+        "SRQFIR_WOF": {
+            "instances": {
+                "0": "0x08011408"
+            }
+        },
+        "SRQ_ERR_RPT": {
+            "instances": {
+                "0": "0x0801141C"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "SRQFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "SRQFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "SRQFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "SRQFIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "SRQFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "SRQFIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "SRQFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "SRQ recoverable error"
+                },
+                "1": {
+                    "desc": "SRQ nonrecoverable error"
+                },
+                "2": {
+                    "desc": "Refresh overrun"
+                },
+                "3": {
+                    "desc": "WAT error"
+                },
+                "4": {
+                    "desc": "RCD parity error"
+                },
+                "5": {
+                    "desc": "MCB logic error"
+                },
+                "6": {
+                    "desc": "Emergency throttle"
+                },
+                "7": {
+                    "desc": "NCF MCB parity error"
+                },
+                "8": {
+                    "desc": "DDR MBA event n"
+                },
+                "9": {
+                    "desc": "WRQ RRQ hang err"
+                },
+                "10": {
+                    "desc": "SM one hot error"
+                },
+                "11": {
+                    "desc": "Reg parity error"
+                },
+                "12": {
+                    "desc": "Cmd parity error"
+                },
+                "13": {
+                    "desc": "Port fail"
+                },
+                "14": {
+                    "desc": "informational register parity error bit"
+                },
+                "15": {
+                    "desc": "Debug parity error"
+                },
+                "16": {
+                    "desc": "WDF unrecoverable mainline error"
+                },
+                "17": {
+                    "desc": "WDF mmio error"
+                },
+                "18": {
+                    "desc": "WDF array UE on mainline operations (SUE put in mem)"
+                },
+                "19": {
+                    "desc": "WDF mainline dataflow error (SUE not reliably put in mem)"
+                },
+                "20": {
+                    "desc": "WDF scom register parity err, affecting mainline config"
+                },
+                "21": {
+                    "desc": "WDF scom register parity err, affecting scom ops only"
+                },
+                "22": {
+                    "desc": "WDF SCOM fsm parity error"
+                },
+                "23": {
+                    "desc": "WDF write buffer array CE"
+                },
+                "24": {
+                    "desc": "NCF UE"
+                },
+                "25": {
+                    "desc": "Firmware initiated channel fail"
+                },
+                "26": {
+                    "desc": "NCF logic error"
+                },
+                "27": {
+                    "desc": "NCF parity error"
+                },
+                "28": {
+                    "desc": "NCF correctable error"
+                },
+                "29": {
+                    "desc": "Internal scom error"
+                },
+                "30": {
+                    "desc": "Internal scom error copy"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "SRQFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "SRQFIR": [
+            {
+                "reg_name": "SRQ_ERR_RPT",
+                "reg_inst": {
+                    "0": 0
+                }
+            }
+        ]
+    }
+}
diff --git a/chip_data/explorer/node_tlx_err_rpt_1.json b/chip_data/explorer/node_tlx_err_rpt_1.json
new file mode 100644
index 0000000..423071e
--- /dev/null
+++ b/chip_data/explorer/node_tlx_err_rpt_1.json
@@ -0,0 +1,97 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "isolation_nodes": {
+        "TLX_ERR_RPT_1": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLX_ERR_RPT_1"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLX_ERR_RPT_1_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000005C00000"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLX_ERR_RPT_1"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLX_ERR_RPT_1_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000005C00000"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLX_ERR_RPT_1"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLX_ERR_RPT_1_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "int",
+                                "int_value": "0x0000000005C00000"
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "37": {
+                    "desc": "TLXT FIFO CE"
+                },
+                "39": {
+                    "desc": "Unexpected Interrupt Response"
+                },
+                "40": {
+                    "desc": "BDI Poisoned"
+                },
+                "41": {
+                    "desc": "TLXT Metadata UE"
+                }
+            }
+        }
+    }
+}
diff --git a/chip_data/explorer/node_tlxfir.json b/chip_data/explorer/node_tlxfir.json
new file mode 100644
index 0000000..56fb114
--- /dev/null
+++ b/chip_data/explorer/node_tlxfir.json
@@ -0,0 +1,301 @@
+{
+    "version": 1,
+    "model_ec": ["EXPLORER_11", "EXPLORER_20"],
+    "registers": {
+        "TLXFIR": {
+            "instances": {
+                "0": "0x08012400"
+            }
+        },
+        "TLXFIR_MASK": {
+            "instances": {
+                "0": "0x08012403"
+            }
+        },
+        "TLXFIR_ACT0": {
+            "instances": {
+                "0": "0x08012406"
+            }
+        },
+        "TLXFIR_ACT1": {
+            "instances": {
+                "0": "0x08012407"
+            }
+        },
+        "TLXFIR_WOF": {
+            "instances": {
+                "0": "0x08012408"
+            }
+        },
+        "TLX_ERR_RPT_0": {
+            "instances": {
+                "0": "0x0801241C"
+            }
+        },
+        "TLX_ERR_RPT_1": {
+            "instances": {
+                "0": "0x0801241D"
+            }
+        },
+        "TLX_ERR_RPT_2": {
+            "instances": {
+                "0": "0x0801241E"
+            }
+        },
+        "TLX_ERR_RPT_0_MASK": {
+            "instances": {
+                "0": "0x08012414"
+            }
+        },
+        "TLX_ERR_RPT_1_MASK": {
+            "instances": {
+                "0": "0x08012415"
+            }
+        },
+        "TLX_ERR_RPT_2_MASK": {
+            "instances": {
+                "0": "0x08012416"
+            }
+        }
+    },
+    "isolation_nodes": {
+        "TLXFIR": {
+            "instances": [0],
+            "rules": [
+                {
+                    "attn_type": ["CS"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLXFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["RE"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLXFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_ACT0"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLXFIR_ACT1"
+                            }
+                        ]
+                    }
+                },
+                {
+                    "attn_type": ["SPA"],
+                    "node_inst": [0],
+                    "expr": {
+                        "expr_type": "and",
+                        "exprs": [
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLXFIR"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_MASK"
+                                }
+                            },
+                            {
+                                "expr_type": "reg",
+                                "reg_name": "TLXFIR_ACT0"
+                            },
+                            {
+                                "expr_type": "not",
+                                "expr": {
+                                    "expr_type": "reg",
+                                    "reg_name": "TLXFIR_ACT1"
+                                }
+                            }
+                        ]
+                    }
+                }
+            ],
+            "bits": {
+                "0": {
+                    "desc": "Info reg parity error"
+                },
+                "1": {
+                    "desc": "Ctrl reg parity error"
+                },
+                "2": {
+                    "desc": "TLX VC0 return credit counter overflow"
+                },
+                "3": {
+                    "desc": "TLX VC1 return credit counter overflow"
+                },
+                "4": {
+                    "desc": "TLX dcp0 return credit counter overflow"
+                },
+                "5": {
+                    "desc": "TLX dcp1 return credit counter overflow"
+                },
+                "6": {
+                    "desc": "TLX credit management block error"
+                },
+                "7": {
+                    "desc": "TLX credit management block parity error"
+                },
+                "8": {
+                    "desc": "TLXT fatal parity error"
+                },
+                "9": {
+                    "desc": "TLXT recoverable error",
+                    "child_node": {
+                        "name": "TLX_ERR_RPT_1"
+                    }
+                },
+                "10": {
+                    "desc": "TLXT configuration error"
+                },
+                "11": {
+                    "desc": "TLXT informational parity error"
+                },
+                "12": {
+                    "desc": "TLXT hard error"
+                },
+                "13:15": {
+                    "desc": "Reserved"
+                },
+                "16": {
+                    "desc": "Corrupted pad mem pattern"
+                },
+                "17": {
+                    "desc": "Downstream OC parity error"
+                },
+                "18": {
+                    "desc": "OC malformed"
+                },
+                "19": {
+                    "desc": "OC protocol error"
+                },
+                "20": {
+                    "desc": "Address translate error"
+                },
+                "21": {
+                    "desc": "Metadata unc or data parity error"
+                },
+                "22": {
+                    "desc": "OC unsupported group 2"
+                },
+                "23": {
+                    "desc": "OC unsupported group 1"
+                },
+                "24": {
+                    "desc": "Bit flip control error"
+                },
+                "25": {
+                    "desc": "Control HW error"
+                },
+                "26": {
+                    "desc": "ECC corrected and others"
+                },
+                "27": {
+                    "desc": "Trace stop"
+                },
+                "28": {
+                    "desc": "Internal SCOM error"
+                },
+                "29": {
+                    "desc": "Internal SCOM error clone"
+                }
+            },
+            "capture_groups": [
+                {
+                    "group_name": "TLXFIR",
+                    "group_inst": {
+                        "0": 0
+                    }
+                }
+            ]
+        }
+    },
+    "capture_groups": {
+        "TLXFIR": [
+            {
+                "reg_name": "TLX_ERR_RPT_0",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "TLX_ERR_RPT_1",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "TLX_ERR_RPT_2",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "TLX_ERR_RPT_0_MASK",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "TLX_ERR_RPT_1_MASK",
+                "reg_inst": {
+                    "0": 0
+                }
+            },
+            {
+                "reg_name": "TLX_ERR_RPT_2_MASK",
+                "reg_inst": {
+                    "0": 0
+                }
+            }
+        ]
+    }
+}