Copied P10, Explorer, and Odyssey chip data from PRD project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I7d0b1571242fb2da9378bcbfa7c2f0541b8ac915
diff --git a/chip_data/odyssey/chip_odyssey.json b/chip_data/odyssey/chip_odyssey.json
new file mode 100644
index 0000000..4e8f3c0
--- /dev/null
+++ b/chip_data/odyssey/chip_odyssey.json
@@ -0,0 +1,22 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "root_nodes": {
+ "CS": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "RE": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "SPA": {
+ "name": "GFIR",
+ "inst": 0
+ },
+ "UCS": {
+ "name": "GFIR",
+ "inst": 0
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_cfir_mem.json b/chip_data/odyssey/node_cfir_mem.json
new file mode 100644
index 0000000..d8c38ca
--- /dev/null
+++ b/chip_data/odyssey/node_cfir_mem.json
@@ -0,0 +1,229 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "CFIR_MEM_CS": {
+ "instances": {
+ "0": "0x08040000"
+ }
+ },
+ "CFIR_MEM_RE": {
+ "instances": {
+ "0": "0x08040001"
+ }
+ },
+ "CFIR_MEM_SPA": {
+ "instances": {
+ "0": "0x08040002"
+ }
+ },
+ "CFIR_MEM_UCS": {
+ "instances": {
+ "0": "0x08040003"
+ }
+ },
+ "CFIR_MEM_CS_MASK": {
+ "instances": {
+ "0": "0x08040040"
+ }
+ },
+ "CFIR_MEM_RE_MASK": {
+ "instances": {
+ "0": "0x08040041"
+ }
+ },
+ "CFIR_MEM_SPA_MASK": {
+ "instances": {
+ "0": "0x08040042"
+ }
+ },
+ "CFIR_MEM_UCS_MASK": {
+ "instances": {
+ "0": "0x08040043"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_MEM": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_MEM_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from MEM_LOCAL_FIR",
+ "child_node": {
+ "name": "MEM_LOCAL_FIR"
+ }
+ },
+ "5": {
+ "desc": "Attention from DLX_FIR",
+ "child_node": {
+ "name": "DLX_FIR"
+ }
+ },
+ "6": {
+ "desc": "Attention from MCBIST_FIR",
+ "child_node": {
+ "name": "MCBIST_FIR"
+ }
+ },
+ "7": {
+ "desc": "Attention from MMIO_FIR",
+ "child_node": {
+ "name": "MMIO_FIR"
+ }
+ },
+ "8": {
+ "desc": "Attention from RDF_FIR 0",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "9": {
+ "desc": "Attention from RDF_FIR 1",
+ "child_node": {
+ "name": "RDF_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "10": {
+ "desc": "Attention from SRQ_FIR",
+ "child_node": {
+ "name": "SRQ_FIR"
+ }
+ },
+ "11": {
+ "desc": "Attention from TLX_FIR",
+ "child_node": {
+ "name": "TLX_FIR"
+ }
+ },
+ "12": {
+ "desc": "Attention from ODP_FIR 0",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "13": {
+ "desc": "Attention from ODP_FIR 1",
+ "child_node": {
+ "name": "ODP_FIR",
+ "inst": {
+ "0": 1
+ }
+ }
+ },
+ "14": {
+ "desc": "Attention from OCMB_PHY_FIR",
+ "child_node": {
+ "name": "OCMB_PHY_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_cfir_tp.json b/chip_data/odyssey/node_cfir_tp.json
new file mode 100644
index 0000000..eca635b
--- /dev/null
+++ b/chip_data/odyssey/node_cfir_tp.json
@@ -0,0 +1,157 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "CFIR_TP_CS": {
+ "instances": {
+ "0": "0x01040000"
+ }
+ },
+ "CFIR_TP_RE": {
+ "instances": {
+ "0": "0x01040001"
+ }
+ },
+ "CFIR_TP_SPA": {
+ "instances": {
+ "0": "0x01040002"
+ }
+ },
+ "CFIR_TP_UCS": {
+ "instances": {
+ "0": "0x01040003"
+ }
+ },
+ "CFIR_TP_CS_MASK": {
+ "instances": {
+ "0": "0x01040040"
+ }
+ },
+ "CFIR_TP_RE_MASK": {
+ "instances": {
+ "0": "0x01040041"
+ }
+ },
+ "CFIR_TP_SPA_MASK": {
+ "instances": {
+ "0": "0x01040042"
+ }
+ },
+ "CFIR_TP_UCS_MASK": {
+ "instances": {
+ "0": "0x01040043"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "CFIR_TP": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_CS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_RE_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_SPA_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "CFIR_TP_UCS_MASK"
+ }
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0FFFFFFFFFFFFFFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "4": {
+ "desc": "Attention from TP_LOCAL_FIR",
+ "child_node": {
+ "name": "TP_LOCAL_FIR"
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_dlx_err_rpt.json b/chip_data/odyssey/node_dlx_err_rpt.json
new file mode 100644
index 0000000..4554c54
--- /dev/null
+++ b/chip_data/odyssey/node_dlx_err_rpt.json
@@ -0,0 +1,123 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "isolation_nodes": {
+ "DLX_ERR_RPT": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_ERR_RPT"
+ },
+ {
+ "expr_type": "int",
+ "int_value": "0x0000000000003FFF"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "50": {
+ "desc": "buffer UE"
+ },
+ "51": {
+ "desc": "insufficient working lanes"
+ },
+ "52": {
+ "desc": "bad CRC from TLXT"
+ },
+ "53": {
+ "desc": "flit hammer"
+ },
+ "54": {
+ "desc": "TX lane reversal"
+ },
+ "55": {
+ "desc": "RX receiving slow A"
+ },
+ "56": {
+ "desc": "RX receiving illegal run length"
+ },
+ "57": {
+ "desc": "control parity error"
+ },
+ "58": {
+ "desc": "scom register parity error"
+ },
+ "59": {
+ "desc": "truncated flit from TL"
+ },
+ "60": {
+ "desc": "illegal run length from TL"
+ },
+ "61": {
+ "desc": "ack pointer overflow"
+ },
+ "62": {
+ "desc": "UE on bus from TLXT"
+ },
+ "63": {
+ "desc": "ECC UE on dword containing run length"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_dlx_fir.json b/chip_data/odyssey/node_dlx_fir.json
new file mode 100644
index 0000000..eaa5cbc
--- /dev/null
+++ b/chip_data/odyssey/node_dlx_fir.json
@@ -0,0 +1,429 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "DLX_FIR": {
+ "instances": {
+ "0": "0x08012400"
+ }
+ },
+ "DLX_FIR_MASK": {
+ "instances": {
+ "0": "0x08012402"
+ }
+ },
+ "DLX_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08012404"
+ }
+ },
+ "DLX_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08012405"
+ }
+ },
+ "DLX_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08012406"
+ }
+ },
+ "DLX_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08012407"
+ }
+ },
+ "DLX_FIR_WOF": {
+ "instances": {
+ "0": "0x08012408"
+ }
+ },
+ "CMN_CONFIG": {
+ "instances": {
+ "0": "0x0801240E"
+ }
+ },
+ "PMU_CNTR": {
+ "instances": {
+ "0": "0x0801240F"
+ }
+ },
+ "DLX_CONFIG0": {
+ "instances": {
+ "0": "0x08012410"
+ }
+ },
+ "DLX_CONFIG1": {
+ "instances": {
+ "0": "0x08012411"
+ }
+ },
+ "DLX_ERR_MASK": {
+ "instances": {
+ "0": "0x08012412"
+ }
+ },
+ "DLX_ERR_RPT": {
+ "instances": {
+ "0": "0x08012413"
+ }
+ },
+ "DLX_EDPL_MAX_COUNT": {
+ "instances": {
+ "0": "0x08012415"
+ }
+ },
+ "DLX_STATUS": {
+ "instances": {
+ "0": "0x08012416"
+ }
+ },
+ "DLX_TRAINING_STATUS": {
+ "instances": {
+ "0": "0x08012417"
+ }
+ },
+ "DLX_RMT_CONFIG": {
+ "instances": {
+ "0": "0x08012418"
+ }
+ },
+ "DLX_RMT_INFO": {
+ "instances": {
+ "0": "0x08012419"
+ }
+ },
+ "DLX_SKIT_CTL": {
+ "instances": {
+ "0": "0x0801241A"
+ }
+ },
+ "DLX_SKIT_STATUS": {
+ "instances": {
+ "0": "0x0801241B"
+ }
+ },
+ "DLX_CYA2": {
+ "instances": {
+ "0": "0x0801241C"
+ }
+ },
+ "DLX_ERR_ACTION": {
+ "instances": {
+ "0": "0x0801241D"
+ }
+ },
+ "DLX_DEBUG_AID": {
+ "instances": {
+ "0": "0x0801241E"
+ }
+ },
+ "DLX_CYA_BITS": {
+ "instances": {
+ "0": "0x0801241F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "DLX_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "DLX_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error in SCOM component"
+ },
+ "1": {
+ "desc": "DL0 fatal error",
+ "child_node": {
+ "name": "DLX_ERR_RPT",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "2": {
+ "desc": "DL0 buffer UE / insufficient working lanes",
+ "child_node": {
+ "name": "DLX_ERR_RPT",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "3": {
+ "desc": "DL0 CE on TL flit"
+ },
+ "4": {
+ "desc": "DL0 detected a CRC error"
+ },
+ "5": {
+ "desc": "DL0 received a nack"
+ },
+ "6": {
+ "desc": "DL0 running in degraded mode"
+ },
+ "7": {
+ "desc": "DL0 parity error detection on a lane"
+ },
+ "8": {
+ "desc": "DL0 retrained due to no forward progress"
+ },
+ "9": {
+ "desc": "DL0 remote side initiated a retrain"
+ },
+ "10": {
+ "desc": "DL0 retrain due to internal error or software"
+ },
+ "11": {
+ "desc": "DL0 threshold reached"
+ },
+ "12": {
+ "desc": "DL0 trained"
+ },
+ "13": {
+ "desc": "DL0 received replay flit with link_errors bit 0"
+ },
+ "14": {
+ "desc": "DL0 received replay flit with link_errors bit 1"
+ },
+ "15": {
+ "desc": "DL0 received replay flit with link_errors bit 2"
+ },
+ "16": {
+ "desc": "DL0 received replay flit with link_errors bit 3"
+ },
+ "17": {
+ "desc": "DL0 received replay flit with link_errors bit 4"
+ },
+ "18": {
+ "desc": "DL0 received replay flit with link_errors bit 5"
+ },
+ "19": {
+ "desc": "DL0 received replay flit with link_errors bit 6"
+ },
+ "20": {
+ "desc": "DL0 received replay flit with link_errors bit 7"
+ },
+ "21": {
+ "desc": "DL0 skitter error"
+ },
+ "22": {
+ "desc": "DL0 skitter drift detected"
+ },
+ "23:63": {
+ "desc": "reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "DLX_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "DLX_FIR": [
+ {
+ "reg_name": "CMN_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "PMU_CNTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CONFIG0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CONFIG1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_MASK",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_EDPL_MAX_COUNT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_TRAINING_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_RMT_CONFIG",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_RMT_INFO",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_SKIT_CTL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_SKIT_STATUS",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CYA2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_ERR_ACTION",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_DEBUG_AID",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "DLX_CYA_BITS",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_gfir.json b/chip_data/odyssey/node_gfir.json
new file mode 100644
index 0000000..86e36ca
--- /dev/null
+++ b/chip_data/odyssey/node_gfir.json
@@ -0,0 +1,85 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "GFIR_CS": {
+ "instances": {
+ "0": "0x570F001C"
+ }
+ },
+ "GFIR_RE": {
+ "instances": {
+ "0": "0x570F001B"
+ }
+ },
+ "GFIR_SPA": {
+ "instances": {
+ "0": "0x570F001A"
+ }
+ },
+ "GFIR_UCS": {
+ "instances": {
+ "0": "0x570F002A"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "GFIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_CS"
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_RE"
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_SPA"
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "GFIR_UCS"
+ }
+ }
+ ],
+ "bits": {
+ "1": {
+ "desc": "Attention from TP chiplet",
+ "child_node": {
+ "name": "CFIR_TP",
+ "inst": {
+ "0": 0
+ }
+ }
+ },
+ "8": {
+ "desc": "Attention from MEM chiplet",
+ "child_node": {
+ "name": "CFIR_MEM",
+ "inst": {
+ "0": 0
+ }
+ }
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_mcbist_fir.json b/chip_data/odyssey/node_mcbist_fir.json
new file mode 100644
index 0000000..0b50099
--- /dev/null
+++ b/chip_data/odyssey/node_mcbist_fir.json
@@ -0,0 +1,512 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MCBIST_FIR": {
+ "instances": {
+ "0": "0x08011400"
+ }
+ },
+ "MCBIST_FIR_MASK": {
+ "instances": {
+ "0": "0x08011402"
+ }
+ },
+ "MCBIST_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011404"
+ }
+ },
+ "MCBIST_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011405"
+ }
+ },
+ "MCBIST_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011406"
+ }
+ },
+ "MCBIST_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011407"
+ }
+ },
+ "MCBIST_FIR_WOF": {
+ "instances": {
+ "0": "0x08011408"
+ }
+ },
+ "MBSEC0": {
+ "instances": {
+ "0": "0x08011455"
+ }
+ },
+ "MBSEC1": {
+ "instances": {
+ "0": "0x08011456"
+ }
+ },
+ "MBSTR": {
+ "instances": {
+ "0": "0x08011457"
+ }
+ },
+ "MBSSYMEC0": {
+ "instances": {
+ "0": "0x08011458"
+ }
+ },
+ "MBSSYMEC1": {
+ "instances": {
+ "0": "0x08011459"
+ }
+ },
+ "MBSSYMEC2": {
+ "instances": {
+ "0": "0x0801145A"
+ }
+ },
+ "MBSSYMEC3": {
+ "instances": {
+ "0": "0x0801145B"
+ }
+ },
+ "MBSSYMEC4": {
+ "instances": {
+ "0": "0x0801145C"
+ }
+ },
+ "MBSSYMEC5": {
+ "instances": {
+ "0": "0x0801145D"
+ }
+ },
+ "MBSSYMEC6": {
+ "instances": {
+ "0": "0x0801145E"
+ }
+ },
+ "MBSSYMEC7": {
+ "instances": {
+ "0": "0x0801145F"
+ }
+ },
+ "MBSSYMEC8": {
+ "instances": {
+ "0": "0x08011460"
+ }
+ },
+ "MBSSYMEC9": {
+ "instances": {
+ "0": "0x08011461"
+ }
+ },
+ "MBSMSEC": {
+ "instances": {
+ "0": "0x08011469"
+ }
+ },
+ "MBNCER": {
+ "instances": {
+ "0": "0x0801146A"
+ }
+ },
+ "MBRCER": {
+ "instances": {
+ "0": "0x0801146B"
+ }
+ },
+ "MBMPER": {
+ "instances": {
+ "0": "0x0801146C"
+ }
+ },
+ "MBUER": {
+ "instances": {
+ "0": "0x0801146D"
+ }
+ },
+ "MBAUER": {
+ "instances": {
+ "0": "0x0801146E"
+ }
+ },
+ "MBA_ERR_MASK_0": {
+ "instances": {
+ "0": "0x08011473"
+ }
+ },
+ "MBA_ERR_MASK_1": {
+ "instances": {
+ "0": "0x08011474"
+ }
+ },
+ "MBSEVR0": {
+ "instances": {
+ "0": "0x0801147E"
+ }
+ },
+ "MCBAGRA": {
+ "instances": {
+ "0": "0x080114D6"
+ }
+ },
+ "MCBMCAT": {
+ "instances": {
+ "0": "0x080114D7"
+ }
+ },
+ "MCB_CNTL": {
+ "instances": {
+ "0": "0x080114DB"
+ }
+ },
+ "MCB_CNTLSTAT": {
+ "instances": {
+ "0": "0x080114DC"
+ }
+ },
+ "MCBCFG": {
+ "instances": {
+ "0": "0x080114E0"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MCBIST_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MCBIST_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error in scom component"
+ },
+ "1": {
+ "desc": "Invalid maint address"
+ },
+ "2": {
+ "desc": "Command address timeout"
+ },
+ "3": {
+ "desc": "Internal FSM error"
+ },
+ "4": {
+ "desc": "CSS Array uncorrected CE or UE"
+ },
+ "5": {
+ "desc": "MCBIST data error"
+ },
+ "6": {
+ "desc": "Hard NCE ETE attn"
+ },
+ "7": {
+ "desc": "Soft NCE ETE attn"
+ },
+ "8": {
+ "desc": "Int NCE ETE attn"
+ },
+ "9": {
+ "desc": "IUE ETE attn"
+ },
+ "10": {
+ "desc": "ICE (IMPE) ETE attn"
+ },
+ "11": {
+ "desc": "MCBIST program complete"
+ },
+ "12": {
+ "desc": "MCBIST CCS subtest done"
+ },
+ "13": {
+ "desc": "WAT debug bus attn"
+ },
+ "14": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "15": {
+ "desc": "SCOM fatal reg parity error"
+ },
+ "16": {
+ "desc": "SCOM WAT and debug reg parity error"
+ },
+ "17": {
+ "desc": "IAUE ETE attn"
+ },
+ "18": {
+ "desc": "IRCD ETE attn"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MCBIST_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MCBIST_FIR": [
+ {
+ "reg_name": "MBSEC0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEC1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSTR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC4",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC5",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC6",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC7",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC8",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSSYMEC9",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSMSEC",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBNCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBRCER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBMPER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBA_ERR_MASK_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBA_ERR_MASK_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBAUER",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBSEVR0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBAGRA",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBMCAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTL",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCB_CNTLSTAT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MCBCFG",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_mem_local_fir.json b/chip_data/odyssey/node_mem_local_fir.json
new file mode 100644
index 0000000..78fba62
--- /dev/null
+++ b/chip_data/odyssey/node_mem_local_fir.json
@@ -0,0 +1,185 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MEM_LOCAL_FIR": {
+ "instances": {
+ "0": "0x08040100"
+ }
+ },
+ "MEM_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x08040102"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08040104"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08040105"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08040106"
+ }
+ },
+ "MEM_LOCAL_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08040107"
+ }
+ },
+ "MEM_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x08040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MEM_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MEM_LOCAL_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR/LFIR parity error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - clock control error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM Access Error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - various errors"
+ },
+ "7": {
+ "desc": "DBG - SCOM parity fail"
+ },
+ "8": {
+ "desc": "unused"
+ },
+ "9": {
+ "desc": "unused"
+ },
+ "10": {
+ "desc": "Trace00 - SCOM parity error"
+ },
+ "11:62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "external local checkstop"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_mmio_fir.json b/chip_data/odyssey/node_mmio_fir.json
new file mode 100644
index 0000000..138e08c
--- /dev/null
+++ b/chip_data/odyssey/node_mmio_fir.json
@@ -0,0 +1,219 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "MMIO_FIR": {
+ "instances": {
+ "0": "0x08010870"
+ }
+ },
+ "MMIO_FIR_MASK": {
+ "instances": {
+ "0": "0x08010872"
+ }
+ },
+ "MMIO_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08010874"
+ }
+ },
+ "MMIO_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08010875"
+ }
+ },
+ "MMIO_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08010876"
+ }
+ },
+ "MMIO_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08010877"
+ }
+ },
+ "MMIO_FIR_WOF": {
+ "instances": {
+ "0": "0x08010878"
+ }
+ },
+ "MMIO_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801087C"
+ }
+ },
+ "MMIO_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801087E"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "MMIO_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "MMIO_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Interal SCOM logic parity error"
+ },
+ "1": {
+ "desc": "Attempt to access an unimplemented address in the AFU descriptor"
+ },
+ "2": {
+ "desc": "Error detected during MMIO inband or senor cache access"
+ },
+ "3": {
+ "desc": "Parity error in SCOM satellite component FSM"
+ },
+ "4": {
+ "desc": "Parity error in MMIO/CFG logic FSM"
+ },
+ "5": {
+ "desc": "Overflow detected in internal MMIO/CFG logic FIFO"
+ },
+ "6": {
+ "desc": "Fatal parity error detected in control register"
+ },
+ "7": {
+ "desc": "Parity error detected in informational register"
+ },
+ "8": {
+ "desc": "Both start signals asserted to Sensor cache logic"
+ },
+ "9": {
+ "desc": "Multiple parity errors on data from sequencer to sensor cache logic"
+ },
+ "10": {
+ "desc": "State machine parity error in sensor cache logic"
+ },
+ "11": {
+ "desc": "Sensor cache register parity error"
+ },
+ "12": {
+ "desc": "acTAG PASID config error"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "MMIO_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "MMIO_FIR": [
+ {
+ "reg_name": "MMIO_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MMIO_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_ocmb_phy_fir.json b/chip_data/odyssey/node_ocmb_phy_fir.json
new file mode 100644
index 0000000..baa4df3
--- /dev/null
+++ b/chip_data/odyssey/node_ocmb_phy_fir.json
@@ -0,0 +1,236 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "OCMB_PHY_FIR": {
+ "instances": {
+ "0": "0x08010C00"
+ }
+ },
+ "OCMB_PHY_FIR_MASK": {
+ "instances": {
+ "0": "0x08010C02"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08010C04"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08010C05"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08010C06"
+ }
+ },
+ "OCMB_PHY_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08010C07"
+ }
+ },
+ "OCMB_PHY_FIR_WOF": {
+ "instances": {
+ "0": "0x08010C08"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "OCMB_PHY_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "OCMB_PHY_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "SCOM FSM or FIR register parity error"
+ },
+ "1": {
+ "desc": "RX state machine parity or mode register parity error (IOO0)"
+ },
+ "2": {
+ "desc": "reserved"
+ },
+ "3": {
+ "desc": "reserved"
+ },
+ "4": {
+ "desc": "reserved"
+ },
+ "5": {
+ "desc": "TX state machine parity or mode register parity error (IOO0)"
+ },
+ "6": {
+ "desc": "reserved"
+ },
+ "7": {
+ "desc": "reserved"
+ },
+ "8": {
+ "desc": "reserved"
+ },
+ "9": {
+ "desc": "reserved"
+ },
+ "10": {
+ "desc": "reserved"
+ },
+ "11": {
+ "desc": "reserved"
+ },
+ "12": {
+ "desc": "reserved"
+ },
+ "13": {
+ "desc": "PPE internal error"
+ },
+ "14": {
+ "desc": "PPE external error"
+ },
+ "15": {
+ "desc": "PPE Halt due to Watchdog or Interrupt"
+ },
+ "16": {
+ "desc": "PPE Halt due to Debug"
+ },
+ "17": {
+ "desc": "PPE Halted"
+ },
+ "18": {
+ "desc": "PPE Watchdog Timeout"
+ },
+ "19": {
+ "desc": "PPE Array Scrub was missed"
+ },
+ "20": {
+ "desc": "PPE Array uncorrectable error"
+ },
+ "21": {
+ "desc": "PPE Array correctable error"
+ },
+ "22": {
+ "desc": "PPE Code Recal Abort"
+ },
+ "23": {
+ "desc": "PPE Code Fatal Error"
+ },
+ "24": {
+ "desc": "PPE Code Bad Lane Warning"
+ },
+ "25": {
+ "desc": "PPE Code DFT Error"
+ },
+ "26": {
+ "desc": "PPE Code Recal Not Run"
+ },
+ "27": {
+ "desc": "PPE Code Thread Locked"
+ },
+ "28": {
+ "desc": "PPE Code Thread Active Time Exceeded"
+ },
+ "29": {
+ "desc": "reserved"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_odp_fir.json b/chip_data/odyssey/node_odp_fir.json
new file mode 100644
index 0000000..3ad5b8d
--- /dev/null
+++ b/chip_data/odyssey/node_odp_fir.json
@@ -0,0 +1,207 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "ODP_FIR": {
+ "instances": {
+ "0": "0x08013000",
+ "1": "0x08013400"
+ }
+ },
+ "ODP_FIR_MASK": {
+ "instances": {
+ "0": "0x08013002",
+ "1": "0x08013402"
+ }
+ },
+ "ODP_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08013004",
+ "1": "0x08013404"
+ }
+ },
+ "ODP_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08013005",
+ "1": "0x08013405"
+ }
+ },
+ "ODP_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08013006",
+ "1": "0x08013406"
+ }
+ },
+ "ODP_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08013007",
+ "1": "0x08013407"
+ }
+ },
+ "ODP_FIR_WOF": {
+ "instances": {
+ "0": "0x08013008",
+ "1": "0x08013408"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "ODP_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "ODP_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "SCOM2APB state machine parity error"
+ },
+ "2": {
+ "desc": "Write data parity error"
+ },
+ "3": {
+ "desc": "APB responder error"
+ },
+ "4": {
+ "desc": "ODPCTRL register parity error"
+ },
+ "5": {
+ "desc": "PHY error"
+ },
+ "6": {
+ "desc": "PHY Sticky Unlock Error"
+ },
+ "7": {
+ "desc": "Bsi Interrupt occurred"
+ },
+ "8": {
+ "desc": "ANIB Receive Error"
+ },
+ "9": {
+ "desc": "Parity Error (even parity) for D5ACSM Channel 1 Parity Error"
+ },
+ "10": {
+ "desc": "Parity Error (even parity) for D5ACSM Channel 0 Parity Error"
+ },
+ "11": {
+ "desc": "PHY RX FIFO Check Error"
+ },
+ "12": {
+ "desc": "PHY RX TX PPT Error"
+ },
+ "13": {
+ "desc": "PHY ECC Error ARC ECC Interrupt"
+ },
+ "14:18": {
+ "desc": "Reserved Firmware Interrupt"
+ },
+ "19": {
+ "desc": "PHY Training Failure Interrupt"
+ },
+ "20": {
+ "desc": "PHY Initialization Complete Interrupt"
+ },
+ "21": {
+ "desc": "PHY Training Complete Interrupt"
+ }
+ }
+ }
+ }
+}
diff --git a/chip_data/odyssey/node_rdf_fir.json b/chip_data/odyssey/node_rdf_fir.json
new file mode 100644
index 0000000..cd418aa
--- /dev/null
+++ b/chip_data/odyssey/node_rdf_fir.json
@@ -0,0 +1,590 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "RDF_FIR": {
+ "instances": {
+ "0": "0x08011800",
+ "1": "0x08012800"
+ }
+ },
+ "RDF_FIR_MASK": {
+ "instances": {
+ "0": "0x08011802",
+ "1": "0x08012802"
+ }
+ },
+ "RDF_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011804",
+ "1": "0x08012804"
+ }
+ },
+ "RDF_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011805",
+ "1": "0x08012805"
+ }
+ },
+ "RDF_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011806",
+ "1": "0x08012806"
+ }
+ },
+ "RDF_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011807",
+ "1": "0x08012807"
+ }
+ },
+ "RDF_FIR_WOF": {
+ "instances": {
+ "0": "0x08011808",
+ "1": "0x08012808"
+ }
+ },
+ "RDF_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801180E",
+ "1": "0x0801280E"
+ }
+ },
+ "RDF_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801180F",
+ "1": "0x0801280F"
+ }
+ },
+ "MSR": {
+ "instances": {
+ "0": "0x0801180C",
+ "1": "0x0801280C"
+ }
+ },
+ "HW_MS0": {
+ "instances": {
+ "0": "0x08011810",
+ "1": "0x08012810"
+ }
+ },
+ "HW_MS1": {
+ "instances": {
+ "0": "0x08011811",
+ "1": "0x08012811"
+ }
+ },
+ "HW_MS2": {
+ "instances": {
+ "0": "0x08011812",
+ "1": "0x08012812"
+ }
+ },
+ "HW_MS3": {
+ "instances": {
+ "0": "0x08011813",
+ "1": "0x08012813"
+ }
+ },
+ "HW_MS4": {
+ "instances": {
+ "0": "0x08011814",
+ "1": "0x08012814"
+ }
+ },
+ "HW_MS5": {
+ "instances": {
+ "0": "0x08011815",
+ "1": "0x08012815"
+ }
+ },
+ "HW_MS6": {
+ "instances": {
+ "0": "0x08011816",
+ "1": "0x08012816"
+ }
+ },
+ "HW_MS7": {
+ "instances": {
+ "0": "0x08011817",
+ "1": "0x08012817"
+ }
+ },
+ "FW_MS0": {
+ "instances": {
+ "0": "0x08011818",
+ "1": "0x08012818"
+ }
+ },
+ "FW_MS1": {
+ "instances": {
+ "0": "0x08011819",
+ "1": "0x08012819"
+ }
+ },
+ "FW_MS2": {
+ "instances": {
+ "0": "0x0801181A",
+ "1": "0x0801281A"
+ }
+ },
+ "FW_MS3": {
+ "instances": {
+ "0": "0x0801181B",
+ "1": "0x0801281B"
+ }
+ },
+ "FW_MS4": {
+ "instances": {
+ "0": "0x0801181C",
+ "1": "0x0801281C"
+ }
+ },
+ "FW_MS5": {
+ "instances": {
+ "0": "0x0801181D",
+ "1": "0x0801281D"
+ }
+ },
+ "FW_MS6": {
+ "instances": {
+ "0": "0x0801181E",
+ "1": "0x0801281E"
+ }
+ },
+ "FW_MS7": {
+ "instances": {
+ "0": "0x0801181F",
+ "1": "0x0801281F"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "RDF_FIR": {
+ "instances": [0, 1],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0, 1],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "RDF_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal SCOM error"
+ },
+ "1": {
+ "desc": "Mainline read MPE on rank 0"
+ },
+ "2": {
+ "desc": "Mainline read MPE on rank 1"
+ },
+ "3": {
+ "desc": "Mainline read MPE on rank 2"
+ },
+ "4": {
+ "desc": "Mainline read MPE on rank 3"
+ },
+ "5": {
+ "desc": "Mainline read MPE on rank 4"
+ },
+ "6": {
+ "desc": "Mainline read MPE on rank 5"
+ },
+ "7": {
+ "desc": "Mainline read MPE on rank 6"
+ },
+ "8": {
+ "desc": "Mainline read MPE on rank 7"
+ },
+ "9": {
+ "desc": "Mainline read NCE"
+ },
+ "10": {
+ "desc": "Mainline read TCE"
+ },
+ "11": {
+ "desc": "Mainline read SCE"
+ },
+ "12": {
+ "desc": "Mainline read MCE"
+ },
+ "13": {
+ "desc": "Mainline read SUE"
+ },
+ "14": {
+ "desc": "Mainline read AUE"
+ },
+ "15": {
+ "desc": "Mainline read UE"
+ },
+ "16": {
+ "desc": "Mainline read RCD"
+ },
+ "17": {
+ "desc": "Mainline read IAUE"
+ },
+ "18": {
+ "desc": "Mainline read IUE"
+ },
+ "19": {
+ "desc": "Mainline read IRCD"
+ },
+ "20": {
+ "desc": "Mainline read IMPE"
+ },
+ "21": {
+ "desc": "Maintenance MPE on rank 0"
+ },
+ "22": {
+ "desc": "Maintenance MPE on rank 1"
+ },
+ "23": {
+ "desc": "Maintenance MPE on rank 2"
+ },
+ "24": {
+ "desc": "Maintenance MPE on rank 3"
+ },
+ "25": {
+ "desc": "Maintenance MPE on rank 4"
+ },
+ "26": {
+ "desc": "Maintenance MPE on rank 5"
+ },
+ "27": {
+ "desc": "Maintenance MPE on rank 6"
+ },
+ "28": {
+ "desc": "Maintenance MPE on rank 7"
+ },
+ "29": {
+ "desc": "Maintenance NCE"
+ },
+ "30": {
+ "desc": "Maintenance TCE"
+ },
+ "31": {
+ "desc": "Maintenance SCE"
+ },
+ "32": {
+ "desc": "Maintenance MCE"
+ },
+ "33": {
+ "desc": "Maintenance SUE"
+ },
+ "34": {
+ "desc": "Maintenance AUE"
+ },
+ "35": {
+ "desc": "Maintenance UE"
+ },
+ "36": {
+ "desc": "Maintenance RCD"
+ },
+ "37": {
+ "desc": "Maintenance IAUE"
+ },
+ "38": {
+ "desc": "Maintenance IUE"
+ },
+ "39": {
+ "desc": "Maintenance IRCD"
+ },
+ "40": {
+ "desc": "Maintenance IMPE"
+ },
+ "41": {
+ "desc": "RDDATA valid error"
+ },
+ "42": {
+ "desc": "SCOM status register parity error"
+ },
+ "43": {
+ "desc": "SCOM recoverable register parity error"
+ },
+ "44": {
+ "desc": "SCOM unrecoverable register parity error"
+ },
+ "45": {
+ "desc": "ECC corrector internal parity error"
+ },
+ "46": {
+ "desc": "Read buffer ECC CHK Cor CE DW0 Detected"
+ },
+ "47": {
+ "desc": "Read buffer ECC CHK Cor CE DW1 Detected"
+ },
+ "48": {
+ "desc": "Read buffer ECC CHK Cor UE DW0 Detected"
+ },
+ "49": {
+ "desc": "Read buffer ECC CHK Cor UE DW1 Detected"
+ },
+ "50": {
+ "desc": "Prefetch buffer ECC CHK Cor CE DW0 Detected"
+ },
+ "51": {
+ "desc": "Prefetch buffer ECC CHK Cor CE DW1 Detected"
+ },
+ "52": {
+ "desc": "Prefetch buffer ECC CHK Cor UE DW0 Detected"
+ },
+ "53": {
+ "desc": "Prefetch buffer ECC CHK Cor UE DW1 Detected"
+ },
+ "54": {
+ "desc": "Parity error on TLXT to RDF read buffer interface"
+ },
+ "55": {
+ "desc": "Parity error on TLXT to RDF read prefetch interface"
+ },
+ "56:60": {
+ "desc": "reserved"
+ },
+ "61": {
+ "desc": "SCOM register parity error for debug/wat control"
+ },
+ "62": {
+ "desc": "Reserved"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "RDF_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "RDF_FIR": [
+ {
+ "reg_name": "RDF_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "RDF_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "MSR",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS3",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS4",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS5",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS6",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "HWMS7",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS0",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS1",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS2",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS3",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS4",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS5",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS6",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ },
+ {
+ "reg_name": "FWMS7",
+ "reg_inst": {
+ "0": 0,
+ "1": 1
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_srq_fir.json b/chip_data/odyssey/node_srq_fir.json
new file mode 100644
index 0000000..5be8898
--- /dev/null
+++ b/chip_data/odyssey/node_srq_fir.json
@@ -0,0 +1,373 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "SRQ_FIR": {
+ "instances": {
+ "0": "0x08011000"
+ }
+ },
+ "SRQ_FIR_MASK": {
+ "instances": {
+ "0": "0x08011002"
+ }
+ },
+ "SRQ_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08011004"
+ }
+ },
+ "SRQ_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08011005"
+ }
+ },
+ "SRQ_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08011006"
+ }
+ },
+ "SRQ_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08011007"
+ }
+ },
+ "SRQ_FIR_WOF": {
+ "instances": {
+ "0": "0x08011008"
+ }
+ },
+ "SRQ_ERR_RPT": {
+ "instances": {
+ "0": "0x0801101C"
+ }
+ },
+ "MBXLT0": {
+ "instances": {
+ "0": "0x08011012"
+ }
+ },
+ "MBXLT1": {
+ "instances": {
+ "0": "0x08011013"
+ }
+ },
+ "MBXLT2": {
+ "instances": {
+ "0": "0x08011014"
+ }
+ },
+ "MBXLT3": {
+ "instances": {
+ "0": "0x08011021"
+ }
+ },
+ "WESR": {
+ "instances": {
+ "0": "0x08011C06"
+ }
+ },
+ "SRQ_ERR_RPT_HOLD": {
+ "instances": {
+ "0": "0x08011C07"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "SRQ_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "SRQ_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "SRQ nonrecoverable parity error"
+ },
+ "2": {
+ "desc": "refresh overrun port0"
+ },
+ "3": {
+ "desc": "WAT error"
+ },
+ "4": {
+ "desc": "RCD parity error port0"
+ },
+ "5": {
+ "desc": "MCB control logic Error in NCF"
+ },
+ "6": {
+ "desc": "Emergency throttle engaged"
+ },
+ "7": {
+ "desc": "DSM errors port0"
+ },
+ "8": {
+ "desc": "event_n was active on the DDR interface port0"
+ },
+ "9": {
+ "desc": "WRQ or RRQ is in a hung state port0"
+ },
+ "10": {
+ "desc": "state machine one hot error port0"
+ },
+ "11": {
+ "desc": "ROQ errors port0"
+ },
+ "12": {
+ "desc": "Address parity error seen internal to sequencer on read or write command port0"
+ },
+ "13": {
+ "desc": "port0 has failed due to a persistent retry"
+ },
+ "14": {
+ "desc": "informational register parity error"
+ },
+ "15": {
+ "desc": "soft error reported from error report register"
+ },
+ "16": {
+ "desc": "WDF unrecoverable mainline error"
+ },
+ "17": {
+ "desc": "WDF mmio error"
+ },
+ "18": {
+ "desc": "WDF array UE on mainline operations (SUE put in mem)"
+ },
+ "19": {
+ "desc": "WDF mainline dataflow error (SUE not reliably put in mem)"
+ },
+ "20": {
+ "desc": "WDF scom register parity error, affecting mainline config"
+ },
+ "21": {
+ "desc": "WDF scom register parity error, affecting scom ops only"
+ },
+ "22": {
+ "desc": "WDF SCOM fsm parity error"
+ },
+ "23": {
+ "desc": "WDF write buffer array CE"
+ },
+ "24": {
+ "desc": "refresh management CE port0"
+ },
+ "25": {
+ "desc": "refresh management RAA counter UE port0"
+ },
+ "26": {
+ "desc": "NCF fifo error port0"
+ },
+ "27": {
+ "desc": "NCF fifo error port1"
+ },
+ "28": {
+ "desc": "memcntl cmd xstop"
+ },
+ "29": {
+ "desc": "SRQ recoverable parity error"
+ },
+ "30": {
+ "desc": "DFI error port0"
+ },
+ "31": {
+ "desc": "xlat addr error port0"
+ },
+ "32": {
+ "desc": "refresh overrun port1"
+ },
+ "33": {
+ "desc": "RCD parity error port1"
+ },
+ "34": {
+ "desc": "DFI error port1"
+ },
+ "35": {
+ "desc": "event_n was active on the DDR interface port1"
+ },
+ "36": {
+ "desc": "WRQ or RRQ is in a hung state port1"
+ },
+ "37": {
+ "desc": "state machine one hot error port1"
+ },
+ "38": {
+ "desc": "ROQ errors port1"
+ },
+ "39": {
+ "desc": "Address parity error seen internal to sequencer on read or write command port1"
+ },
+ "40": {
+ "desc": "port1 has failed due to a persistent retry"
+ },
+ "41": {
+ "desc": "refresh management CE port1"
+ },
+ "42": {
+ "desc": "refresh management RAA counter UE port1"
+ },
+ "43": {
+ "desc": "xlat addr error port1"
+ },
+ "44": {
+ "desc": "check on ccs in progress bit"
+ },
+ "45": {
+ "desc": "DSM errors port1"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "SRQ_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "SRQ_FIR": [
+ {
+ "reg_name": "SRQ_ERR_RPT",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "MBXLT3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "WESR",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "SRQ_ERR_RPT_HOLD",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_tlx_fir.json b/chip_data/odyssey/node_tlx_fir.json
new file mode 100644
index 0000000..67ccaad
--- /dev/null
+++ b/chip_data/odyssey/node_tlx_fir.json
@@ -0,0 +1,330 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "TLX_FIR": {
+ "instances": {
+ "0": "0x08012000"
+ }
+ },
+ "TLX_FIR_MASK": {
+ "instances": {
+ "0": "0x08012002"
+ }
+ },
+ "TLX_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x08012004"
+ }
+ },
+ "TLX_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x08012005"
+ }
+ },
+ "TLX_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x08012006"
+ }
+ },
+ "TLX_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x08012007"
+ }
+ },
+ "TLX_FIR_WOF": {
+ "instances": {
+ "0": "0x08012008"
+ }
+ },
+ "SRQ_ROQ_CTL_0": {
+ "instances": {
+ "0": "0x0801100F"
+ }
+ },
+ "TLX_CFG_0": {
+ "instances": {
+ "0": "0x0801200C"
+ }
+ },
+ "TLX_CFG_1": {
+ "instances": {
+ "0": "0x0801200D"
+ }
+ },
+ "TLX_CFG_2": {
+ "instances": {
+ "0": "0x0801200E"
+ }
+ },
+ "TLX_CFG_3": {
+ "instances": {
+ "0": "0x0801200F"
+ }
+ },
+ "TLX_ERR_RPT_0": {
+ "instances": {
+ "0": "0x0801201C"
+ }
+ },
+ "TLX_ERR_RPT_1": {
+ "instances": {
+ "0": "0x0801201D"
+ }
+ },
+ "TLX_ERR_RPT_2": {
+ "instances": {
+ "0": "0x0801201E"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TLX_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TLX_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "Internal parity error"
+ },
+ "1": {
+ "desc": "TLXT control register parity error"
+ },
+ "2": {
+ "desc": "TLX VC0 return credit overflow"
+ },
+ "3": {
+ "desc": "TLX VC3 return credit overflow"
+ },
+ "4": {
+ "desc": "TLX DCP0 return credit overflow"
+ },
+ "5": {
+ "desc": "TLX DCP3 return credit overflow"
+ },
+ "6": {
+ "desc": "TLXC error"
+ },
+ "7": {
+ "desc": "TLXC parity error"
+ },
+ "8": {
+ "desc": "TLXT config parity error"
+ },
+ "9": {
+ "desc": "TLXT response parity error"
+ },
+ "10": {
+ "desc": "TLXT framer control parity error"
+ },
+ "11": {
+ "desc": "TLXT Xarb control error"
+ },
+ "12": {
+ "desc": "TLXT DLX interface error"
+ },
+ "13": {
+ "desc": "TLX info register parity error"
+ },
+ "14": {
+ "desc": "TLX reorder queue error"
+ },
+ "15": {
+ "desc": "TLXT invalid configuration"
+ },
+ "16": {
+ "desc": "TLXR is dropping commands after a fatal error"
+ },
+ "17": {
+ "desc": "Malformed OC packet received"
+ },
+ "18": {
+ "desc": "Protocol error detected in OC downstream sequence"
+ },
+ "19": {
+ "desc": "Legal OC command not supported"
+ },
+ "20": {
+ "desc": "Legal OC command length not supported"
+ },
+ "21": {
+ "desc": "TLXR OC Misaligned"
+ },
+ "22": {
+ "desc": "MMIO returned non-zero response to a write"
+ },
+ "23": {
+ "desc": "Hardware error in TLXR control logic"
+ },
+ "24": {
+ "desc": "TLXR Info Event"
+ },
+ "25": {
+ "desc": "TLXR detected internal error"
+ },
+ "26": {
+ "desc": "TLXR Threshold errors"
+ },
+ "27": {
+ "desc": "Trace_Stop from TLXR"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "TLX_FIR",
+ "group_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+ },
+ "capture_groups": {
+ "TLX_FIR": [
+ {
+ "reg_name": "SRQ_ROQ_CTL_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_2",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_CFG_3",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_0",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_1",
+ "reg_inst": {
+ "0": 0
+ }
+ },
+ {
+ "reg_name": "TLX_ERR_RPT_2",
+ "reg_inst": {
+ "0": 0
+ }
+ }
+ ]
+ }
+}
diff --git a/chip_data/odyssey/node_tp_local_fir.json b/chip_data/odyssey/node_tp_local_fir.json
new file mode 100644
index 0000000..55c5ea8
--- /dev/null
+++ b/chip_data/odyssey/node_tp_local_fir.json
@@ -0,0 +1,251 @@
+{
+ "version": 1,
+ "model_ec": ["ODYSSEY_10"],
+ "registers": {
+ "TP_LOCAL_FIR": {
+ "instances": {
+ "0": "0x01040100"
+ }
+ },
+ "TP_LOCAL_FIR_MASK": {
+ "instances": {
+ "0": "0x01040102"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_XSTOP": {
+ "instances": {
+ "0": "0x01040104"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_RECOV": {
+ "instances": {
+ "0": "0x01040105"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_ATTN": {
+ "instances": {
+ "0": "0x01040106"
+ }
+ },
+ "TP_LOCAL_FIR_CFG_LXSTOP": {
+ "instances": {
+ "0": "0x01040107"
+ }
+ },
+ "TP_LOCAL_FIR_WOF": {
+ "instances": {
+ "0": "0x01040108"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "TP_LOCAL_FIR": {
+ "instances": [0],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_XSTOP"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_RECOV"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["SPA"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_ATTN"
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["UCS"],
+ "node_inst": [0],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "TP_LOCAL_FIR_CFG_LXSTOP"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "CFIR/LFIR parity error"
+ },
+ "1": {
+ "desc": "CPLT_CTRL - PCB access error"
+ },
+ "2": {
+ "desc": "CC - PCB access error"
+ },
+ "3": {
+ "desc": "CC - clock control error"
+ },
+ "4": {
+ "desc": "PSC - PSCOM Access Error"
+ },
+ "5": {
+ "desc": "PSC - internal or ring interface error"
+ },
+ "6": {
+ "desc": "THERM - various errors"
+ },
+ "7": {
+ "desc": "DBG - SCOM parity fail"
+ },
+ "8": {
+ "desc": "unused"
+ },
+ "9": {
+ "desc": "FSI errors (OTP, I2C)"
+ },
+ "10": {
+ "desc": "Trace00 - SCOM parity error"
+ },
+ "11": {
+ "desc": "ITR - FMU error"
+ },
+ "12": {
+ "desc": "ITR - PCB error"
+ },
+ "13": {
+ "desc": "PCB master - timeout"
+ },
+ "14": {
+ "desc": "I2CM - parity errors"
+ },
+ "15:17": {
+ "desc": "unused"
+ },
+ "18": {
+ "desc": "Error reported from one or more PCB responder - PLL lock/unlock"
+ },
+ "19": {
+ "desc": "SBE - PPE internal hardware error"
+ },
+ "20": {
+ "desc": "SBE - PPE external hardware error"
+ },
+ "21": {
+ "desc": "SBE - PPE code error"
+ },
+ "22": {
+ "desc": "SBE - PPE debug code breakpoint"
+ },
+ "23": {
+ "desc": "SBE - PPE in halted state"
+ },
+ "24": {
+ "desc": "SBE - PPE watchdog timeout"
+ },
+ "25:26": {
+ "desc": "SBE - unused"
+ },
+ "27": {
+ "desc": "SBE - PPE triggers DBG"
+ },
+ "28:29": {
+ "desc": "unused"
+ },
+ "30": {
+ "desc": "PCB controller - multicast group member count underrun"
+ },
+ "31": {
+ "desc": "PCB controller - parity error"
+ },
+ "32:35": {
+ "desc": "unused"
+ },
+ "36": {
+ "desc": "PIBMEM"
+ },
+ "37": {
+ "desc": "PIBMEM"
+ },
+ "38:44": {
+ "desc": "unused"
+ },
+ "45": {
+ "desc": "SPI controller 0 error"
+ },
+ "46:62": {
+ "desc": "unused"
+ },
+ "63": {
+ "desc": "external local checkstop"
+ }
+ }
+ }
+ }
+}