Copied P10, Explorer, and Odyssey chip data from PRD project
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I7d0b1571242fb2da9378bcbfa7c2f0541b8ac915
diff --git a/chip_data/p10_10/node_eq_l3_fir.json b/chip_data/p10_10/node_eq_l3_fir.json
new file mode 100644
index 0000000..35ca70e
--- /dev/null
+++ b/chip_data/p10_10/node_eq_l3_fir.json
@@ -0,0 +1,373 @@
+{
+ "version": 1,
+ "model_ec": ["P10_10"],
+ "registers": {
+ "EQ_L3_FIR": {
+ "instances": {
+ "0": "0x20018600",
+ "1": "0x20014600",
+ "2": "0x20012600",
+ "3": "0x20011600",
+ "4": "0x21018600",
+ "5": "0x21014600",
+ "6": "0x21012600",
+ "7": "0x21011600",
+ "8": "0x22018600",
+ "9": "0x22014600",
+ "10": "0x22012600",
+ "11": "0x22011600",
+ "12": "0x23018600",
+ "13": "0x23014600",
+ "14": "0x23012600",
+ "15": "0x23011600",
+ "16": "0x24018600",
+ "17": "0x24014600",
+ "18": "0x24012600",
+ "19": "0x24011600",
+ "20": "0x25018600",
+ "21": "0x25014600",
+ "22": "0x25012600",
+ "23": "0x25011600",
+ "24": "0x26018600",
+ "25": "0x26014600",
+ "26": "0x26012600",
+ "27": "0x26011600",
+ "28": "0x27018600",
+ "29": "0x27014600",
+ "30": "0x27012600",
+ "31": "0x27011600"
+ }
+ },
+ "EQ_L3_FIR_MASK": {
+ "instances": {
+ "0": "0x20018603",
+ "1": "0x20014603",
+ "2": "0x20012603",
+ "3": "0x20011603",
+ "4": "0x21018603",
+ "5": "0x21014603",
+ "6": "0x21012603",
+ "7": "0x21011603",
+ "8": "0x22018603",
+ "9": "0x22014603",
+ "10": "0x22012603",
+ "11": "0x22011603",
+ "12": "0x23018603",
+ "13": "0x23014603",
+ "14": "0x23012603",
+ "15": "0x23011603",
+ "16": "0x24018603",
+ "17": "0x24014603",
+ "18": "0x24012603",
+ "19": "0x24011603",
+ "20": "0x25018603",
+ "21": "0x25014603",
+ "22": "0x25012603",
+ "23": "0x25011603",
+ "24": "0x26018603",
+ "25": "0x26014603",
+ "26": "0x26012603",
+ "27": "0x26011603",
+ "28": "0x27018603",
+ "29": "0x27014603",
+ "30": "0x27012603",
+ "31": "0x27011603"
+ }
+ },
+ "EQ_L3_FIR_ACT0": {
+ "instances": {
+ "0": "0x20018606",
+ "1": "0x20014606",
+ "2": "0x20012606",
+ "3": "0x20011606",
+ "4": "0x21018606",
+ "5": "0x21014606",
+ "6": "0x21012606",
+ "7": "0x21011606",
+ "8": "0x22018606",
+ "9": "0x22014606",
+ "10": "0x22012606",
+ "11": "0x22011606",
+ "12": "0x23018606",
+ "13": "0x23014606",
+ "14": "0x23012606",
+ "15": "0x23011606",
+ "16": "0x24018606",
+ "17": "0x24014606",
+ "18": "0x24012606",
+ "19": "0x24011606",
+ "20": "0x25018606",
+ "21": "0x25014606",
+ "22": "0x25012606",
+ "23": "0x25011606",
+ "24": "0x26018606",
+ "25": "0x26014606",
+ "26": "0x26012606",
+ "27": "0x26011606",
+ "28": "0x27018606",
+ "29": "0x27014606",
+ "30": "0x27012606",
+ "31": "0x27011606"
+ }
+ },
+ "EQ_L3_FIR_ACT1": {
+ "instances": {
+ "0": "0x20018607",
+ "1": "0x20014607",
+ "2": "0x20012607",
+ "3": "0x20011607",
+ "4": "0x21018607",
+ "5": "0x21014607",
+ "6": "0x21012607",
+ "7": "0x21011607",
+ "8": "0x22018607",
+ "9": "0x22014607",
+ "10": "0x22012607",
+ "11": "0x22011607",
+ "12": "0x23018607",
+ "13": "0x23014607",
+ "14": "0x23012607",
+ "15": "0x23011607",
+ "16": "0x24018607",
+ "17": "0x24014607",
+ "18": "0x24012607",
+ "19": "0x24011607",
+ "20": "0x25018607",
+ "21": "0x25014607",
+ "22": "0x25012607",
+ "23": "0x25011607",
+ "24": "0x26018607",
+ "25": "0x26014607",
+ "26": "0x26012607",
+ "27": "0x26011607",
+ "28": "0x27018607",
+ "29": "0x27014607",
+ "30": "0x27012607",
+ "31": "0x27011607"
+ }
+ }
+ },
+ "isolation_nodes": {
+ "EQ_L3_FIR": {
+ "instances": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
+ 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31
+ ],
+ "rules": [
+ {
+ "attn_type": ["CS"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ }
+ ]
+ }
+ },
+ {
+ "attn_type": ["RE"],
+ "node_inst": [
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29,
+ 30, 31
+ ],
+ "expr": {
+ "expr_type": "and",
+ "exprs": [
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR"
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_MASK"
+ }
+ },
+ {
+ "expr_type": "not",
+ "expr": {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT0"
+ }
+ },
+ {
+ "expr_type": "reg",
+ "reg_name": "EQ_L3_FIR_ACT1"
+ }
+ ]
+ }
+ }
+ ],
+ "bits": {
+ "0": {
+ "desc": "No members available for a CGC"
+ },
+ "1": {
+ "desc": "L3 attempted to master a CP (Castout/Push) command"
+ },
+ "2": {
+ "desc": "Access attempted to use invalid topology table entry"
+ },
+ "3": {
+ "desc": "L3 cache CE and UE within a short period"
+ },
+ "4": {
+ "desc": "CE detected on L3 cache read"
+ },
+ "5": {
+ "desc": "UE detected on L3 cache read"
+ },
+ "6": {
+ "desc": "SUE detected on L3 cache read"
+ },
+ "7": {
+ "desc": "L3 cache write data CE from Power Bus"
+ },
+ "8": {
+ "desc": "L3 cache write data UE from Power Bus"
+ },
+ "9": {
+ "desc": "L3 cache write data sue from Power Bus"
+ },
+ "10": {
+ "desc": "L3 cache write data CE from L2"
+ },
+ "11": {
+ "desc": "L3 cache write data UE from L2"
+ },
+ "12": {
+ "desc": "L3 cache write SUE from L2"
+ },
+ "13": {
+ "desc": "L3 DIR read CE"
+ },
+ "14": {
+ "desc": "L3 Dir read UE"
+ },
+ "15": {
+ "desc": "Dir error not found during corr seq"
+ },
+ "16": {
+ "desc": "Received addr_error cresp on Snoop Machine or Castout Operation"
+ },
+ "17": {
+ "desc": "Received addr_error cresp for Prefetch Operation"
+ },
+ "18": {
+ "desc": "L3_PB_HANG_POLL"
+ },
+ "19": {
+ "desc": "Invalid LRU count error"
+ },
+ "20": {
+ "desc": "Reserved"
+ },
+ "21": {
+ "desc": "Reserved"
+ },
+ "22": {
+ "desc": "Reserved"
+ },
+ "23": {
+ "desc": "Prefetch or Write Inject machine PowerBus data hang check"
+ },
+ "24": {
+ "desc": "L3 Hw control err"
+ },
+ "25": {
+ "desc": "Cache inhibited op in L3 directory"
+ },
+ "26": {
+ "desc": "L3 line delete CE done"
+ },
+ "27": {
+ "desc": "L3 snooped an incoming LCO"
+ },
+ "28": {
+ "desc": "LRU intended to victimize a line, but invalid line selected"
+ },
+ "29": {
+ "desc": "L3 cache congruence class deleted"
+ },
+ "30": {
+ "desc": "Incoming LCO ID mismatch"
+ },
+ "31": {
+ "desc": "L3 PowerBus Master Write CRESP ack_dead"
+ },
+ "32": {
+ "desc": "PB Master Read received ack_dead CRESP"
+ }
+ },
+ "capture_groups": [
+ {
+ "group_name": "EQ_L3_FIR",
+ "group_inst": {
+ "0": 0,
+ "1": 1,
+ "2": 2,
+ "3": 3,
+ "4": 4,
+ "5": 5,
+ "6": 6,
+ "7": 7,
+ "8": 8,
+ "9": 9,
+ "10": 10,
+ "11": 11,
+ "12": 12,
+ "13": 13,
+ "14": 14,
+ "15": 15,
+ "16": 16,
+ "17": 17,
+ "18": 18,
+ "19": 19,
+ "20": 20,
+ "21": 21,
+ "22": 22,
+ "23": 23,
+ "24": 24,
+ "25": 25,
+ "26": 26,
+ "27": 27,
+ "28": 28,
+ "29": 29,
+ "30": 30,
+ "31": 31
+ }
+ }
+ ]
+ }
+ }
+}