Chip Data file updates for PAU, NMMU, and PCI FIRs
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: I3da92a838eb04532e6f78a1f1ad2d40b52ff01d3
diff --git a/xml/p10/node_nmmu_cq_fir.xml b/xml/p10/node_nmmu_cq_fir.xml
index 52837a7..e5bf5e8 100644
--- a/xml/p10/node_nmmu_cq_fir.xml
+++ b/xml/p10/node_nmmu_cq_fir.xml
@@ -7,6 +7,16 @@
<action attn_type="RE" config="01"/>
<action attn_type="UCS" config="11"/>
</local_fir>
+
+ <register name="NMMU_CQ_ERR_RPT_0">
+ <instance reg_inst="0" addr="0x02010C22" />
+ <instance reg_inst="1" addr="0x03010C22" />
+ </register>
+
+ <capture_group node_inst="0:1">
+ <capture_register reg_name="NMMU_CQ_ERR_RPT_0" reg_inst="0:1" />
+ </capture_group>
+
<bit pos="0">PBI internal parity error</bit>
<bit pos="1">PowerBus command hang error</bit>
<bit pos="2">PowerBus read address error</bit>
diff --git a/xml/p10/node_nmmu_fir.xml b/xml/p10/node_nmmu_fir.xml
index ff68bd9..9f9b0ad 100644
--- a/xml/p10/node_nmmu_fir.xml
+++ b/xml/p10/node_nmmu_fir.xml
@@ -7,50 +7,50 @@
<action attn_type="RE" config="01"/>
<action attn_type="UCS" config="11"/>
</local_fir>
- <bit pos="0">Fabric DIn xlat array CE error detected.</bit>
- <bit pos="1">Fabric DIn xlat array UE error detected.</bit>
- <bit pos="2">Fabric DIn xlat array SUE error detected.</bit>
- <bit pos="3">Fabric mst rd array CE error detected.</bit>
- <bit pos="4">Fabric mst rd array UE error detected.</bit>
- <bit pos="5">Fabric mst rd array SUE error detected.</bit>
- <bit pos="6">Fabric xlat protocol error detected.</bit>
- <bit pos="7">Fabric xlat op timeout detected.</bit>
- <bit pos="8">SLB directory parity error detected.</bit>
- <bit pos="9">SLB cache parity error detected.</bit>
- <bit pos="10">SLB lru parity error detected.</bit>
- <bit pos="11">SLB multi-hit error detected.</bit>
- <bit pos="12">TLB directory parity error detected.</bit>
- <bit pos="13">TLB cache parity error detected.</bit>
- <bit pos="14">TLB lru parity error detected.</bit>
- <bit pos="15">TLB multi-hit error detected.</bit>
- <bit pos="16">Segment fault detected .</bit>
- <bit pos="17">Page fault detected due to no matching pte.</bit>
- <bit pos="18">Page fault detected due to basic prot chk fail.</bit>
- <bit pos="19">Page fault detected due to virt prot chk fail.</bit>
- <bit pos="20">Page fault detected due to seid mismatch .</bit>
- <bit pos="21">Address error cresp detected by twsm for read .</bit>
- <bit pos="22">PTE update fail due to armwf mismatch.</bit>
- <bit pos="23">Address error cresp detected by twsm for write.</bit>
- <bit pos="24">Unsupported radix cfg for guest-side .</bit>
- <bit pos="25">Unsupported radix cfg for host-side .</bit>
- <bit pos="26">Invalid wimg setting detected .</bit>
- <bit pos="27">Invalid radix quad access detected .</bit>
- <bit pos="28">Unexpected access to foreign address space .</bit>
- <bit pos="29">Prefetch abort/fail detected .</bit>
- <bit pos="30">Context cache array parity error detected .</bit>
- <bit pos="31">Radix pwc array parity error detected .</bit>
- <bit pos="32">Tablewalk sm control error detected .</bit>
- <bit pos="33">Castout sm control error detected .</bit>
- <bit pos="34">Check-in sm control error detected .</bit>
- <bit pos="35">Invalidate sm control error detected .</bit>
- <bit pos="36">Tablewalk sm timeout error detected .</bit>
- <bit pos="37">Castout sm timeout error detected .</bit>
- <bit pos="38">Check-in sm timeout error detected .</bit>
- <bit pos="39">Invalidate sm timeout error detected .</bit>
- <bit pos="40">NX local checkstop error detected .</bit>
- <bit pos="41">CP0 local checkstop error detected .</bit>
- <bit pos="42">CP1 local checkstop error detected .</bit>
- <bit pos="43">NPU local checkstop error detected .</bit>
- <bit pos="44">FBC local checkstop error detected .</bit>
- <bit pos="45">FBC local checkstop error detected .</bit>
+ <bit pos="0">Fabric DIn xlat array CE error detected</bit>
+ <bit pos="1">Fabric DIn xlat array UE error detected</bit>
+ <bit pos="2">Fabric DIn xlat array SUE error detected</bit>
+ <bit pos="3">Fabric mst rd array CE error detected</bit>
+ <bit pos="4">Fabric mst rd array UE error detected</bit>
+ <bit pos="5">Fabric mst rd array SUE error detected</bit>
+ <bit pos="6">Fabric xlat protocol error detected</bit>
+ <bit pos="7">Fabric xlat op timeout detected</bit>
+ <bit pos="8">SLB directory parity error detected</bit>
+ <bit pos="9">SLB cache parity error detected</bit>
+ <bit pos="10">SLB lru parity error detected</bit>
+ <bit pos="11">SLB multi-hit error detected</bit>
+ <bit pos="12">TLB directory parity error detected</bit>
+ <bit pos="13">TLB cache parity error detected</bit>
+ <bit pos="14">TLB lru parity error detected</bit>
+ <bit pos="15">TLB multi-hit error detected</bit>
+ <bit pos="16">Segment fault detected</bit>
+ <bit pos="17">Page fault detected due to no matching pte</bit>
+ <bit pos="18">Page fault detected due to basic prot chk fail</bit>
+ <bit pos="19">Page fault detected due to virt prot chk fail</bit>
+ <bit pos="20">Page fault detected due to seid mismatch</bit>
+ <bit pos="21">Address error cresp detected by twsm for read</bit>
+ <bit pos="22">PTE update fail due to armwf mismatch</bit>
+ <bit pos="23">Address error cresp detected by twsm for write</bit>
+ <bit pos="24">Unsupported radix cfg for guest-side</bit>
+ <bit pos="25">Unsupported radix cfg for host-side</bit>
+ <bit pos="26">Invalid wimg setting detected</bit>
+ <bit pos="27">Invalid radix quad access detected</bit>
+ <bit pos="28">Unexpected access to foreign address space</bit>
+ <bit pos="29">Prefetch abort/fail detected</bit>
+ <bit pos="30">Context cache array parity error detected</bit>
+ <bit pos="31">Radix pwc array parity error detected</bit>
+ <bit pos="32">Tablewalk sm control error detected</bit>
+ <bit pos="33">Castout sm control error detected</bit>
+ <bit pos="34">Check-in sm control error detected</bit>
+ <bit pos="35">Invalidate sm control error detected</bit>
+ <bit pos="36">Tablewalk sm timeout error detected</bit>
+ <bit pos="37">Castout sm timeout error detected</bit>
+ <bit pos="38">Check-in sm timeout error detected</bit>
+ <bit pos="39">Invalidate sm timeout error detected</bit>
+ <bit pos="40">NX local checkstop error detected</bit>
+ <bit pos="41">CP0 local checkstop error detected</bit>
+ <bit pos="42">CP1 local checkstop error detected</bit>
+ <bit pos="43">NPU local checkstop error detected</bit>
+ <bit pos="44">FBC local checkstop error detected</bit>
+ <bit pos="45">FBC local checkstop error detected</bit>
</attn_node>
diff --git a/xml/p10/node_pau_fir_0.xml b/xml/p10/node_pau_fir_0.xml
index 0458b31..79adfec 100644
--- a/xml/p10/node_pau_fir_0.xml
+++ b/xml/p10/node_pau_fir_0.xml
@@ -16,39 +16,39 @@
<bit pos="2">NTL data array UE</bit>
<bit pos="3">NTL NVLInk Control/Header/AE Parity error</bit>
<bit pos="4">NTL NVLink Data Parity error</bit>
- <bit pos="5">NTL NVLink Malformed Packet (illegal Cmd encode, etc.)</bit>
- <bit pos="6">NTL NVLink Unsupported Packet (receiving DGD, receiving Atomic with unsupported DatLen, etc)</bit>
- <bit pos="7">NTL NVLink Config errors (Credits received > max configured)</bit>
+ <bit pos="5">NTL NVLink Malformed Packet</bit>
+ <bit pos="6">NTL NVLink Unsupported Packet</bit>
+ <bit pos="7">NTL NVLink Config errors</bit>
<bit pos="8">NTL NVLink CRC errors or LMD=Stomp</bit>
- <bit pos="9">NTL PRI errors (errors returned by NDL Wrapper on PRI interface)</bit>
- <bit pos="10">NTL logic error (overflow, underflow, etc)</bit>
+ <bit pos="9">NTL PRI errors</bit>
+ <bit pos="10">NTL logic error</bit>
<bit pos="11">NTL LMD=Data Poison</bit>
<bit pos="12">NTL data array SUE</bit>
<bit pos="13">CQ CTL/SM ASBE Array single-bit correctable error</bit>
- <bit pos="14">CQ CTL/SM PBR PowerBus Recoverable (ex: abort_trm CResp)</bit>
- <bit pos="15">CQ CTL/SM REG Register ring error (ie noack)</bit>
- <bit pos="16">CQ CTL/SM DUE Data Uncorrectable error for MMIO store data</bit>
- <bit pos="17">CQ CTL/SM UT=1 to frozen PE (for naples this was in AT as part of the PCT lookup).</bit>
- <bit pos="18">CQ CTL/SM NCF NVLink configuration error (ex: Probe missed its GPUBAR)</bit>
- <bit pos="19">CQ CTL/SM NVF NVLink fatal (ex: rcv data resp to write req)</bit>
- <bit pos="20">CQ CTL/SM OCR OpenCAPI Recoverable, Command failed (ex: SUE data to memory, a*_failed response to AFU, etc) and brick not fenced.</bit>
- <bit pos="21">CQ CTL/SM AUE Array uncorrectable error</bit>
- <bit pos="22">CQ CTL/SM PBP PowerBus parity error</bit>
- <bit pos="23">CQ CTL/SM PBF PowerBus Fatal (ex: addr_error CResp)</bit>
- <bit pos="24">CQ CTL/SM PBC PowerBus configuration error (ex: group > 3)</bit>
- <bit pos="25">CQ CTL/SM FWD Forward-Progress (internal timer or rpt_hang.data)</bit>
- <bit pos="26">CQ CTL/SM NLG PAU Logic error (ex: invalid state, missed table lookup, etc.)</bit>
- <bit pos="27">Cresp=Addr_Error received for a load command (PowerBus LD_cresp_addr_error)</bit>
- <bit pos="28">Cresp=Addr_Error received for a store command (PowerBus ST_cresp_addr_error)</bit>
- <bit pos="29">CQ DAT ECC UE on data/BE arrays. Relevant word is marked with SUE</bit>
+ <bit pos="14">CQ CTL/SM PBR PowerBus Recoverable</bit>
+ <bit pos="15">CQ CTL/SM REG Register ring error</bit>
+ <bit pos="16">CQ CTL/SM DUE Data Uncorrectable error for MMIO store data</bit>
+ <bit pos="17">CQ CTL/SM UT=1 to frozen PE</bit>
+ <bit pos="18">CQ CTL/SM NCF NVLink configuration error</bit>
+ <bit pos="19">CQ CTL/SM NVF NVLink fatal</bit>
+ <bit pos="20">CQ CTL/SM OCR OpenCAPI Recoverable, Command failed, and brick not fenced.</bit>
+ <bit pos="21">CQ CTL/SM AUE Array uncorrectable error</bit>
+ <bit pos="22">CQ CTL/SM PBP PowerBus parity error</bit>
+ <bit pos="23">CQ CTL/SM PBF PowerBus Fatal</bit>
+ <bit pos="24">CQ CTL/SM PBC PowerBus configuration error</bit>
+ <bit pos="25">CQ CTL/SM FWD Forward-Progress</bit>
+ <bit pos="26">CQ CTL/SM NLG PAU Logic error</bit>
+ <bit pos="27">Cresp=Addr_Error received for a load command</bit>
+ <bit pos="28">Cresp=Addr_Error received for a store command</bit>
+ <bit pos="29">CQ DAT ECC UE on data/BE arrays</bit>
<bit pos="30">CQ DAT ECC CE on data/BE arrays</bit>
- <bit pos="31">CQ DAT parity error on data/BE latches. Relevant word is marked with SUE</bit>
+ <bit pos="31">CQ DAT parity error on data/BE latches</bit>
<bit pos="32">CQ DAT parity errors on configuration registers</bit>
<bit pos="33">CQ DAT parity errors on received PowerBus rtag</bit>
<bit pos="34">CQ DAT parity errors on internal state latches</bit>
- <bit pos="35">CQ DAT logic error (invalid state bit patterns, credit overflow, etc.)</bit>
- <bit pos="36">CQ_DAT ECC SUE on data/BE arrays that can be due to poisoned data from GPU</bit>
- <bit pos="37">CQ_DAT ECC SUE on PB receive data (CANNOT be due to poisoned data from GPU)</bit>
+ <bit pos="35">CQ DAT logic error</bit>
+ <bit pos="36">CQ DAT ECC SUE on data/BE arrays</bit>
+ <bit pos="37">CQ DAT ECC SUE on PB receive data</bit>
<bit pos="38">CQ DAT Reserved, macro bit 9</bit>
<bit pos="39">CQ DAT Reserved, macro bit 10</bit>
<bit pos="40">XTS internal logic error</bit>
diff --git a/xml/p10/node_pau_fir_1.xml b/xml/p10/node_pau_fir_1.xml
index e8b9718..5ad3c95 100644
--- a/xml/p10/node_pau_fir_1.xml
+++ b/xml/p10/node_pau_fir_1.xml
@@ -23,13 +23,13 @@
<bit pos="9">NDL Brick4 nostall</bit>
<bit pos="10">NDL Brick5 stall</bit>
<bit pos="11">NDL Brick5 nostall</bit>
- <bit pos="12">MISC Register ring error (noack, >1 ack)</bit>
+ <bit pos="12">MISC Register ring error</bit>
<bit pos="13">MISC Parity error from interrupt base real address register</bit>
<bit pos="14">MISC Parity error on Indirect SCOM Address register</bit>
<bit pos="15">MISC Parity error on MISC Control register</bit>
<bit pos="16">FIR1 Reserved, bit 16</bit>
- <bit pos="17">ATS Invalid TVT entry (TCE Table Size = 0b00000)</bit>
- <bit pos="18">ATS TVT Address range error (no xlate: EA out of range; xlate: unused EA bits non-zero, TVE uses > max # EA bits)</bit>
+ <bit pos="17">ATS Invalid TVT entry</bit>
+ <bit pos="18">ATS TVT Address range error</bit>
<bit pos="19">ATS TCE Page access error during TCE cache lookup</bit>
<bit pos="20">ATS Effective Address hit multiple TCE cache entries</bit>
<bit pos="21">ATS TCE Page access error during TCE table-walk</bit>
@@ -38,7 +38,7 @@
<bit pos="24">ATS Parity error on TCE cache data array</bit>
<bit pos="25">ATS ECC UE on Effective Address array</bit>
<bit pos="26">ATS ECC CE on Effective Address array</bit>
- <bit pos="27">ATS ECC UE on TDRmem array (table-walk state machine also hangs)</bit>
+ <bit pos="27">ATS ECC UE on TDRmem array</bit>
<bit pos="28">ATS ECC CE on TDRmem array</bit>
<bit pos="29">ATS ECC UE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
<bit pos="30">ATS ECC CE on CQ CTL DMA Read data to TDR_mem array during table-walk</bit>
diff --git a/xml/p10/node_pau_fir_2.xml b/xml/p10/node_pau_fir_2.xml
index 12b0fbd..5f1790a 100644
--- a/xml/p10/node_pau_fir_2.xml
+++ b/xml/p10/node_pau_fir_2.xml
@@ -15,56 +15,56 @@
<bit pos="1">OTL Brick3 translation fault</bit>
<bit pos="2">OTL Brick4 translation fault</bit>
<bit pos="3">OTL Brick5 translation fault</bit>
- <bit pos="4">OTL TL credit counter overflow caused by return_tl_credits.</bit>
- <bit pos="5">OTL RX acTag specified in a command is outside the configured specification set.</bit>
- <bit pos="6">OTL RX acTag specified in the command points to an invalid entry.</bit>
- <bit pos="7">OTL RX reserved opcode used.</bit>
- <bit pos="8">OTL RX return_tl_credit command found outside slot0.</bit>
- <bit pos="9">OTL RX bad opcode and template combination.</bit>
- <bit pos="10">OTL RX unsupported template format.</bit>
- <bit pos="11">OTL RX bad template x00 format.</bit>
- <bit pos="12">OTL RX control flit overrun.</bit>
- <bit pos="13">OTL RX unexpected data flit.</bit>
- <bit pos="14">OTL RX DL link down.</bit>
- <bit pos="15">OTL RX bad data received on command.</bit>
- <bit pos="16">OTL RX bad data received on response.</bit>
- <bit pos="17">OTL RX AP response not allowed (CAPPTag not recognized).</bit>
- <bit pos="18">OR of all OTL parity errors.</bit>
- <bit pos="19">OR of all OTL ECC CE errors.</bit>
- <bit pos="20">OR of all OTL ECC UE errors.</bit>
- <bit pos="21">RXO OP Errors.</bit>
- <bit pos="22">RXO Internal Errors.</bit>
- <bit pos="23">OTL RXI fifo overrun.</bit>
- <bit pos="24">OTL RXI control flit data run length invalid.</bit>
- <bit pos="25">OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL.</bit>
- <bit pos="26">OTL RXI bad data received vc2.</bit>
- <bit pos="27">OTL RXI dcp2 fifo overrun.</bit>
- <bit pos="28">OTL RXI vc1 fifo overrun.</bit>
- <bit pos="29">OTL RXI vc2 fifo overrun.</bit>
- <bit pos="30">Opcode data length not supported.</bit>
- <bit pos="31">OTL TXI opcode error.</bit>
- <bit pos="32">malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2).</bit>
+ <bit pos="4">OTL TL credit counter overflow caused by return_tl_credits</bit>
+ <bit pos="5">OTL RX acTag specified in a command is outside the configured specification set</bit>
+ <bit pos="6">OTL RX acTag specified in the command points to an invalid entry</bit>
+ <bit pos="7">OTL RX reserved opcode used</bit>
+ <bit pos="8">OTL RX return_tl_credit command found outside slot0</bit>
+ <bit pos="9">OTL RX bad opcode and template combination</bit>
+ <bit pos="10">OTL RX unsupported template format</bit>
+ <bit pos="11">OTL RX bad template x00 format</bit>
+ <bit pos="12">OTL RX control flit overrun</bit>
+ <bit pos="13">OTL RX unexpected data flit</bit>
+ <bit pos="14">OTL RX DL link down</bit>
+ <bit pos="15">OTL RX bad data received on command</bit>
+ <bit pos="16">OTL RX bad data received on response</bit>
+ <bit pos="17">OTL RX AP response not allowed (CAPPTag not recognized)</bit>
+ <bit pos="18">OR of all OTL parity errors</bit>
+ <bit pos="19">OR of all OTL ECC CE errors</bit>
+ <bit pos="20">OR of all OTL ECC UE errors</bit>
+ <bit pos="21">RXO OP Errors</bit>
+ <bit pos="22">RXO Internal Errors</bit>
+ <bit pos="23">OTL RXI fifo overrun</bit>
+ <bit pos="24">OTL RXI control flit data run length invalid</bit>
+ <bit pos="25">OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL</bit>
+ <bit pos="26">OTL RXI bad data received vc2</bit>
+ <bit pos="27">OTL RXI dcp2 fifo overrun</bit>
+ <bit pos="28">OTL RXI vc1 fifo overrun</bit>
+ <bit pos="29">OTL RXI vc2 fifo overrun</bit>
+ <bit pos="30">Opcode data length not supported</bit>
+ <bit pos="31">OTL TXI opcode error</bit>
+ <bit pos="32">malformed packet error type 4 (rxi_misc_error_fieldrsvdne0_tlvc2)</bit>
<bit pos="33">OTL Happi no bar match</bit>
- <bit pos="34">OTL Reserved, macro bit 30.</bit>
- <bit pos="35">OTL Reserved, macro bit 31.</bit>
- <bit pos="36">MMIO invalidate requested while one is in progress.</bit>
- <bit pos="37">Unexpected ITAG returned on itag completion port 0.</bit>
- <bit pos="38">Unexpected ITAG returned on itag completion port 1.</bit>
- <bit pos="39">Unexpected Read PEE completion.</bit>
- <bit pos="40">Unexpected Checkout response.</bit>
- <bit pos="41">Translation request while SPAP is invalid.</bit>
- <bit pos="42">Read a PEE which was not valid.</bit>
- <bit pos="43">Bloom filter protection error.</bit>
- <bit pos="44">Translation request to non-valid TA.</bit>
- <bit pos="45">TA Translation request to an invalid TA.</bit>
- <bit pos="46">correctable array error (SBE).</bit>
- <bit pos="47">uncorrectable array error (UE or parity).</bit>
- <bit pos="48">S/TLBI buffer overflow.</bit>
- <bit pos="49">SBE correctable error on Powerbus checkout response data or Powerbus PEE read data.</bit>
- <bit pos="50">UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data.</bit>
- <bit pos="51">SUE error on Powerbus checkout response data or Powerbus PEE read data.</bit>
- <bit pos="52">PA mem_hit when bar mode is nonzero .</bit>
- <bit pos="53">XSL Reserved, macro bit 17.</bit>
+ <bit pos="34">OTL Reserved, macro bit 30</bit>
+ <bit pos="35">OTL Reserved, macro bit 31</bit>
+ <bit pos="36">MMIO invalidate requested while one is in progress</bit>
+ <bit pos="37">Unexpected ITAG returned on itag completion port 0</bit>
+ <bit pos="38">Unexpected ITAG returned on itag completion port 1</bit>
+ <bit pos="39">Unexpected Read PEE completion</bit>
+ <bit pos="40">Unexpected Checkout response</bit>
+ <bit pos="41">Translation request while SPAP is invalid</bit>
+ <bit pos="42">Read a PEE which was not valid</bit>
+ <bit pos="43">Bloom filter protection error</bit>
+ <bit pos="44">Translation request to non-valid TA</bit>
+ <bit pos="45">TA Translation request to an invalid TA</bit>
+ <bit pos="46">correctable array error (SBE)</bit>
+ <bit pos="47">uncorrectable array error (UE or parity)</bit>
+ <bit pos="48">S/TLBI buffer overflow</bit>
+ <bit pos="49">SBE correctable error on Powerbus checkout response data or Powerbus PEE read data</bit>
+ <bit pos="50">UE uncorrectable error on Powerbus checkout response data or Powerbus PEE read data</bit>
+ <bit pos="51">SUE error on Powerbus checkout response data or Powerbus PEE read data</bit>
+ <bit pos="52">PA mem_hit when bar mode is nonzero</bit>
+ <bit pos="53">XSL Reserved, macro bit 17</bit>
<bit pos="54">OTL Brick0 translation fault</bit>
<bit pos="55">OTL Brick1 translation fault</bit>
<bit pos="56">AME ECC UE on control information or state bit errors that are contained within AME and ATL</bit>
diff --git a/xml/p10/node_pci_etu_fir.xml b/xml/p10/node_pci_etu_fir.xml
index d64ba50..2a49a08 100644
--- a/xml/p10/node_pci_etu_fir.xml
+++ b/xml/p10/node_pci_etu_fir.xml
@@ -10,68 +10,68 @@
<action attn_type="CS" config="00"/>
<action attn_type="RE" config="01"/>
</local_fir>
- <bit pos="0">See Outbound Error Status Register, bit 0 for details.</bit>
- <bit pos="1">See Outbound Error Status Register, bit 1/2 for details.</bit>
- <bit pos="2">See Outbound Error Status Register, bit 3/8 for details.</bit>
- <bit pos="3">See Outbound Error Status Register, bit 28 for details.</bit>
- <bit pos="4">See Outbound Error Status Register, bit 4/5/9/10/11/14/15 for details.</bit>
- <bit pos="5">ETU FIR Register</bit>
- <bit pos="6">See Outbound Error Status Register, bit 6 for details.</bit>
- <bit pos="7">See Outbound Error Status Register, bit 13/22 for details.</bit>
- <bit pos="8">See Outbound Error Status Register, bit 23/37/38/40/43/44/45/47/48/49 for details.</bit>
- <bit pos="9">See Outbound Error Status Register, bit 50/51/52 for details.</bit>
- <bit pos="10">See Outbound Error Status Register, bit 19/20/21/53/54/55 for details.</bit>
- <bit pos="11">See Outbound Error Status Register, bit 16 for details.</bit>
- <bit pos="12">See Outbound Error Status Register, bit 17 for details.</bit>
- <bit pos="13">See Outbound Error Status Register, bit 18 for details.</bit>
- <bit pos="14">See Outbound Error Status Register, bit 56/57 for details.</bit>
- <bit pos="15">See Outbound Error Status Register, bit 17 for details.</bit>
- <bit pos="16">See RSB Error Status Register, bit 00 for details.</bit>
- <bit pos="17">See RSB Error Status Register, bit 2/3/5 for details.</bit>
- <bit pos="18">See RSB Error Status Register, bit 1/4 for details.</bit>
- <bit pos="19">See RSB Error Status Register, bit 9/10 for details.</bit>
- <bit pos="20">See RSB Error Status Register, bit 8 for details.</bit>
- <bit pos="21">See RSB Error Status Register, bit 7 for details.</bit>
- <bit pos="22">See RSB Error Status Register, bit 6 for details.</bit>
- <bit pos="23">See RSB Error Status Register, bit 13/14 for details.</bit>
- <bit pos="24">See RSB Error Status Register, bit 12 for details.</bit>
- <bit pos="25">See Outbound Error Status Register, bit 11 for details.</bit>
- <bit pos="26">See Outbound Error Status Register, bit 15/27 for details.</bit>
- <bit pos="27">See RSB Error Status Register, bit 17/19 for details.</bit>
- <bit pos="28">See RSB Error Status Register, bit 16/18 for details.</bit>
- <bit pos="29">See RSB Error Status Register, bit 30/31 for details.</bit>
- <bit pos="30">See RSB Error Status Register, bit 28/29 for details.</bit>
- <bit pos="31">See RSB Error Status Register, bit 24/25/26 for details.</bit>
- <bit pos="32">See ARB Error Status Register, bit 33 for details.</bit>
- <bit pos="33">See ARB Error Status Register, bit 27 for details.</bit>
- <bit pos="34">See ARB Error Status Register, bit 02/03 for details.</bit>
- <bit pos="35">See ARB Error Status Register, bit 26/28 for details.</bit>
- <bit pos="36">See ARB Error Status Register, bit 57 for details.</bit>
- <bit pos="37">See ARB Error Status Register, bit 58 for details.</bit>
- <bit pos="38">See ARB Error Status Register, bit 59 for details.</bit>
- <bit pos="39">See Outbound Error Status Register, bit 39 for details.</bit>
- <bit pos="40">See ARB Error Status Register, bit 4/7/8/9/10/11/12/13/14/15/16/17/18/22/23/36/37/38/42/43/44/45/46/47/48/59/55/56 for details.</bit>
- <bit pos="41">See ARB Error Status Register, bit 32/41 for details.</bit>
- <bit pos="42">See ARB Error Status Register, bit 00/01/19 for details.</bit>
- <bit pos="43">See ARB Error Status Register, bit 34/35 for details.</bit>
- <bit pos="44">See ARB Error Status Register, bit 5/20/25/29 for details.</bit>
- <bit pos="45">See ARB Error Status Register, bit 6/26/30/31 for details.</bit>
- <bit pos="46">See ARB Error Status Register, bit 24 for details.</bit>
- <bit pos="47">See ARB Error Status Register, bit 40 for details.</bit>
- <bit pos="48">See MRG Error Status Register, bit 08-16/22/23/26/28/30-37/40-50 for details.</bit>
- <bit pos="49">See MRG Error Status Register, bit 51 for details.</bit>
- <bit pos="50">See MRG Error Status Register, bit 40/56/58/60 for details.</bit>
- <bit pos="51">See MRG Error Status Register, bit 41/57/59/61 for details.</bit>
- <bit pos="52">See MRG Error Status Register, bit 24 for details.</bit>
- <bit pos="53">See MRG Error Status Register, bit 17/18 for details.</bit>
- <bit pos="54">ETU FIR Register</bit>
- <bit pos="55">ETU FIR Register</bit>
- <bit pos="56">See TCE Error Status Register, bit 01/02 for details.</bit>
- <bit pos="57">See TCE Error Status Register, bit 08 for details.</bit>
- <bit pos="58">See TCE Error Status Register, bit 13 for details.</bit>
- <bit pos="59">See TCE Error Status Register for details.</bit>
- <bit pos="60">See TCE Error Status Register, bit 09/11/25/27 for details.</bit>
- <bit pos="61">See TCE Error Status Register, bit 10/12/26/28 for details.</bit>
- <bit pos="62">ETU FIR Register</bit>
- <bit pos="63">FIR Internal Parity Error.</bit>
+ <bit pos="0">AIB_COMMAND_INVALID</bit>
+ <bit pos="1">AIB_ADDRESS_INVALID</bit>
+ <bit pos="2">AIB_ACCESS_ERROR</bit>
+ <bit pos="3">PAPR_OUTBOUND_INJECT_ERROR</bit>
+ <bit pos="4">AIB_FATAL_CLASS_ERROR</bit>
+ <bit pos="5">AIB_INF_CLASS_ERROR</bit>
+ <bit pos="6">spare</bit>
+ <bit pos="7">PE_STOP_STATE_SIGNALED</bit>
+ <bit pos="8">OUT_COMMON_ARRAY_FATAL_ERROR</bit>
+ <bit pos="9">OUT_COMMON_LATCH_FATAL_ERROR</bit>
+ <bit pos="10">OUT_COMMON_LOGIC_FATAL_ERROR</bit>
+ <bit pos="11">BLIF_OUT_INTERFACE_PARITY_ERROR</bit>
+ <bit pos="12">CFG_WRITE_CA_OR_UR_RESPONSE</bit>
+ <bit pos="13">MMIO_REQUEST_TIMEOUT</bit>
+ <bit pos="14">OUT_RRB_SOURCED_ERROR</bit>
+ <bit pos="15">CFG_LOGIC_SIGNALED_ERROR</bit>
+ <bit pos="16">RSB_REG_REQUEST_ADDRESS_ERROR</bit>
+ <bit pos="17">RSB_FDA_FATAL_ERROR</bit>
+ <bit pos="18">RSB_FDA_INF_ERROR</bit>
+ <bit pos="19">RSB_FDB_FATAL_ERROR</bit>
+ <bit pos="20">RSB_FDB_INF_ERROR</bit>
+ <bit pos="21">RSB_ERR_FATAL_ERROR</bit>
+ <bit pos="22">RSB_ERR_INF_ERROR</bit>
+ <bit pos="23">RSB_DBG_FATAL_ERROR</bit>
+ <bit pos="24">RSB_DBG_INF_ERROR</bit>
+ <bit pos="25">PCIE_REQUEST_ACCESS_ERROR</bit>
+ <bit pos="26">RSB_BUS_LOGIC_ERROR</bit>
+ <bit pos="27">RSB_UVI_FATAL_ERROR</bit>
+ <bit pos="28">RSB_UVI_INF_ERROR</bit>
+ <bit pos="29">SCOM_FATAL_ERROR</bit>
+ <bit pos="30">SCOM_INF_ERROR</bit>
+ <bit pos="31">PCIE_MACRO_ERROR_ACTIVE_STATUS</bit>
+ <bit pos="32">ARB_IODA_FATAL_ERROR</bit>
+ <bit pos="33">ARB_MSI_PE_MATCH_ERROR</bit>
+ <bit pos="34">ARB_MSI_ADDRESS_ERROR</bit>
+ <bit pos="35">ARB_TVT_ERROR</bit>
+ <bit pos="36">ARB_RCVD_FATAL_ERROR_MSG</bit>
+ <bit pos="37">ARB_RCVD_NONFATAL_ERROR_MSG</bit>
+ <bit pos="38">ARB_RCVD_CORRECTIBLE_ERROR_MSG</bit>
+ <bit pos="39">PAPR_INBOUND_INJECT_ERROR</bit>
+ <bit pos="40">ARB_COMMON_FATAL_ERROR</bit>
+ <bit pos="41">ARB_TABLE_BAR_DISABLED_ERROR</bit>
+ <bit pos="42">ARB_BLIF_COMPLETION_ERROR</bit>
+ <bit pos="43">ARB_PCT_TIMEOUT_ERROR</bit>
+ <bit pos="44">ARB_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="45">ARB_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="46">ARB_TLP_POISON_SIGNALED</bit>
+ <bit pos="47">ARB_RTT_PENUM_INVALID_ERROR</bit>
+ <bit pos="48">MRG_COMMON_FATAL_ERROR</bit>
+ <bit pos="49">MRG_TABLE_BAR_DISABLED_ERROR</bit>
+ <bit pos="50">MRG_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="51">MRG_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="52">MRG_AIB2_TX_TIMEOUT_ERROR</bit>
+ <bit pos="53">MRG_MRT_ERROR</bit>
+ <bit pos="54">spare</bit>
+ <bit pos="55">spare</bit>
+ <bit pos="56">TCE_IODA_PAGE_ACCESS_ERROR</bit>
+ <bit pos="57">TCE_REQUEST_TIMEOUT_ERROR</bit>
+ <bit pos="58">TCE_UNEXPECTED_RESPONSE_ERROR</bit>
+ <bit pos="59">TCE_COMMON_FATAL_ERROR</bit>
+ <bit pos="60">TCE_ECC_CORRECTABLE_ERROR</bit>
+ <bit pos="61">TCE_ECC_UNCORRECTABLE_ERROR</bit>
+ <bit pos="62">spare</bit>
+ <bit pos="63">FIR_INTERNAL_PARITY_ERROR</bit>
</attn_node>
diff --git a/xml/p10/node_pci_fir.xml b/xml/p10/node_pci_fir.xml
index bd68142..826c6ac 100644
--- a/xml/p10/node_pci_fir.xml
+++ b/xml/p10/node_pci_fir.xml
@@ -10,10 +10,24 @@
<action attn_type="CS" config="00"/>
<action attn_type="RE" config="01"/>
</local_fir>
- <bit pos="0">PCI FIR</bit>
- <bit pos="1">PCI FIR</bit>
- <bit pos="2">PCI FIR</bit>
- <bit pos="3">PCI FIR</bit>
- <bit pos="4">PCI FIR</bit>
- <bit pos="5">PCI FIR</bit>
+
+ <register name="PBAIB_CERR_RPT_REG">
+ <instance reg_inst="0" addr="0x0801084B" />
+ <instance reg_inst="1" addr="0x0801088B" />
+ <instance reg_inst="2" addr="0x080108CB" />
+ <instance reg_inst="3" addr="0x0901084B" />
+ <instance reg_inst="4" addr="0x0901088B" />
+ <instance reg_inst="5" addr="0x090108CB" />
+ </register>
+
+ <capture_group node_inst="0:5">
+ <capture_register reg_name="PBAIB_CERR_RPT_REG" reg_inst="0:5" />
+ </capture_group>
+
+ <bit pos="0">register parity error</bit>
+ <bit pos="1">hardware error</bit>
+ <bit pos="2">AIB interface error</bit>
+ <bit pos="3">ETU reset error</bit>
+ <bit pos="4">PEC SCOM error</bit>
+ <bit pos="5">spare</bit>
</attn_node>
diff --git a/xml/p10/node_pci_nest_fir.xml b/xml/p10/node_pci_nest_fir.xml
index d594ebe..8fe18bb 100644
--- a/xml/p10/node_pci_nest_fir.xml
+++ b/xml/p10/node_pci_nest_fir.xml
@@ -10,32 +10,56 @@
<action attn_type="CS" config="00"/>
<action attn_type="RE" config="01"/>
</local_fir>
- <bit pos="0">PCI Nest FIR NFIR</bit>
- <bit pos="1">PCI Nest FIR NFIR</bit>
- <bit pos="2">PCI Nest FIR NFIR</bit>
- <bit pos="3">PCI Nest FIR NFIR</bit>
- <bit pos="4">PCI Nest FIR NFIR</bit>
- <bit pos="5">PCI Nest FIR NFIR</bit>
- <bit pos="6">PCI Nest FIR NFIR</bit>
- <bit pos="7">PCI Nest FIR NFIR</bit>
- <bit pos="8">PCI Nest FIR NFIR</bit>
- <bit pos="9">PCI Nest FIR NFIR</bit>
- <bit pos="10">PCI Nest FIR NFIR</bit>
- <bit pos="11">PCI Nest FIR NFIR</bit>
- <bit pos="12">PCI Nest FIR NFIR</bit>
- <bit pos="13">PCI Nest FIR NFIR</bit>
- <bit pos="14">PCI Nest FIR NFIR</bit>
- <bit pos="15">PCI Nest FIR NFIR</bit>
- <bit pos="16">PCI Nest FIR NFIR</bit>
- <bit pos="17">PCI Nest FIR NFIR</bit>
- <bit pos="18">PCI Nest FIR NFIR</bit>
- <bit pos="19">PCI Nest FIR NFIR</bit>
- <bit pos="20">PCI Nest FIR NFIR</bit>
- <bit pos="21">PCI Nest FIR NFIR</bit>
- <bit pos="22">PCI Nest FIR NFIR</bit>
- <bit pos="23">PCI Nest FIR NFIR</bit>
- <bit pos="24">PCI Nest FIR NFIR</bit>
- <bit pos="25">PCI Nest FIR NFIR</bit>
- <bit pos="26">PCI Nest FIR NFIR</bit>
- <bit pos="27">PCI Nest FIR NFIR</bit>
+
+ <register name="PCI_NFIR_ERR_RPT0">
+ <instance reg_inst="0" addr="0x0301184A" />
+ <instance reg_inst="1" addr="0x0301188A" />
+ <instance reg_inst="2" addr="0x030118CA" />
+ <instance reg_inst="3" addr="0x0201184A" />
+ <instance reg_inst="4" addr="0x0201188A" />
+ <instance reg_inst="5" addr="0x020118CA" />
+ </register>
+
+ <register name="PCI_NFIR_ERR_RPT1">
+ <instance reg_inst="0" addr="0x0301184B" />
+ <instance reg_inst="1" addr="0x0301188B" />
+ <instance reg_inst="2" addr="0x030118CB" />
+ <instance reg_inst="3" addr="0x0201184B" />
+ <instance reg_inst="4" addr="0x0201188B" />
+ <instance reg_inst="5" addr="0x020118CB" />
+ </register>
+
+ <capture_group node_inst="0:5">
+ <capture_register reg_name="PCI_NFIR_ERR_RPT0" reg_inst="0:5" />
+ <capture_register reg_name="PCI_NFIR_ERR_RPT1" reg_inst="0:5" />
+ </capture_group>
+
+ <bit pos="0">BAR Parity Error</bit>
+ <bit pos="1">Non-BAR Parity Error</bit>
+ <bit pos="2">Power Bus to PEC CE</bit>
+ <bit pos="3">Power Bus to PEC UE</bit>
+ <bit pos="4">Power Bus to PEC SUE</bit>
+ <bit pos="5">Array CE</bit>
+ <bit pos="6">Array UE</bit>
+ <bit pos="7">Array SUE</bit>
+ <bit pos="8">Register Array Parity Error</bit>
+ <bit pos="9">Power Bus Interface Parity Error</bit>
+ <bit pos="10">Power Bus Data Hang</bit>
+ <bit pos="11">Power Bus Hang Error</bit>
+ <bit pos="12">RD ARE Error</bit>
+ <bit pos="13">Non-Rd ARE Error</bit>
+ <bit pos="14">PCI Hang Error</bit>
+ <bit pos="15">PCI Clock Error</bit>
+ <bit pos="16">AIB Fence</bit>
+ <bit pos="17">Hardware Error</bit>
+ <bit pos="18">Unsolicited Power Bus Data</bit>
+ <bit pos="19">Unexpected Combined Response</bit>
+ <bit pos="20">Invalid Combined Response</bit>
+ <bit pos="21">Power Bus Unsupported Size</bit>
+ <bit pos="22">Power Bus Unsupported Command</bit>
+ <bit pos="23">reserved</bit>
+ <bit pos="24">reserved</bit>
+ <bit pos="25">reserved</bit>
+ <bit pos="26">Software Defined</bit>
+ <bit pos="27">PEC SCOM Engine Error</bit>
</attn_node>