Add OMI_DL_ERROR_HOLD to chip data XML
There is one for P10 and another for Explorer, with very similar
patterns.
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ied70efd56ee09d8925480aebee52b0bf1b328a70
diff --git a/xml/p10/node_mc_omi_dl_fir.xml b/xml/p10/node_mc_omi_dl_fir.xml
index 396d0f4..50bcfe8 100644
--- a/xml/p10/node_mc_omi_dl_fir.xml
+++ b/xml/p10/node_mc_omi_dl_fir.xml
@@ -13,66 +13,37 @@
<action attn_type="RE" config="01"/>
<action attn_type="SPA" config="10"/>
</local_fir>
- <bit pos="0">OMI-DL0 fatal_error - see error hold register(54 to 63) for details</bit>
- <bit pos="1">OMI-DL0 UE on data flit - see error hold register(50 to 51) for details</bit>
- <bit pos="2">OMI-DL0 CE on TL flit - see error hold register(48 to 49) for details</bit>
- <bit pos="3">OMI-DL0 detected a CRC error</bit>
- <bit pos="4">OMI-DL0 received a nack</bit>
- <bit pos="5">OMI-DL0 running in degraded mode - see error hold register(44 to 45) for details</bit>
- <bit pos="6">OMI-DL0 parity error detection on a lane - see error hold register(34 to 43) for details</bit>
- <bit pos="7">OMI-DL0 retrained due to no forward progress</bit>
- <bit pos="8">OMI-DL0 remote side initiated a retrain</bit>
- <bit pos="9">OMI-DL0 retrain due to internal error or software initiated - see error hold register(28 to 31) for details</bit>
- <bit pos="10">OMI-DL0 threshold reached - see error hold register(25 to 27) for details</bit>
- <bit pos="11">OMI-DL0 trained</bit>
- <bit pos="12">OMI-DL0 endpoint error bit 0</bit>
- <bit pos="13">OMI-DL0 endpoint error bit 1</bit>
- <bit pos="14">OMI-DL0 endpoint error bit 2</bit>
- <bit pos="15">OMI-DL0 endpoint error bit 3</bit>
- <bit pos="16">OMI-DL0 endpoint error bit 4</bit>
- <bit pos="17">OMI-DL0 endpoint error bit 5</bit>
- <bit pos="18">OMI-DL0 endpoint error bit 6</bit>
- <bit pos="19">OMI-DL0 endpoint error bit 7</bit>
- <bit pos="20">OMI-DL1 fatal_error - see error hold register(54 to 63) for details</bit>
- <bit pos="21">OMI-DL1 UE on data flit - see error hold register(50 to 51) for details</bit>
- <bit pos="22">OMI-DL1 CE on TL flit - see error hold register(48 to 49) for details</bit>
- <bit pos="23">OMI-DL1 detected a CRC error</bit>
- <bit pos="24">OMI-DL1 received a nack</bit>
- <bit pos="25">OMI-DL1 running in degraded mode - see error hold register(44 to 45) for details</bit>
- <bit pos="26">OMI-DL1 parity error detection on a lane - see error hold register(34 to 43) for details</bit>
- <bit pos="27">OMI-DL1 retrained due to no forward progress</bit>
- <bit pos="28">OMI-DL1 remote side initiated a retrain</bit>
- <bit pos="29">OMI-DL1 retrain due to internal error or software initiated - see error hold register(28 to 31) for details</bit>
- <bit pos="30">OMI-DL1 threshold reached - see error hold register(25 to 27) for details</bit>
- <bit pos="31">OMI-DL1 trained</bit>
- <bit pos="32">OMI-DL1 endpoint error bit 0</bit>
- <bit pos="33">OMI-DL1 endpoint error bit 1</bit>
- <bit pos="34">OMI-DL1 endpoint error bit 2</bit>
- <bit pos="35">OMI-DL1 endpoint error bit 3</bit>
- <bit pos="36">OMI-DL1 endpoint error bit 4</bit>
- <bit pos="37">OMI-DL1 endpoint error bit 5</bit>
- <bit pos="38">OMI-DL1 endpoint error bit 6</bit>
- <bit pos="39">OMI-DL1 endpoint error bit 7</bit>
- <bit pos="40">OMI-DL2 unused</bit>
- <bit pos="41">OMI-DL2 unused</bit>
- <bit pos="42">OMI-DL2 unused</bit>
- <bit pos="43">OMI-DL2 unused</bit>
- <bit pos="44">OMI-DL2 unused</bit>
- <bit pos="45">OMI-DL2 unused</bit>
- <bit pos="46">OMI-DL2 unused</bit>
- <bit pos="47">OMI-DL2 unused</bit>
- <bit pos="48">OMI-DL2 unused</bit>
- <bit pos="49">OMI-DL2 unused</bit>
- <bit pos="50">OMI-DL2 unused</bit>
- <bit pos="51">OMI-DL2 unused</bit>
- <bit pos="52">OMI-DL2 unused</bit>
- <bit pos="53">OMI-DL2 unused</bit>
- <bit pos="54">OMI-DL2 unused</bit>
- <bit pos="55">OMI-DL2 unused</bit>
- <bit pos="56">OMI-DL2 unused</bit>
- <bit pos="57">OMI-DL2 unused</bit>
- <bit pos="58">OMI-DL2 unused</bit>
- <bit pos="59">OMI-DL2 unused</bit>
- <bit pos="60">performance monitor wrapped</bit>
+
+ <register name="CMN_CONFIG">
+ <instance reg_inst="0" addr="0x0C01140E" />
+ <instance reg_inst="1" addr="0x0C01180E" />
+ <instance reg_inst="2" addr="0x0D01140E" />
+ <instance reg_inst="3" addr="0x0D01180E" />
+ <instance reg_inst="4" addr="0x0E01140E" />
+ <instance reg_inst="5" addr="0x0E01180E" />
+ <instance reg_inst="6" addr="0x0F01140E" />
+ <instance reg_inst="7" addr="0x0F01180E" />
+ </register>
+
+ <register name="PMU_CNTR">
+ <instance reg_inst="0" addr="0x0C01140F" />
+ <instance reg_inst="1" addr="0x0C01180F" />
+ <instance reg_inst="2" addr="0x0D01140F" />
+ <instance reg_inst="3" addr="0x0D01180F" />
+ <instance reg_inst="4" addr="0x0E01140F" />
+ <instance reg_inst="5" addr="0x0E01180F" />
+ <instance reg_inst="6" addr="0x0F01140F" />
+ <instance reg_inst="7" addr="0x0F01180F" />
+ </register>
+
+ <capture_group node_inst="0:7">
+ <capture_register reg_name="CMN_CONFIG" reg_inst="0:7" />
+ <capture_register reg_name="PMU_CNTR" reg_inst="0:7" />
+ </capture_group>
+
+ <bit pos="0:19" child_node="MC_OMI_DL" node_inst="0,2,4,6,8,10,12,14">OMI-DL0</bit>
+ <bit pos="20:39" child_node="MC_OMI_DL" node_inst="1,3,5,7,9,11,13,15">OMI-DL1</bit>
+ <bit pos="40:59">OMI-DL2</bit>
+ <bit pos="60">Performance monitor wrapped</bit>
<bit pos="61">OMI-DL common FIR Register</bit>
</attn_node>