Chip data file updates for PAUC chiplet
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ic6b7cc0d43240982b73021e4fc71400004ba170b
diff --git a/xml/p10/node_pau_ptl_fir.xml b/xml/p10/node_pau_ptl_fir.xml
index 4086969..d6cb342 100644
--- a/xml/p10/node_pau_ptl_fir.xml
+++ b/xml/p10/node_pau_ptl_fir.xml
@@ -9,6 +9,36 @@
<action attn_type="RE" config="01"/>
<action attn_type="SPA" config="10"/>
</local_fir>
+ <register name="PB_TL_LINK_SYN_01">
+ <instance reg_inst="0" addr="0x10011812" />
+ <instance reg_inst="1" addr="0x11011812" />
+ <instance reg_inst="2" addr="0x12011812" />
+ <instance reg_inst="3" addr="0x13011812" />
+ </register>
+ <register name="PB_TL_LINK_SYN_23">
+ <instance reg_inst="0" addr="0x10011813" />
+ <instance reg_inst="1" addr="0x11011813" />
+ <instance reg_inst="2" addr="0x12011813" />
+ <instance reg_inst="3" addr="0x13011813" />
+ </register>
+ <register name="PB_EN_DOB_ECC_ERR">
+ <instance reg_inst="0" addr="0x10011818" />
+ <instance reg_inst="1" addr="0x11011818" />
+ <instance reg_inst="2" addr="0x12011818" />
+ <instance reg_inst="3" addr="0x13011818" />
+ </register>
+ <register name="PB_MISC_CFG">
+ <instance reg_inst="0" addr="0x10011825" />
+ <instance reg_inst="1" addr="0x11011825" />
+ <instance reg_inst="2" addr="0x12011825" />
+ <instance reg_inst="3" addr="0x13011825" />
+ </register>
+ <capture_group node_inst="0:3">
+ <capture_register reg_name="PB_TL_LINK_SYN_01" reg_inst="0:3" />
+ <capture_register reg_name="PB_TL_LINK_SYN_23" reg_inst="0:3" />
+ <capture_register reg_name="PB_EN_DOB_ECC_ERR" reg_inst="0:3" />
+ <capture_register reg_name="PB_MISC_CFG" reg_inst="0:3" />
+ </capture_group>
<bit pos="0">fmr00 trained. Even PTL, even half.</bit>
<bit pos="1">fmr01 trained. Even PTL, odd half.</bit>
<bit pos="2">fmr02 trained. Odd PTL, even half.</bit>
@@ -16,35 +46,35 @@
<bit pos="4">dob01 ue</bit>
<bit pos="5">dob01 ce</bit>
<bit pos="6">dob01 sue</bit>
- <bit pos="7">data outbound switch internal error - even PTL.</bit>
+ <bit pos="7" child_node="PB_DOB01_DIB01_INT_ERR" node_inst="0:3">data outbound switch internal error - even PTL.</bit>
<bit pos="8">dob23 ue</bit>
<bit pos="9">dob23 ce</bit>
<bit pos="10">dob23 sue</bit>
- <bit pos="11">data outbound switch internal error - odd PTL.</bit>
- <bit pos="12">Even PTL, even framer internal error</bit>
+ <bit pos="11" child_node="PB_DOB23_DIB23_INT_ERR" node_inst="0:3">data outbound switch internal error - odd PTL.</bit>
+ <bit pos="12" child_node="PB_FM0123_ERR" node_inst="0:3">Even PTL, even framer internal error</bit>
<bit pos="13">Even PTL, outbound switch cmd/presp/cresp internal error</bit>
- <bit pos="14">Even PTL, odd framer internal error</bit>
- <bit pos="15">Odd PTL, even framer internal error</bit>
+ <bit pos="14" child_node="PB_FM0123_ERR" node_inst="0:3">Even PTL, odd framer internal error</bit>
+ <bit pos="15" child_node="PB_FM0123_ERR" node_inst="0:3">Odd PTL, even framer internal error</bit>
<bit pos="16">Odd PTL, outbound switch cmd/presp/cresp internal error</bit>
- <bit pos="17">Odd PTL, odd framer internal error</bit>
- <bit pos="18">Even PTL, even parser internal error</bit>
- <bit pos="19">Even PTL, odd parser internal error</bit>
- <bit pos="20">Odd PTL, even parser internal error</bit>
- <bit pos="21">Odd PTL, odd parser internal error</bit>
+ <bit pos="17" child_node="PB_FM0123_ERR" node_inst="0:3">Odd PTL, odd framer internal error</bit>
+ <bit pos="18" child_node="PB_PR0123_ERR" node_inst="0:3">Even PTL, even parser internal error</bit>
+ <bit pos="19" child_node="PB_PR0123_ERR" node_inst="0:3">Even PTL, odd parser internal error</bit>
+ <bit pos="20" child_node="PB_PR0123_ERR" node_inst="0:3">Odd PTL, even parser internal error</bit>
+ <bit pos="21" child_node="PB_PR0123_ERR" node_inst="0:3">Odd PTL, odd parser internal error</bit>
<bit pos="22">Even PTL, even link down</bit>
<bit pos="23">Even PTL, odd link down</bit>
<bit pos="24">Odd PTL, even link down</bit>
<bit pos="25">Odd PTL, odd link down</bit>
- <bit pos="26">Even PTL data inbound switch internal error</bit>
- <bit pos="27">Odd PTL data inbound switch internal error</bit>
- <bit pos="28">mailbox 00 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_00_REG.</bit>
- <bit pos="29">mailbox 01 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_01_REG.</bit>
- <bit pos="30">mailbox 10 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_10_REG.</bit>
- <bit pos="31">mailbox 11 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_11_REG.</bit>
- <bit pos="32">mailbox 20 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_20_REG.</bit>
- <bit pos="33">mailbox 21 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_21_REG.</bit>
- <bit pos="34">mailbox 30 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_30_REG.</bit>
- <bit pos="35">mailbox 31 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_31_REG.</bit>
+ <bit pos="26" child_node="PB_DOB01_DIB01_INT_ERR" node_inst="0:3">Even PTL data inbound switch internal error</bit>
+ <bit pos="27" child_node="PB_DOB23_DIB23_INT_ERR" node_inst="0:3">Odd PTL data inbound switch internal error</bit>
+ <bit pos="28">mailbox 00 special attention</bit>
+ <bit pos="29">mailbox 01 special attention</bit>
+ <bit pos="30">mailbox 10 special attention</bit>
+ <bit pos="31">mailbox 11 special attention</bit>
+ <bit pos="32">mailbox 20 special attention</bit>
+ <bit pos="33">mailbox 21 special attention</bit>
+ <bit pos="34">mailbox 30 special attention</bit>
+ <bit pos="35">mailbox 31 special attention</bit>
<bit pos="36">ptl0 spare</bit>
<bit pos="37">ptl1 spare</bit>
<bit pos="38">ptl2 spare</bit>