diff --git a/xml/p10/node_pau_pb0123_pr_err.xml b/xml/p10/node_pau_pb0123_pr_err.xml
new file mode 100644
index 0000000..4ec3fd2
--- /dev/null
+++ b/xml/p10/node_pau_pb0123_pr_err.xml
@@ -0,0 +1,74 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_PR0123_ERR" reg_type="SCOM">
+    <register name="PB_PR0123_ERR">
+        <instance reg_inst="0" addr="0x10011829" />
+        <instance reg_inst="1" addr="0x11011829" />
+        <instance reg_inst="2" addr="0x12011829" />
+        <instance reg_inst="3" addr="0x13011829" />
+    </register>
+    <rule attn_type="CS" node_inst="0:3">
+        <expr type="reg" value1="PB_PR0123_ERR"/>
+    </rule>
+    <rule attn_type="RE" node_inst="0:3">
+        <expr type="reg" value1="PB_PR0123_ERR"/>
+    </rule>
+    <rule attn_type="SPA" node_inst="0:3">
+        <expr type="reg" value1="PB_PR0123_ERR"/>
+    </rule>
+    <bit pos="0">prs0_address_pty</bit>
+    <bit pos="1">prs0_atag_pty</bit>
+    <bit pos="2">prs0_cc0_crediterr</bit>
+    <bit pos="3">prs0_cc1_crediterr</bit>
+    <bit pos="4">prs0_cc2_crediterr</bit>
+    <bit pos="5">prs0_cc3_crediterr</bit>
+    <bit pos="6">prs0_control_error</bit>
+    <bit pos="7">prs0_data_pty_err</bit>
+    <bit pos="8">prs0_rtag_misc_pty</bit>
+    <bit pos="9">prs0_rtag_pty</bit>
+    <bit pos="10">prs0_ttag_pty</bit>
+    <bit pos="11">prs0_vc0_crediterr</bit>
+    <bit pos="12">prs0_vc1_crediterr</bit>
+    <bit pos="13">prs0_link_down</bit>
+    <bit pos="16">prs1_address_pty</bit>
+    <bit pos="17">prs1_atag_pty</bit>
+    <bit pos="18">prs1_cc0_crediterr</bit>
+    <bit pos="19">prs1_cc1_crediterr</bit>
+    <bit pos="20">prs1_cc2_crediterr</bit>
+    <bit pos="21">prs1_cc3_crediterr</bit>
+    <bit pos="22">prs1_control_error</bit>
+    <bit pos="23">prs1_data_pty_err</bit>
+    <bit pos="24">prs1_rtag_misc_pty</bit>
+    <bit pos="25">prs1_rtag_pty</bit>
+    <bit pos="26">prs1_ttag_pty</bit>
+    <bit pos="27">prs1_vc0_crediterr</bit>
+    <bit pos="28">prs1_vc1_crediterr</bit>
+    <bit pos="29">prs1_link_down</bit>
+    <bit pos="32">prs2_address_pty</bit>
+    <bit pos="33">prs2_atag_pty</bit>
+    <bit pos="34">prs2_cc0_crediterr</bit>
+    <bit pos="35">prs2_cc1_crediterr</bit>
+    <bit pos="36">prs2_cc2_crediterr</bit>
+    <bit pos="37">prs2_cc3_crediterr</bit>
+    <bit pos="38">prs2_control_error</bit>
+    <bit pos="39">prs2_data_pty_err</bit>
+    <bit pos="40">prs2_rtag_misc_pty</bit>
+    <bit pos="41">prs2_rtag_pty</bit>
+    <bit pos="42">prs2_ttag_pty</bit>
+    <bit pos="43">prs2_vc0_crediterr</bit>
+    <bit pos="44">prs2_vc1_crediterr</bit>
+    <bit pos="45">prs2_link_down</bit>
+    <bit pos="48">prs3_address_pty</bit>
+    <bit pos="49">prs3_atag_pty</bit>
+    <bit pos="50">prs3_cc0_crediterr</bit>
+    <bit pos="51">prs3_cc1_crediterr</bit>
+    <bit pos="52">prs3_cc2_crediterr</bit>
+    <bit pos="53">prs3_cc3_crediterr</bit>
+    <bit pos="54">prs3_control_error</bit>
+    <bit pos="55">prs3_data_pty_err</bit>
+    <bit pos="56">prs3_rtag_misc_pty</bit>
+    <bit pos="57">prs3_rtag_pty</bit>
+    <bit pos="58">prs3_ttag_pty</bit>
+    <bit pos="59">prs3_vc0_crediterr</bit>
+    <bit pos="60">prs3_vc1_crediterr</bit>
+    <bit pos="61">prs3_link_down</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_pb_dob01_dib01_int_err.xml b/xml/p10/node_pau_pb_dob01_dib01_int_err.xml
new file mode 100644
index 0000000..a7bc58d
--- /dev/null
+++ b/xml/p10/node_pau_pb_dob01_dib01_int_err.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_DOB01_DIB01_INT_ERR" reg_type="SCOM">
+    <register name="PB_DOB01_DIB01_INT_ERR">
+        <instance reg_inst="0" addr="0x10011828" />
+        <instance reg_inst="1" addr="0x11011828" />
+        <instance reg_inst="2" addr="0x12011828" />
+        <instance reg_inst="3" addr="0x13011828" />
+    </register>
+    <rule attn_type="CS" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/>
+    </rule>
+    <rule attn_type="RE" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/>
+    </rule>
+    <rule attn_type="SPA" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB01_DIB01_INT_ERR"/>
+    </rule>
+    <bit pos="0">dob01_rtag_pbiterr</bit>
+    <bit pos="1">dob01_rtag_perr</bit>
+    <bit pos="2">dob01_misc_perr</bit>
+    <bit pos="3">dob01_f0vc0_evenperr</bit>
+    <bit pos="4">dob01_f0vc0_oddperr</bit>
+    <bit pos="5">dob01_f0vc1_evenperr</bit>
+    <bit pos="6">dob01_f0vc1_oddperr</bit>
+    <bit pos="7">dob01_f1vc0_evenperr</bit>
+    <bit pos="8">dob01_f1vc0_oddperr</bit>
+    <bit pos="9">dob01_f1vc1_evenperr</bit>
+    <bit pos="10">dob01_f1vc1_oddperr</bit>
+    <bit pos="11">dob01_f0_underflow</bit>
+    <bit pos="12">dob01_f0_overflow</bit>
+    <bit pos="13">dob01_f1_underflow</bit>
+    <bit pos="14">dob01_f1_overflow</bit>
+    <bit pos="15">dob01_vc0_underflow</bit>
+    <bit pos="16">dob01_vc0_overflow</bit>
+    <bit pos="17">dob01_vc1_underflow</bit>
+    <bit pos="18">dob01_vc1_overflow</bit>
+    <bit pos="19">dob01_f0vc0_underflow</bit>
+    <bit pos="20">dob01_f0vc0_overflow</bit>
+    <bit pos="21">dob01_f0vc1_underflow</bit>
+    <bit pos="22">dob01_f0vc1_overflow</bit>
+    <bit pos="23">dob01_f1vc0_underflow</bit>
+    <bit pos="24">dob01_f1vc0_overflow</bit>
+    <bit pos="25">dob01_f1vc1_underflow</bit>
+    <bit pos="26">dob01_f1vc1_overflow</bit>
+    <bit pos="27">dob01_vc0_prefetch_overflow</bit>
+    <bit pos="28">dob01_vc1_prefetch_overflow</bit>
+    <bit pos="29">dib01_evn0_underflow</bit>
+    <bit pos="30">dib01_evn0_overflow</bit>
+    <bit pos="31">dib01_evn1_underflow</bit>
+    <bit pos="32">dib01_evn1_overflow</bit>
+    <bit pos="33">dib01_rtag_pbiterr</bit>
+    <bit pos="34">dib01_rtag_perr</bit>
+    <bit pos="35">dib01_misc_perr</bit>
+    <bit pos="36">dib01_odd0_underflow</bit>
+    <bit pos="37">dib01_odd0_overflow</bit>
+    <bit pos="38">dib01_odd1_underflow</bit>
+    <bit pos="39">dib01_odd1_overflow</bit>
+    <bit pos="40">dib01_rtag_underflow</bit>
+    <bit pos="41">dib01_rtag_overflow</bit>
+    <bit pos="42">dib01_data_underflow</bit>
+    <bit pos="43">dib01_data_overflow</bit>
+    <bit pos="44">dib01_vc0_underflow</bit>
+    <bit pos="45">dib01_vc0_overflow</bit>
+    <bit pos="46">dib01_vc1_underflow</bit>
+    <bit pos="47">dib01_vc1_overflow</bit>
+    <bit pos="48">dib01_f0vc0_over_underflow</bit>
+    <bit pos="49">dib01_f0vc1_over_underflow</bit>
+    <bit pos="50">dib01_f1vc0_over_underflow</bit>
+    <bit pos="51">dib01_f1vc1_over_underflow</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_pb_dob23_dib23_int_err.xml b/xml/p10/node_pau_pb_dob23_dib23_int_err.xml
new file mode 100644
index 0000000..d24b7d4
--- /dev/null
+++ b/xml/p10/node_pau_pb_dob23_dib23_int_err.xml
@@ -0,0 +1,70 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_DOB23_DIB23_INT_ERR" reg_type="SCOM">
+    <register name="PB_DOB23_DIB23_INT_ERR">
+        <instance reg_inst="0" addr="0x1001182A" />
+        <instance reg_inst="1" addr="0x1101182A" />
+        <instance reg_inst="2" addr="0x1201182A" />
+        <instance reg_inst="3" addr="0x1301182A" />
+    </register>
+    <rule attn_type="CS" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB23_DIB23_INT_ERR"/>
+    </rule>
+    <rule attn_type="RE" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB23_DIB23_INT_ERR"/>
+    </rule>
+    <rule attn_type="SPA" node_inst="0:3">
+        <expr type="reg" value1="PB_DOB23_DIB23_INT_ERR"/>
+    </rule>
+    <bit pos="0">dob23_rtag_pbiterr</bit>
+    <bit pos="1">dob23_rtag_perr</bit>
+    <bit pos="2">dob23_misc_perr</bit>
+    <bit pos="3">dob23_f0vc0_evenperr</bit>
+    <bit pos="4">dob23_f0vc0_oddperr</bit>
+    <bit pos="5">dob23_f0vc1_evenperr</bit>
+    <bit pos="6">dob23_f0vc1_oddperr</bit>
+    <bit pos="7">dob23_f1vc0_evenperr</bit>
+    <bit pos="8">dob23_f1vc0_oddperr</bit>
+    <bit pos="9">dob23_f1vc1_evenperr</bit>
+    <bit pos="10">dob23_f1vc1_oddperr</bit>
+    <bit pos="11">dob23_f0_underflow</bit>
+    <bit pos="12">dob23_f0_overflow</bit>
+    <bit pos="13">dob23_f1_underflow</bit>
+    <bit pos="14">dob23_f1_overflow</bit>
+    <bit pos="15">dob23_vc0_underflow</bit>
+    <bit pos="16">dob23_vc0_overflow</bit>
+    <bit pos="17">dob23_vc1_underflow</bit>
+    <bit pos="18">dob23_vc1_overflow</bit>
+    <bit pos="19">dob23_f0vc0_underflow</bit>
+    <bit pos="20">dob23_f0vc0_overflow</bit>
+    <bit pos="21">dob23_f0vc1_underflow</bit>
+    <bit pos="22">dob23_f0vc1_overflow</bit>
+    <bit pos="23">dob23_f1vc0_underflow</bit>
+    <bit pos="24">dob23_f1vc0_overflow</bit>
+    <bit pos="25">dob23_f1vc1_underflow</bit>
+    <bit pos="26">dob23_f1vc1_overflow</bit>
+    <bit pos="27">dob23_vc0_prefetch_overflow</bit>
+    <bit pos="28">dob23_vc1_prefetch_overflow</bit>
+    <bit pos="29">dib23_evn0_underflow</bit>
+    <bit pos="30">dib23_evn0_overflow</bit>
+    <bit pos="31">dib23_evn1_underflow</bit>
+    <bit pos="32">dib23_evn1_overflow</bit>
+    <bit pos="33">dib23_rtag_pbiterr</bit>
+    <bit pos="34">dib23_rtag_perr</bit>
+    <bit pos="35">dib23_misc_perr</bit>
+    <bit pos="36">dib23_odd0_underflow</bit>
+    <bit pos="37">dib23_odd0_overflow</bit>
+    <bit pos="38">dib23_odd1_underflow</bit>
+    <bit pos="39">dib23_odd1_overflow</bit>
+    <bit pos="40">dib23_rtag_underflow</bit>
+    <bit pos="41">dib23_rtag_overflow</bit>
+    <bit pos="42">dib23_data_underflow</bit>
+    <bit pos="43">dib23_data_overflow</bit>
+    <bit pos="44">dib23_vc0_underflow</bit>
+    <bit pos="45">dib23_vc0_overflow</bit>
+    <bit pos="46">dib23_vc1_underflow</bit>
+    <bit pos="47">dib23_vc1_overflow</bit>
+    <bit pos="48">dib23_f0vc0_over_underflow</bit>
+    <bit pos="49">dib23_f0vc1_over_underflow</bit>
+    <bit pos="50">dib23_f1vc0_over_underflow</bit>
+    <bit pos="51">dib23_f1vc1_over_underflow</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_pb_fm0123_err.xml b/xml/p10/node_pau_pb_fm0123_err.xml
new file mode 100644
index 0000000..7381c73
--- /dev/null
+++ b/xml/p10/node_pau_pb_fm0123_err.xml
@@ -0,0 +1,82 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_FM0123_ERR" reg_type="SCOM">
+    <register name="PB_FM0123_ERR">
+        <instance reg_inst="0" addr="0x10011827" />
+        <instance reg_inst="1" addr="0x11011827" />
+        <instance reg_inst="2" addr="0x12011827" />
+        <instance reg_inst="3" addr="0x13011827" />
+    </register>
+    <rule attn_type="CS" node_inst="0:3">
+        <expr type="reg" value1="PB_FM0123_ERR"/>
+    </rule>
+    <rule attn_type="RE" node_inst="0:3">
+        <expr type="reg" value1="PB_FM0123_ERR"/>
+    </rule>
+    <rule attn_type="SPA" node_inst="0:3">
+        <expr type="reg" value1="PB_FM0123_ERR"/>
+    </rule>
+    <bit pos="0">fmr0_control_error</bit>
+    <bit pos="1">fmr0_addr_perr</bit>
+    <bit pos="2">fmr0_cc0_crediterr</bit>
+    <bit pos="3">fmr0_cc1_crediterr</bit>
+    <bit pos="4">fmr0_cc2_crediterr</bit>
+    <bit pos="5">fmr0_cc3_crediterr</bit>
+    <bit pos="6">fmr0_dat_hi_perr</bit>
+    <bit pos="7">fmr0_dat_lo_perr</bit>
+    <bit pos="8">fmr0_frame_crediterr</bit>
+    <bit pos="9">fmr0_internal_err</bit>
+    <bit pos="10">fmr0_prsp_ptyerr</bit>
+    <bit pos="11">fmr0_ttag_perr</bit>
+    <bit pos="12">fmr0_vc0_crediterr</bit>
+    <bit pos="13">fmr0_vc1_crediterr</bit>
+    <bit pos="14">fmr0_rtag_ptyerr</bit>
+    <bit pos="15">fmr0_rtag_misc_pty</bit>
+    <bit pos="16">fmr1_control_error</bit>
+    <bit pos="17">fmr1_addr_perr</bit>
+    <bit pos="18">fmr1_cc0_crediterr</bit>
+    <bit pos="19">fmr1_cc1_crediterr</bit>
+    <bit pos="20">fmr1_cc2_crediterr</bit>
+    <bit pos="21">fmr1_cc3_crediterr</bit>
+    <bit pos="22">fmr1_dat_hi_perr</bit>
+    <bit pos="23">fmr1_dat_lo_perr</bit>
+    <bit pos="24">fmr1_frame_crediterr</bit>
+    <bit pos="25">fmr1_internal_err</bit>
+    <bit pos="26">fmr1_prsp_ptyerr</bit>
+    <bit pos="27">fmr1_ttag_perr</bit>
+    <bit pos="28">fmr1_vc0_crediterr</bit>
+    <bit pos="29">fmr1_vc1_crediterr</bit>
+    <bit pos="30">fmr1_rtag_ptyerr</bit>
+    <bit pos="31">fmr1_rtag_misc_pty</bit>
+    <bit pos="32">fmr2_control_error</bit>
+    <bit pos="33">fmr2_addr_perr</bit>
+    <bit pos="34">fmr2_cc0_crediterr</bit>
+    <bit pos="35">fmr2_cc1_crediterr</bit>
+    <bit pos="36">fmr2_cc2_crediterr</bit>
+    <bit pos="37">fmr2_cc3_crediterr</bit>
+    <bit pos="38">fmr2_dat_hi_perr</bit>
+    <bit pos="39">fmr2_dat_lo_perr</bit>
+    <bit pos="40">fmr2_frame_crediterr</bit>
+    <bit pos="41">fmr2_internal_err</bit>
+    <bit pos="42">fmr2_prsp_ptyerr</bit>
+    <bit pos="43">fmr2_ttag_perr</bit>
+    <bit pos="44">fmr2_vc0_crediterr</bit>
+    <bit pos="45">fmr2_vc1_crediterr</bit>
+    <bit pos="46">fmr2_rtag_ptyerr</bit>
+    <bit pos="47">fmr2_rtag_misc_pty</bit>
+    <bit pos="48">fmr3_control_error</bit>
+    <bit pos="49">fmr3_addr_perr</bit>
+    <bit pos="50">fmr3_cc0_crediterr</bit>
+    <bit pos="51">fmr3_cc1_crediterr</bit>
+    <bit pos="52">fmr3_cc2_crediterr</bit>
+    <bit pos="53">fmr3_cc3_crediterr</bit>
+    <bit pos="54">fmr3_dat_hi_perr</bit>
+    <bit pos="55">fmr3_dat_lo_perr</bit>
+    <bit pos="56">fmr3_frame_crediterr</bit>
+    <bit pos="57">fmr3_internal_err</bit>
+    <bit pos="58">fmr3_prsp_ptyerr</bit>
+    <bit pos="59">fmr3_ttag_perr</bit>
+    <bit pos="60">fmr3_vc0_crediterr</bit>
+    <bit pos="61">fmr3_vc1_crediterr</bit>
+    <bit pos="62">fmr3_rtag_ptyerr</bit>
+    <bit pos="63">fmr3_rtag_misc_pty</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_ptl_fir.xml b/xml/p10/node_pau_ptl_fir.xml
index 4086969..d6cb342 100644
--- a/xml/p10/node_pau_ptl_fir.xml
+++ b/xml/p10/node_pau_ptl_fir.xml
@@ -9,6 +9,36 @@
         <action attn_type="RE" config="01"/>
         <action attn_type="SPA" config="10"/>
     </local_fir>
+    <register name="PB_TL_LINK_SYN_01">
+        <instance reg_inst="0" addr="0x10011812" />
+        <instance reg_inst="1" addr="0x11011812" />
+        <instance reg_inst="2" addr="0x12011812" />
+        <instance reg_inst="3" addr="0x13011812" />
+    </register>
+    <register name="PB_TL_LINK_SYN_23">
+        <instance reg_inst="0" addr="0x10011813" />
+        <instance reg_inst="1" addr="0x11011813" />
+        <instance reg_inst="2" addr="0x12011813" />
+        <instance reg_inst="3" addr="0x13011813" />
+    </register>
+    <register name="PB_EN_DOB_ECC_ERR">
+        <instance reg_inst="0" addr="0x10011818" />
+        <instance reg_inst="1" addr="0x11011818" />
+        <instance reg_inst="2" addr="0x12011818" />
+        <instance reg_inst="3" addr="0x13011818" />
+    </register>
+    <register name="PB_MISC_CFG">
+        <instance reg_inst="0" addr="0x10011825" />
+        <instance reg_inst="1" addr="0x11011825" />
+        <instance reg_inst="2" addr="0x12011825" />
+        <instance reg_inst="3" addr="0x13011825" />
+    </register>
+    <capture_group node_inst="0:3">
+        <capture_register reg_name="PB_TL_LINK_SYN_01" reg_inst="0:3" />
+        <capture_register reg_name="PB_TL_LINK_SYN_23" reg_inst="0:3" />
+        <capture_register reg_name="PB_EN_DOB_ECC_ERR" reg_inst="0:3" />
+        <capture_register reg_name="PB_MISC_CFG"       reg_inst="0:3" />
+    </capture_group>
     <bit pos="0">fmr00 trained. Even PTL, even half.</bit>
     <bit pos="1">fmr01 trained. Even PTL, odd half.</bit>
     <bit pos="2">fmr02 trained. Odd PTL, even half.</bit>
@@ -16,35 +46,35 @@
     <bit pos="4">dob01 ue</bit>
     <bit pos="5">dob01 ce</bit>
     <bit pos="6">dob01 sue</bit>
-    <bit pos="7">data outbound switch internal error - even PTL.</bit>
+    <bit pos="7" child_node="PB_DOB01_DIB01_INT_ERR" node_inst="0:3">data outbound switch internal error - even PTL.</bit>
     <bit pos="8">dob23 ue</bit>
     <bit pos="9">dob23 ce</bit>
     <bit pos="10">dob23 sue</bit>
-    <bit pos="11">data outbound switch internal error - odd PTL.</bit>
-    <bit pos="12">Even PTL, even framer internal error</bit>
+    <bit pos="11" child_node="PB_DOB23_DIB23_INT_ERR" node_inst="0:3">data outbound switch internal error - odd PTL.</bit>
+    <bit pos="12" child_node="PB_FM0123_ERR" node_inst="0:3">Even PTL, even framer internal error</bit>
     <bit pos="13">Even PTL, outbound switch cmd/presp/cresp internal error</bit>
-    <bit pos="14">Even PTL, odd framer internal error</bit>
-    <bit pos="15">Odd PTL, even framer internal error</bit>
+    <bit pos="14" child_node="PB_FM0123_ERR" node_inst="0:3">Even PTL, odd framer internal error</bit>
+    <bit pos="15" child_node="PB_FM0123_ERR" node_inst="0:3">Odd PTL, even framer internal error</bit>
     <bit pos="16">Odd PTL, outbound switch cmd/presp/cresp internal error</bit>
-    <bit pos="17">Odd PTL, odd framer internal error</bit>
-    <bit pos="18">Even PTL, even parser internal error</bit>
-    <bit pos="19">Even PTL, odd parser internal error</bit>
-    <bit pos="20">Odd PTL, even parser internal error</bit>
-    <bit pos="21">Odd PTL, odd parser internal error</bit>
+    <bit pos="17" child_node="PB_FM0123_ERR" node_inst="0:3">Odd PTL, odd framer internal error</bit>
+    <bit pos="18" child_node="PB_PR0123_ERR" node_inst="0:3">Even PTL, even parser internal error</bit>
+    <bit pos="19" child_node="PB_PR0123_ERR" node_inst="0:3">Even PTL, odd parser internal error</bit>
+    <bit pos="20" child_node="PB_PR0123_ERR" node_inst="0:3">Odd PTL, even parser internal error</bit>
+    <bit pos="21" child_node="PB_PR0123_ERR" node_inst="0:3">Odd PTL, odd parser internal error</bit>
     <bit pos="22">Even PTL, even link down</bit>
     <bit pos="23">Even PTL, odd link down</bit>
     <bit pos="24">Odd PTL, even link down</bit>
     <bit pos="25">Odd PTL, odd link down</bit>
-    <bit pos="26">Even PTL data inbound switch internal error</bit>
-    <bit pos="27">Odd PTL data inbound switch internal error</bit>
-    <bit pos="28">mailbox 00 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_00_REG.</bit>
-    <bit pos="29">mailbox 01 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_01_REG.</bit>
-    <bit pos="30">mailbox 10 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_10_REG.</bit>
-    <bit pos="31">mailbox 11 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_11_REG.</bit>
-    <bit pos="32">mailbox 20 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_20_REG.</bit>
-    <bit pos="33">mailbox 21 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_21_REG.</bit>
-    <bit pos="34">mailbox 30 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_30_REG.</bit>
-    <bit pos="35">mailbox 31 special attention. Gets set to 1 when a remote chip writes PB_MAILBOX_31_REG.</bit>
+    <bit pos="26" child_node="PB_DOB01_DIB01_INT_ERR" node_inst="0:3">Even PTL data inbound switch internal error</bit>
+    <bit pos="27" child_node="PB_DOB23_DIB23_INT_ERR" node_inst="0:3">Odd PTL data inbound switch internal error</bit>
+    <bit pos="28">mailbox 00 special attention</bit>
+    <bit pos="29">mailbox 01 special attention</bit>
+    <bit pos="30">mailbox 10 special attention</bit>
+    <bit pos="31">mailbox 11 special attention</bit>
+    <bit pos="32">mailbox 20 special attention</bit>
+    <bit pos="33">mailbox 21 special attention</bit>
+    <bit pos="34">mailbox 30 special attention</bit>
+    <bit pos="35">mailbox 31 special attention</bit>
     <bit pos="36">ptl0 spare</bit>
     <bit pos="37">ptl1 spare</bit>
     <bit pos="38">ptl2 spare</bit>