#include "simulator.hpp"

START_TEST_CASE(SampleTestSet1)

CHIP(proc0, SAMPLE)
CHIP(proc1, SAMPLE)

START_ITERATION

REG_SCOM(proc0, 0xf0000000, 0x0000000000000000) // GFIR_CS
REG_SCOM(proc0, 0xf0000001, 0x0000000000000000) // GFIR_RE

REG_SCOM(proc0, 0x00f00000, 0x0000000000000000) // CFIR0_CS   inst 0
REG_SCOM(proc0, 0x00f00001, 0x0000000000000000) // CFIR0_RE   inst 0
REG_SCOM(proc0, 0x00f00002, 0x0000000000000000) // CFIR0_MASK inst 0

REG_SCOM(proc0, 0x00f00010, 0x0000000000000000) // CFIR0_CS   inst 1
REG_SCOM(proc0, 0x00f00011, 0x0000000000000000) // CFIR0_RE   inst 1
REG_SCOM(proc0, 0x00f00012, 0x0000000000000000) // CFIR0_MASK inst 1

REG_SCOM(proc0, 0x00f10000, 0x0000000000000000) // CFIR1_CS   inst 0
REG_SCOM(proc0, 0x00f10001, 0x0000000000000000) // CFIR1_RE   inst 0
REG_SCOM(proc0, 0x00f10002, 0x0000000000000000) // CFIR1_MASK inst 0

REG_SCOM(proc0, 0x0000f000, 0x0000000000000000) // LFIR0      inst 0
REG_SCOM(proc0, 0x0000f003, 0x0000000000000000) // LFIR0_MASK inst 0
REG_SCOM(proc0, 0x0000f006, 0x0000000000000000) // LFIR0_ACT0 inst 0
REG_SCOM(proc0, 0x0000f007, 0x0000000000000000) // LFIR0_ACT1 inst 0

REG_SCOM(proc0, 0x0000f010, 0x0000000000000000) // LFIR0      inst 1
REG_SCOM(proc0, 0x0000f013, 0x0000000000000000) // LFIR0_MASK inst 1
REG_SCOM(proc0, 0x0000f016, 0x0000000000000000) // LFIR0_ACT0 inst 1
REG_SCOM(proc0, 0x0000f017, 0x0000000000000000) // LFIR0_ACT1 inst 1

REG_SCOM(proc0, 0x0000f100, 0x0000000000000000) // LFIR1      inst 0
REG_SCOM(proc0, 0x0000f103, 0x0000000000000000) // LFIR1_MASK inst 0
REG_SCOM(proc0, 0x0000f106, 0x0000000000000000) // LFIR1_ACT0 inst 0
REG_SCOM(proc0, 0x0000f107, 0x0000000000000000) // LFIR1_ACT1 inst 0

REG_SCOM(proc0, 0x0000f110, 0x0000000000000000) // LFIR1      inst 1
REG_SCOM(proc0, 0x0000f113, 0x0000000000000000) // LFIR1_MASK inst 1
REG_SCOM(proc0, 0x0000f116, 0x0000000000000000) // LFIR1_ACT0 inst 1
REG_SCOM(proc0, 0x0000f117, 0x0000000000000000) // LFIR1_ACT1 inst 1

REG_SCOM(proc0, 0x0000f120, 0x0000000000000000) // LFIR1      inst 2
REG_SCOM(proc0, 0x0000f123, 0x0000000000000000) // LFIR1_MASK inst 2
REG_SCOM(proc0, 0x0000f126, 0x0000000000000000) // LFIR1_ACT0 inst 2
REG_SCOM(proc0, 0x0000f127, 0x0000000000000000) // LFIR1_ACT1 inst 2

REG_SCOM(proc0, 0x0000f130, 0x0000000000000000) // LFIR1      inst 3
REG_SCOM(proc0, 0x0000f133, 0x0000000000000000) // LFIR1_MASK inst 3
REG_SCOM(proc0, 0x0000f136, 0x0000000000000000) // LFIR1_ACT0 inst 3
REG_SCOM(proc0, 0x0000f137, 0x0000000000000000) // LFIR1_ACT1 inst 3

REG_SCOM(proc0, 0x0000f140, 0x0000000000000000) // LFIR1      inst 4
REG_SCOM(proc0, 0x0000f143, 0x0000000000000000) // LFIR1_MASK inst 4
REG_SCOM(proc0, 0x0000f146, 0x0000000000000000) // LFIR1_ACT0 inst 4
REG_SCOM(proc0, 0x0000f147, 0x0000000000000000) // LFIR1_ACT1 inst 4

REG_SCOM(proc0, 0x0000f150, 0x0000000000000000) // LFIR1      inst 5
REG_SCOM(proc0, 0x0000f153, 0x0000000000000000) // LFIR1_MASK inst 5
REG_SCOM(proc0, 0x0000f156, 0x0000000000000000) // LFIR1_ACT0 inst 5
REG_SCOM(proc0, 0x0000f157, 0x0000000000000000) // LFIR1_ACT1 inst 5

REG_SCOM(proc0, 0x0000f200, 0x0000000000000000) // LFIR2      inst 0
REG_SCOM(proc0, 0x0000f203, 0x0000000000000000) // LFIR2_MASK inst 0
REG_SCOM(proc0, 0x0000f206, 0x0000000000000000) // LFIR2_ACT0 inst 0
REG_SCOM(proc0, 0x0000f207, 0x0000000000000000) // LFIR2_ACT1 inst 0

// TODO
// EXP_SIG(proc0, 0x2222, 0, 0, CHECKSTOP)

END_ITERATION

END_TEST_CASE