Update P10 chip data XML
Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ia864d6b7cb6bea6f245c0794687b0d32f2a3691c
diff --git a/xml/p10/node_cfir_pauw_cs_re_p10_10.xml b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
new file mode 100644
index 0000000..73a16cb
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_CS_RE" reg_type="SCOM">
+ <register name="CFIR_PAUW_XSTOP">
+ <instance addr="0x12040000" reg_inst="0"/>
+ <instance addr="0x13040000" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_XSTOP_MASK">
+ <instance addr="0x12040040" reg_inst="0"/>
+ <instance addr="0x13040040" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_RECOV">
+ <instance addr="0x12040001" reg_inst="0"/>
+ <instance addr="0x13040001" reg_inst="1"/>
+ </register>
+ <register name="CFIR_PAUW_RECOV_MASK">
+ <instance addr="0x12040041" reg_inst="0"/>
+ <instance addr="0x13040041" reg_inst="1"/>
+ </register>
+ <rule attn_type="CS" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_XSTOP"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_XSTOP_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <rule attn_type="RE" node_inst="0:1">
+ <expr type="and">
+ <expr type="reg" value1="CFIR_PAUW_RECOV"/>
+ <expr type="not">
+ <expr type="reg" value1="CFIR_PAUW_RECOV_MASK"/>
+ </expr>
+ <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+ </expr>
+ </rule>
+ <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+ <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
+ <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
+ <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
+ <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+ <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+</attn_node>