commit f8a726b7cf54ad457aff25389db1c43fc277c13d
author Zane Shelley <zshelle@us.ibm.com> Wed Dec 16 21:29:32 2020 -0600
committer Zane Shelley <zshelle@us.ibm.com> Wed Dec 16 21:49:10 2020 -0600
tree 444538860cb96e9bb451c4389ccad5baef418cbd
parent d280cca793349d2cd06efbbef5db65c9bae34b98

Update P10 chip data XML

Signed-off-by: Zane Shelley <zshelle@us.ibm.com>
Change-Id: Ia864d6b7cb6bea6f245c0794687b0d32f2a3691c

xml/p10/node_tp_local_fir.xml

diff --git a/xml/p10/node_tp_local_fir.xml b/xml/p10/node_tp_local_fir.xml
index 6c82c2f..ba5bf15 100644
--- a/xml/p10/node_tp_local_fir.xml
+++ b/xml/p10/node_tp_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="TP_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="TP_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="TP_LOCAL_FIR">
         <instance addr="0x01040100" reg_inst="0"/>
         <action attn_type="CS" config="000"/>
@@ -10,11 +10,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
@@ -31,12 +31,12 @@
     <bit pos="20">Trace00 - scom parity err</bit>
     <bit pos="21">ITR - FMU error</bit>
     <bit pos="22">ITR - PCB error</bit>
-    <bit pos="23">PCB Master - timeout - read and clear 000F001F - RECOV</bit>
-    <bit pos="24">I2CM - Parity errors, Can be considered as recoverable error</bit>
+    <bit pos="23">PCB Master - timeout</bit>
+    <bit pos="24">I2CM - Parity errors</bit>
     <bit pos="25">TOD - any error</bit>
     <bit pos="26">TOD - access error PIB</bit>
     <bit pos="27">TOD - unused tie0</bit>
-    <bit pos="28">PCB Slave - read and clear nn0F001F RECOV</bit>
+    <bit pos="28">Error reported from one or more PCB Slaves</bit>
     <bit pos="29">SBE - PPE int hardware error</bit>
     <bit pos="30">SBE - PPE ext hardware error</bit>
     <bit pos="31">SBE- PPE code error</bit>
@@ -46,23 +46,23 @@
     <bit pos="35">SBE - unused tie0</bit>
     <bit pos="36">SBE - unused tie0</bit>
     <bit pos="37">SBE - PPE triggers DBG</bit>
-    <bit pos="38">OTP - SCOM access errors &amp; single ecc correctable errors. Can be considered as Recoverable type.</bit>
+    <bit pos="38">OTP - SCOM access errors &amp; single ecc correctable errors</bit>
     <bit pos="39">TPIO External Trigger</bit>
-    <bit pos="40">PCB Master - DECMCAST_GRP_ERR - read and clear 000F001F - RECOV</bit>
-    <bit pos="41">PCB Master - Parity ERR - read and clear 000F001F - RECOV</bit>
+    <bit pos="40">PCB Master - Multicast group member count underrun (MC misconfig)</bit>
+    <bit pos="41">PCB Master - Parity ERR</bit>
     <bit pos="42">RCS - OSC0 Error</bit>
     <bit pos="43">RCS - OSC1 Error</bit>
-    <bit pos="44">RCS - Delay line 0 unlock</bit>
-    <bit pos="45">RCS - Delay line 1 unlock</bit>
+    <bit pos="44">RCS - Up/down counter A unlock</bit>
+    <bit pos="45">RCS - Up/down counter B unlock</bit>
     <bit pos="46">PIBMEM</bit>
     <bit pos="47">PIBMEM</bit>
-    <bit pos="48">OTP - Combination of ecc uncorrectable error and correctable error counter overflow - Can be considered as checkstop</bit>
-    <bit pos="49">DPLL_FIR_NEST_DCO_EMPTY</bit>
-    <bit pos="50">DPLL_FIR_NEST_DCO_FULL</bit>
-    <bit pos="51">DPLL_FIR_NEST_INT_ERROR</bit>
-    <bit pos="52">DPLL_FIR_PAU_DCO_EMPTY</bit>
-    <bit pos="53">DPLL_FIR_PAU_DCO_FULL</bit>
-    <bit pos="54">DPLL_FIR_PAU_INT_ERROR</bit>
+    <bit pos="48">OTP - ECC UE or CE count overflow</bit>
+    <bit pos="49">Nest DPLL: DCO empty</bit>
+    <bit pos="50">Nest DPLL: DCO full</bit>
+    <bit pos="51">Nest DPLL: internal error</bit>
+    <bit pos="52">PAU DPLL: DCO empty</bit>
+    <bit pos="53">PAU DPLL: DCO full</bit>
+    <bit pos="54">PAU DPLL: internal error</bit>
     <bit pos="55">SPI Master 0 Err</bit>
     <bit pos="56">SPI Master 1 Err</bit>
     <bit pos="57">SPI Master 2 Err</bit>