diff --git a/xml/build_chip_data_binary b/xml/build_chip_data_binary
index c6dc0c7..2844fd5 100755
--- a/xml/build_chip_data_binary
+++ b/xml/build_chip_data_binary
@@ -31,6 +31,7 @@
     EXPLORER_11 => 0x60D20011, # Explorer Chip DD1.0
     EXPLORER_20 => 0x60D20020, # Explorer Chip DD1.0
     P10_10      => 0x20DA0010, # P10 Chip DD1.0
+    P10_20      => 0x20DA0020, # P10 Chip DD2.0
 };
 
 # All models/ECs that may exist in the XML, but no longer needs to be built.
diff --git a/xml/chip_data_xml.md b/xml/chip_data_xml.md
index 96cbfed..d7d839a 100644
--- a/xml/chip_data_xml.md
+++ b/xml/chip_data_xml.md
@@ -415,6 +415,7 @@
 | `EXPLORER_11` | Explorer chip EC 1.1 |
 | `EXPLORER_20` | Explorer chip EC 2.0 |
 | `P10_10`      | P10 chip EC 1.0      |
+| `P10_20`      | P10 chip EC 2.0      |
 
 ### 3.4) Supported Attention Types
 
diff --git a/xml/p10/chip_p10.xml b/xml/p10/chip_p10.xml
index f598f33..d019d34 100644
--- a/xml/p10/chip_p10.xml
+++ b/xml/p10/chip_p10.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<chip model_ec="P10_10" name="P10">
+<chip model_ec="P10_10,P10_20" name="P10">
     <attn_tree attn_type="CS" node_inst="0" root_node="GFIR_CS"/>
     <attn_tree attn_type="RE" node_inst="0" root_node="GFIR_RE"/>
     <attn_tree attn_type="SPA" node_inst="0" root_node="GFIR_SPA"/>
diff --git a/xml/p10/node_cfir_eq_cs.xml b/xml/p10/node_cfir_eq_cs.xml
index 8aa6162..f5b3ee3 100644
--- a/xml/p10/node_cfir_eq_cs.xml
+++ b/xml/p10/node_cfir_eq_cs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_EQ_CS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_CS" reg_type="SCOM">
     <register name="CFIR_EQ_XSTOP">
         <instance addr="0x20040000" reg_inst="0"/>
         <instance addr="0x21040000" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_eq_ha.xml b/xml/p10/node_cfir_eq_ha.xml
index 00cf785..23383ee 100644
--- a/xml/p10/node_cfir_eq_ha.xml
+++ b/xml/p10/node_cfir_eq_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_EQ_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_HA" reg_type="SCOM">
     <register name="CFIR_EQ_HOSTATTN">
         <instance addr="0x20040004" reg_inst="0"/>
         <instance addr="0x21040004" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_eq_re.xml b/xml/p10/node_cfir_eq_re.xml
index 180691a..b60b24c 100644
--- a/xml/p10/node_cfir_eq_re.xml
+++ b/xml/p10/node_cfir_eq_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_EQ_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_RE" reg_type="SCOM">
     <register name="CFIR_EQ_RECOV">
         <instance addr="0x20040001" reg_inst="0"/>
         <instance addr="0x21040001" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_eq_spa.xml b/xml/p10/node_cfir_eq_spa.xml
index c2d544b..5d01d14 100644
--- a/xml/p10/node_cfir_eq_spa.xml
+++ b/xml/p10/node_cfir_eq_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_EQ_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_SPA" reg_type="SCOM">
     <register name="CFIR_EQ_SPATTN">
         <instance addr="0x20040002" reg_inst="0"/>
         <instance addr="0x21040002" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_eq_ucs.xml b/xml/p10/node_cfir_eq_ucs.xml
index 6220245..dc54940 100644
--- a/xml/p10/node_cfir_eq_ucs.xml
+++ b/xml/p10/node_cfir_eq_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_EQ_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_EQ_UCS" reg_type="SCOM">
     <register name="CFIR_EQ_LOCAL_XSTOP">
         <instance addr="0x20040003" reg_inst="0"/>
         <instance addr="0x21040003" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_iohs_cs_re_spa.xml b/xml/p10/node_cfir_iohs_cs_re_spa.xml
index d3153ac..568188e 100644
--- a/xml/p10/node_cfir_iohs_cs_re_spa.xml
+++ b/xml/p10/node_cfir_iohs_cs_re_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_IOHS_CS_RE_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_CS_RE_SPA" reg_type="SCOM">
     <register name="CFIR_IOHS_XSTOP">
         <instance addr="0x18040000" reg_inst="0"/>
         <instance addr="0x19040000" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_iohs_ucs_ha.xml b/xml/p10/node_cfir_iohs_ucs_ha.xml
index cf8f9cc..9959a20 100644
--- a/xml/p10/node_cfir_iohs_ucs_ha.xml
+++ b/xml/p10/node_cfir_iohs_ucs_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_IOHS_UCS_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_IOHS_UCS_HA" reg_type="SCOM">
     <register name="CFIR_IOHS_LOCAL_XSTOP">
         <instance addr="0x18040003" reg_inst="0"/>
         <instance addr="0x19040003" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_mc_cs_re_spa.xml b/xml/p10/node_cfir_mc_cs_re_spa.xml
index 2bf05f9..0dd2c05 100644
--- a/xml/p10/node_cfir_mc_cs_re_spa.xml
+++ b/xml/p10/node_cfir_mc_cs_re_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_MC_CS_RE_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_CS_RE_SPA" reg_type="SCOM">
     <register name="CFIR_MC_XSTOP">
         <instance addr="0x0C040000" reg_inst="0"/>
         <instance addr="0x0D040000" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_mc_ucs_ha.xml b/xml/p10/node_cfir_mc_ucs_ha.xml
index 3934db8..37c27ed 100644
--- a/xml/p10/node_cfir_mc_ucs_ha.xml
+++ b/xml/p10/node_cfir_mc_ucs_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_MC_UCS_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_MC_UCS_HA" reg_type="SCOM">
     <register name="CFIR_MC_LOCAL_XSTOP">
         <instance addr="0x0C040003" reg_inst="0"/>
         <instance addr="0x0D040003" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_n0_cs_re.xml b/xml/p10/node_cfir_n0_cs_re.xml
index 1df737a..845b897 100644
--- a/xml/p10/node_cfir_n0_cs_re.xml
+++ b/xml/p10/node_cfir_n0_cs_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N0_CS_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N0_CS_RE" reg_type="SCOM">
     <register name="CFIR_N0_XSTOP">
         <instance addr="0x02040000" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_n0_ha.xml b/xml/p10/node_cfir_n0_ha.xml
index 496223f..f912397 100644
--- a/xml/p10/node_cfir_n0_ha.xml
+++ b/xml/p10/node_cfir_n0_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N0_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N0_HA" reg_type="SCOM">
     <register name="CFIR_N0_HOSTATTN">
         <instance addr="0x02040004" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_n0_spa.xml b/xml/p10/node_cfir_n0_spa.xml
index 573d748..63aa866 100644
--- a/xml/p10/node_cfir_n0_spa.xml
+++ b/xml/p10/node_cfir_n0_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N0_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N0_SPA" reg_type="SCOM">
     <register name="CFIR_N0_SPATTN">
         <instance addr="0x02040002" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_n0_ucs.xml b/xml/p10/node_cfir_n0_ucs.xml
index 6fe76a4..93c5b18 100644
--- a/xml/p10/node_cfir_n0_ucs.xml
+++ b/xml/p10/node_cfir_n0_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N0_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N0_UCS" reg_type="SCOM">
     <register name="CFIR_N0_LOCAL_XSTOP">
         <instance addr="0x02040003" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_n1_cs.xml b/xml/p10/node_cfir_n1_cs.xml
index c5492b1..253bb52 100644
--- a/xml/p10/node_cfir_n1_cs.xml
+++ b/xml/p10/node_cfir_n1_cs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N1_CS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N1_CS" reg_type="SCOM">
     <register name="CFIR_N1_XSTOP">
         <instance addr="0x03040000" reg_inst="0"/>
     </register>
@@ -24,22 +24,22 @@
     <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
     <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
     <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
     <bit child_node="PB_EXT_FIR" node_inst="0" pos="33">PowerBus EH EXTFIR register</bit>
     <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
     <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register.  Register bits are set for any error condition detected by the PBA.  The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
diff --git a/xml/p10/node_cfir_n1_ha.xml b/xml/p10/node_cfir_n1_ha.xml
index 8dd5dd7..09b2150 100644
--- a/xml/p10/node_cfir_n1_ha.xml
+++ b/xml/p10/node_cfir_n1_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N1_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N1_HA" reg_type="SCOM">
     <register name="CFIR_N1_HOSTATTN">
         <instance addr="0x03040004" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_n1_re.xml b/xml/p10/node_cfir_n1_re.xml
index d565d0e..6e8d74a 100644
--- a/xml/p10/node_cfir_n1_re.xml
+++ b/xml/p10/node_cfir_n1_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N1_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N1_RE" reg_type="SCOM">
     <register name="CFIR_N1_RECOV">
         <instance addr="0x03040001" reg_inst="0"/>
     </register>
@@ -24,22 +24,22 @@
     <bit child_node="PCI_NEST_FIR" node_inst="0" pos="13">PCI Nest FIR Register</bit>
     <bit child_node="PCI_NEST_FIR" node_inst="1" pos="14">PCI Nest FIR Register</bit>
     <bit child_node="PCI_NEST_FIR" node_inst="2" pos="15">PCI Nest FIR Register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
     <bit child_node="PSIHB_FIR" node_inst="0" pos="38">PSI Host Bridge FIR Register</bit>
     <bit child_node="PBAF_FIR" node_inst="0" pos="39">PBA Local Fault Isolation Register.  Register bits are set for any error condition detected by the PBA.  The PBAFIR will freeze upon logging the first error not masked in PBAFIRMASK.</bit>
 </attn_node>
diff --git a/xml/p10/node_cfir_n1_spa.xml b/xml/p10/node_cfir_n1_spa.xml
index d7a2ca7..97dfd93 100644
--- a/xml/p10/node_cfir_n1_spa.xml
+++ b/xml/p10/node_cfir_n1_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N1_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N1_SPA" reg_type="SCOM">
     <register name="CFIR_N1_SPATTN">
         <instance addr="0x03040002" reg_inst="0"/>
     </register>
@@ -17,20 +17,20 @@
     </rule>
     <bit child_node="N1_LOCAL_FIR" node_inst="0" pos="4">Local FIR</bit>
     <bit child_node="MCD_FIR" node_inst="0" pos="7">Local FIR register for MCD</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="4" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="5" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="6" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="7" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="8" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="9" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="10" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="11" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="1" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="2" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="3" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="12" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="13" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="14" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
-    <bit child_node="PB_STATION_FIR" node_inst="15" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="0" pos="17">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="1" pos="18">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="2" pos="19">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="3" pos="20">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="4" pos="21">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="5" pos="22">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="6" pos="23">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EQ" node_inst="7" pos="24">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN1" node_inst="0" pos="25">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN2" node_inst="0" pos="26">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN3" node_inst="0" pos="27">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_EN4" node_inst="0" pos="28">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES1" node_inst="0" pos="29">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES2" node_inst="0" pos="30">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES3" node_inst="0" pos="31">PowerBus PB RaceTrack Station nest domain FIR register</bit>
+    <bit child_node="PB_STATION_FIR_ES4" node_inst="0" pos="32">PowerBus PB RaceTrack Station nest domain FIR register</bit>
 </attn_node>
diff --git a/xml/p10/node_cfir_n1_ucs.xml b/xml/p10/node_cfir_n1_ucs.xml
index 11220f3..4a57ccf 100644
--- a/xml/p10/node_cfir_n1_ucs.xml
+++ b/xml/p10/node_cfir_n1_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_N1_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_N1_UCS" reg_type="SCOM">
     <register name="CFIR_N1_LOCAL_XSTOP">
         <instance addr="0x03040003" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_paue_cs_re.xml b/xml/p10/node_cfir_paue_cs_re.xml
index a1bcb5a..81967a2 100644
--- a/xml/p10/node_cfir_paue_cs_re.xml
+++ b/xml/p10/node_cfir_paue_cs_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUE_CS_RE" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUE_CS_RE" reg_type="SCOM">
     <register name="CFIR_PAUE_XSTOP">
         <instance addr="0x10040000" reg_inst="0"/>
         <instance addr="0x11040000" reg_inst="1"/>
@@ -39,6 +39,5 @@
     <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
     <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
     <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
 </attn_node>
diff --git a/xml/p10/node_cfir_paue_cs_re_p10_10.xml b/xml/p10/node_cfir_paue_cs_re_p10_10.xml
new file mode 100644
index 0000000..a1bcb5a
--- /dev/null
+++ b/xml/p10/node_cfir_paue_cs_re_p10_10.xml
@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_CS_RE" reg_type="SCOM">
+    <register name="CFIR_PAUE_XSTOP">
+        <instance addr="0x10040000" reg_inst="0"/>
+        <instance addr="0x11040000" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUE_XSTOP_MASK">
+        <instance addr="0x10040040" reg_inst="0"/>
+        <instance addr="0x11040040" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUE_RECOV">
+        <instance addr="0x10040001" reg_inst="0"/>
+        <instance addr="0x11040001" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUE_RECOV_MASK">
+        <instance addr="0x10040041" reg_inst="0"/>
+        <instance addr="0x11040041" reg_inst="1"/>
+    </register>
+    <rule attn_type="CS" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUE_XSTOP"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUE_XSTOP_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUE_RECOV"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUE_RECOV_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+    <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_ha.xml b/xml/p10/node_cfir_paue_ha.xml
index fe5fc3d..089d3c4 100644
--- a/xml/p10/node_cfir_paue_ha.xml
+++ b/xml/p10/node_cfir_paue_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUE_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PAUE_HA" reg_type="SCOM">
     <register name="CFIR_PAUE_HOSTATTN">
         <instance addr="0x10040004" reg_inst="0"/>
         <instance addr="0x11040004" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_paue_spa.xml b/xml/p10/node_cfir_paue_spa.xml
index b173b23..71c2552 100644
--- a/xml/p10/node_cfir_paue_spa.xml
+++ b/xml/p10/node_cfir_paue_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUE_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUE_SPA" reg_type="SCOM">
     <register name="CFIR_PAUE_SPATTN">
         <instance addr="0x10040002" reg_inst="0"/>
         <instance addr="0x11040002" reg_inst="1"/>
@@ -19,6 +19,5 @@
     </rule>
     <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
     <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
 </attn_node>
diff --git a/xml/p10/node_cfir_paue_spa_p10_10.xml b/xml/p10/node_cfir_paue_spa_p10_10.xml
new file mode 100644
index 0000000..b173b23
--- /dev/null
+++ b/xml/p10/node_cfir_paue_spa_p10_10.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_SPA" reg_type="SCOM">
+    <register name="CFIR_PAUE_SPATTN">
+        <instance addr="0x10040002" reg_inst="0"/>
+        <instance addr="0x11040002" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUE_SPATTN_MASK">
+        <instance addr="0x10040042" reg_inst="0"/>
+        <instance addr="0x11040042" reg_inst="1"/>
+    </register>
+    <rule attn_type="SPA" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUE_SPATTN"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUE_SPATTN_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_PTL_FIR" node_inst="0,1" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_paue_ucs.xml b/xml/p10/node_cfir_paue_ucs.xml
index efac4df..9f31ee3 100644
--- a/xml/p10/node_cfir_paue_ucs.xml
+++ b/xml/p10/node_cfir_paue_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUE_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUE_UCS" reg_type="SCOM">
     <register name="CFIR_PAUE_LOCAL_XSTOP">
         <instance addr="0x10040003" reg_inst="0"/>
         <instance addr="0x11040003" reg_inst="1"/>
@@ -22,5 +22,4 @@
     <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
     <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
 </attn_node>
diff --git a/xml/p10/node_cfir_paue_ucs_p10_10.xml b/xml/p10/node_cfir_paue_ucs_p10_10.xml
new file mode 100644
index 0000000..efac4df
--- /dev/null
+++ b/xml/p10/node_cfir_paue_ucs_p10_10.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUE_UCS" reg_type="SCOM">
+    <register name="CFIR_PAUE_LOCAL_XSTOP">
+        <instance addr="0x10040003" reg_inst="0"/>
+        <instance addr="0x11040003" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUE_LOCAL_XSTOP_MASK">
+        <instance addr="0x10040043" reg_inst="0"/>
+        <instance addr="0x11040043" reg_inst="1"/>
+    </register>
+    <rule attn_type="UCS" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUE_LOCAL_XSTOP"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUE_LOCAL_XSTOP_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="0,1" pos="4">Local FIR</bit>
+    <bit child_node="PAU_FIR_0" node_inst="0,3" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="0,3" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="0,3" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="0,1" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="0,1" pos="14">Local FIR register for the chip pervasive logic</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_cs_re.xml b/xml/p10/node_cfir_pauw_cs_re.xml
index 73a16cb..2ab3794 100644
--- a/xml/p10/node_cfir_pauw_cs_re.xml
+++ b/xml/p10/node_cfir_pauw_cs_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUW_CS_RE" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUW_CS_RE" reg_type="SCOM">
     <register name="CFIR_PAUW_XSTOP">
         <instance addr="0x12040000" reg_inst="0"/>
         <instance addr="0x13040000" reg_inst="1"/>
@@ -42,6 +42,5 @@
     <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
     <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
     <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
 </attn_node>
diff --git a/xml/p10/node_cfir_pauw_cs_re_p10_10.xml b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
new file mode 100644
index 0000000..73a16cb
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_cs_re_p10_10.xml
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_CS_RE" reg_type="SCOM">
+    <register name="CFIR_PAUW_XSTOP">
+        <instance addr="0x12040000" reg_inst="0"/>
+        <instance addr="0x13040000" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUW_XSTOP_MASK">
+        <instance addr="0x12040040" reg_inst="0"/>
+        <instance addr="0x13040040" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUW_RECOV">
+        <instance addr="0x12040001" reg_inst="0"/>
+        <instance addr="0x13040001" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUW_RECOV_MASK">
+        <instance addr="0x12040041" reg_inst="0"/>
+        <instance addr="0x13040041" reg_inst="1"/>
+    </register>
+    <rule attn_type="CS" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUW_XSTOP"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUW_XSTOP_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUW_RECOV"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUW_RECOV_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+    <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ha.xml b/xml/p10/node_cfir_pauw_ha.xml
index e9090eb..bd7ac57 100644
--- a/xml/p10/node_cfir_pauw_ha.xml
+++ b/xml/p10/node_cfir_pauw_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUW_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PAUW_HA" reg_type="SCOM">
     <register name="CFIR_PAUW_HOSTATTN">
         <instance addr="0x12040004" reg_inst="0"/>
         <instance addr="0x13040004" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_pauw_spa.xml b/xml/p10/node_cfir_pauw_spa.xml
index 95df6ad..3075b4d 100644
--- a/xml/p10/node_cfir_pauw_spa.xml
+++ b/xml/p10/node_cfir_pauw_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUW_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUW_SPA" reg_type="SCOM">
     <register name="CFIR_PAUW_SPATTN">
         <instance addr="0x12040002" reg_inst="0"/>
         <instance addr="0x13040002" reg_inst="1"/>
@@ -19,6 +19,5 @@
     </rule>
     <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
     <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
 </attn_node>
diff --git a/xml/p10/node_cfir_pauw_spa_p10_10.xml b/xml/p10/node_cfir_pauw_spa_p10_10.xml
new file mode 100644
index 0000000..95df6ad
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_spa_p10_10.xml
@@ -0,0 +1,24 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_SPA" reg_type="SCOM">
+    <register name="CFIR_PAUW_SPATTN">
+        <instance addr="0x12040002" reg_inst="0"/>
+        <instance addr="0x13040002" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUW_SPATTN_MASK">
+        <instance addr="0x12040042" reg_inst="0"/>
+        <instance addr="0x13040042" reg_inst="1"/>
+    </register>
+    <rule attn_type="SPA" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUW_SPATTN"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUW_SPATTN_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_PTL_FIR" node_inst="2,3" pos="16"/>
+</attn_node>
diff --git a/xml/p10/node_cfir_pauw_ucs.xml b/xml/p10/node_cfir_pauw_ucs.xml
index f52277a..87fab96 100644
--- a/xml/p10/node_cfir_pauw_ucs.xml
+++ b/xml/p10/node_cfir_pauw_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PAUW_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="CFIR_PAUW_UCS" reg_type="SCOM">
     <register name="CFIR_PAUW_LOCAL_XSTOP">
         <instance addr="0x12040003" reg_inst="0"/>
         <instance addr="0x13040003" reg_inst="1"/>
@@ -25,5 +25,4 @@
     <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
     <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
     <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
-    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
 </attn_node>
diff --git a/xml/p10/node_cfir_pauw_ucs_p10_10.xml b/xml/p10/node_cfir_pauw_ucs_p10_10.xml
new file mode 100644
index 0000000..f52277a
--- /dev/null
+++ b/xml/p10/node_cfir_pauw_ucs_p10_10.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="CFIR_PAUW_UCS" reg_type="SCOM">
+    <register name="CFIR_PAUW_LOCAL_XSTOP">
+        <instance addr="0x12040003" reg_inst="0"/>
+        <instance addr="0x13040003" reg_inst="1"/>
+    </register>
+    <register name="CFIR_PAUW_LOCAL_XSTOP_MASK">
+        <instance addr="0x12040043" reg_inst="0"/>
+        <instance addr="0x13040043" reg_inst="1"/>
+    </register>
+    <rule attn_type="UCS" node_inst="0:1">
+        <expr type="and">
+            <expr type="reg" value1="CFIR_PAUW_LOCAL_XSTOP"/>
+            <expr type="not">
+                <expr type="reg" value1="CFIR_PAUW_LOCAL_XSTOP_MASK"/>
+            </expr>
+            <expr type="int" value1="0x0FFFFFFFFFFFFFFF"/>
+        </expr>
+    </rule>
+    <bit child_node="PAU_LOCAL_FIR" node_inst="2,3" pos="4">Local FIR</bit>
+    <bit child_node="PAU_FIR_0" node_inst="4,6" pos="5">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="4,6" pos="6">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="4,6" pos="7">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_FIR_0" node_inst="5,7" pos="9">Local FIR register for the PAU (1 of 3)</bit>
+    <bit child_node="PAU_FIR_1" node_inst="5,7" pos="10">Local FIR register for the PAU (2 of 3)</bit>
+    <bit child_node="PAU_FIR_2" node_inst="5,7" pos="11">Local FIR register for the PAU (3 of 3)</bit>
+    <bit child_node="PAU_PHY_FIR" node_inst="2,3" pos="13">Local FIR register for the chip pervasive logic</bit>
+    <bit child_node="PAU_DL_FIR" node_inst="2,3" pos="14">Local FIR register for the chip pervasive logic</bit>
+</attn_node>
diff --git a/xml/p10/node_cfir_pci_cs_re.xml b/xml/p10/node_cfir_pci_cs_re.xml
index f13a754..0c78fd3 100644
--- a/xml/p10/node_cfir_pci_cs_re.xml
+++ b/xml/p10/node_cfir_pci_cs_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PCI_CS_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_CS_RE" reg_type="SCOM">
     <register name="CFIR_PCI_XSTOP">
         <instance addr="0x08040000" reg_inst="0"/>
         <instance addr="0x09040000" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_pci_spa_ha.xml b/xml/p10/node_cfir_pci_spa_ha.xml
index 1487b89..f03156a 100644
--- a/xml/p10/node_cfir_pci_spa_ha.xml
+++ b/xml/p10/node_cfir_pci_spa_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PCI_SPA_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_SPA_HA" reg_type="SCOM">
     <register name="CFIR_PCI_SPATTN">
         <instance addr="0x08040002" reg_inst="0"/>
         <instance addr="0x09040002" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_pci_ucs.xml b/xml/p10/node_cfir_pci_ucs.xml
index fc91dff..c48ac5b 100644
--- a/xml/p10/node_cfir_pci_ucs.xml
+++ b/xml/p10/node_cfir_pci_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_PCI_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_PCI_UCS" reg_type="SCOM">
     <register name="CFIR_PCI_LOCAL_XSTOP">
         <instance addr="0x08040003" reg_inst="0"/>
         <instance addr="0x09040003" reg_inst="1"/>
diff --git a/xml/p10/node_cfir_tp_cs_re.xml b/xml/p10/node_cfir_tp_cs_re.xml
index 2117513..20fd153 100644
--- a/xml/p10/node_cfir_tp_cs_re.xml
+++ b/xml/p10/node_cfir_tp_cs_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_TP_CS_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_CS_RE" reg_type="SCOM">
     <register name="CFIR_TP_XSTOP">
         <instance addr="0x01040000" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_cfir_tp_spa_ucs_ha.xml b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
index fc2dd4e..37313b9 100644
--- a/xml/p10/node_cfir_tp_spa_ucs_ha.xml
+++ b/xml/p10/node_cfir_tp_spa_ucs_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="CFIR_TP_SPA_UCS_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="CFIR_TP_SPA_UCS_HA" reg_type="SCOM">
     <register name="CFIR_TP_SPATTN">
         <instance addr="0x01040002" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_eq_core_fir.xml b/xml/p10/node_eq_core_fir.xml
index 4125951..85e933b 100644
--- a/xml/p10/node_eq_core_fir.xml
+++ b/xml/p10/node_eq_core_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_CORE_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="EQ_CORE_FIR" reg_type="SCOM">
     <register name="EQ_CORE_FIR">
         <instance addr="0x20028440" reg_inst="0"/>
         <instance addr="0x20024440" reg_inst="1"/>
@@ -222,7 +222,7 @@
     <bit pos="10">reserved</bit>
     <bit pos="11">ISU logic recoverable error</bit>
     <bit pos="12">ISU logic core checkstop</bit>
-    <bit pos="13">ISU recoverable if not in MT window</bit>
+    <bit pos="13">reserved</bit>
     <bit pos="14">MCHK received while ME=0 - non recoverable</bit>
     <bit pos="15">UE from L2</bit>
     <bit pos="16">Number of UEs from L2 above threshold</bit>
diff --git a/xml/p10/node_eq_core_fir_p10_10.xml b/xml/p10/node_eq_core_fir_p10_10.xml
new file mode 100644
index 0000000..4125951
--- /dev/null
+++ b/xml/p10/node_eq_core_fir_p10_10.xml
@@ -0,0 +1,276 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_CORE_FIR" reg_type="SCOM">
+    <register name="EQ_CORE_FIR">
+        <instance addr="0x20028440" reg_inst="0"/>
+        <instance addr="0x20024440" reg_inst="1"/>
+        <instance addr="0x20022440" reg_inst="2"/>
+        <instance addr="0x20021440" reg_inst="3"/>
+        <instance addr="0x21028440" reg_inst="4"/>
+        <instance addr="0x21024440" reg_inst="5"/>
+        <instance addr="0x21022440" reg_inst="6"/>
+        <instance addr="0x21021440" reg_inst="7"/>
+        <instance addr="0x22028440" reg_inst="8"/>
+        <instance addr="0x22024440" reg_inst="9"/>
+        <instance addr="0x22022440" reg_inst="10"/>
+        <instance addr="0x22021440" reg_inst="11"/>
+        <instance addr="0x23028440" reg_inst="12"/>
+        <instance addr="0x23024440" reg_inst="13"/>
+        <instance addr="0x23022440" reg_inst="14"/>
+        <instance addr="0x23021440" reg_inst="15"/>
+        <instance addr="0x24028440" reg_inst="16"/>
+        <instance addr="0x24024440" reg_inst="17"/>
+        <instance addr="0x24022440" reg_inst="18"/>
+        <instance addr="0x24021440" reg_inst="19"/>
+        <instance addr="0x25028440" reg_inst="20"/>
+        <instance addr="0x25024440" reg_inst="21"/>
+        <instance addr="0x25022440" reg_inst="22"/>
+        <instance addr="0x25021440" reg_inst="23"/>
+        <instance addr="0x26028440" reg_inst="24"/>
+        <instance addr="0x26024440" reg_inst="25"/>
+        <instance addr="0x26022440" reg_inst="26"/>
+        <instance addr="0x26021440" reg_inst="27"/>
+        <instance addr="0x27028440" reg_inst="28"/>
+        <instance addr="0x27024440" reg_inst="29"/>
+        <instance addr="0x27022440" reg_inst="30"/>
+        <instance addr="0x27021440" reg_inst="31"/>
+    </register>
+    <register name="EQ_CORE_FIR_MASK">
+        <instance addr="0x20028443" reg_inst="0"/>
+        <instance addr="0x20024443" reg_inst="1"/>
+        <instance addr="0x20022443" reg_inst="2"/>
+        <instance addr="0x20021443" reg_inst="3"/>
+        <instance addr="0x21028443" reg_inst="4"/>
+        <instance addr="0x21024443" reg_inst="5"/>
+        <instance addr="0x21022443" reg_inst="6"/>
+        <instance addr="0x21021443" reg_inst="7"/>
+        <instance addr="0x22028443" reg_inst="8"/>
+        <instance addr="0x22024443" reg_inst="9"/>
+        <instance addr="0x22022443" reg_inst="10"/>
+        <instance addr="0x22021443" reg_inst="11"/>
+        <instance addr="0x23028443" reg_inst="12"/>
+        <instance addr="0x23024443" reg_inst="13"/>
+        <instance addr="0x23022443" reg_inst="14"/>
+        <instance addr="0x23021443" reg_inst="15"/>
+        <instance addr="0x24028443" reg_inst="16"/>
+        <instance addr="0x24024443" reg_inst="17"/>
+        <instance addr="0x24022443" reg_inst="18"/>
+        <instance addr="0x24021443" reg_inst="19"/>
+        <instance addr="0x25028443" reg_inst="20"/>
+        <instance addr="0x25024443" reg_inst="21"/>
+        <instance addr="0x25022443" reg_inst="22"/>
+        <instance addr="0x25021443" reg_inst="23"/>
+        <instance addr="0x26028443" reg_inst="24"/>
+        <instance addr="0x26024443" reg_inst="25"/>
+        <instance addr="0x26022443" reg_inst="26"/>
+        <instance addr="0x26021443" reg_inst="27"/>
+        <instance addr="0x27028443" reg_inst="28"/>
+        <instance addr="0x27024443" reg_inst="29"/>
+        <instance addr="0x27022443" reg_inst="30"/>
+        <instance addr="0x27021443" reg_inst="31"/>
+    </register>
+    <register name="EQ_CORE_FIR_ACT0">
+        <instance addr="0x20028446" reg_inst="0"/>
+        <instance addr="0x20024446" reg_inst="1"/>
+        <instance addr="0x20022446" reg_inst="2"/>
+        <instance addr="0x20021446" reg_inst="3"/>
+        <instance addr="0x21028446" reg_inst="4"/>
+        <instance addr="0x21024446" reg_inst="5"/>
+        <instance addr="0x21022446" reg_inst="6"/>
+        <instance addr="0x21021446" reg_inst="7"/>
+        <instance addr="0x22028446" reg_inst="8"/>
+        <instance addr="0x22024446" reg_inst="9"/>
+        <instance addr="0x22022446" reg_inst="10"/>
+        <instance addr="0x22021446" reg_inst="11"/>
+        <instance addr="0x23028446" reg_inst="12"/>
+        <instance addr="0x23024446" reg_inst="13"/>
+        <instance addr="0x23022446" reg_inst="14"/>
+        <instance addr="0x23021446" reg_inst="15"/>
+        <instance addr="0x24028446" reg_inst="16"/>
+        <instance addr="0x24024446" reg_inst="17"/>
+        <instance addr="0x24022446" reg_inst="18"/>
+        <instance addr="0x24021446" reg_inst="19"/>
+        <instance addr="0x25028446" reg_inst="20"/>
+        <instance addr="0x25024446" reg_inst="21"/>
+        <instance addr="0x25022446" reg_inst="22"/>
+        <instance addr="0x25021446" reg_inst="23"/>
+        <instance addr="0x26028446" reg_inst="24"/>
+        <instance addr="0x26024446" reg_inst="25"/>
+        <instance addr="0x26022446" reg_inst="26"/>
+        <instance addr="0x26021446" reg_inst="27"/>
+        <instance addr="0x27028446" reg_inst="28"/>
+        <instance addr="0x27024446" reg_inst="29"/>
+        <instance addr="0x27022446" reg_inst="30"/>
+        <instance addr="0x27021446" reg_inst="31"/>
+    </register>
+    <register name="EQ_CORE_FIR_ACT1">
+        <instance addr="0x20028447" reg_inst="0"/>
+        <instance addr="0x20024447" reg_inst="1"/>
+        <instance addr="0x20022447" reg_inst="2"/>
+        <instance addr="0x20021447" reg_inst="3"/>
+        <instance addr="0x21028447" reg_inst="4"/>
+        <instance addr="0x21024447" reg_inst="5"/>
+        <instance addr="0x21022447" reg_inst="6"/>
+        <instance addr="0x21021447" reg_inst="7"/>
+        <instance addr="0x22028447" reg_inst="8"/>
+        <instance addr="0x22024447" reg_inst="9"/>
+        <instance addr="0x22022447" reg_inst="10"/>
+        <instance addr="0x22021447" reg_inst="11"/>
+        <instance addr="0x23028447" reg_inst="12"/>
+        <instance addr="0x23024447" reg_inst="13"/>
+        <instance addr="0x23022447" reg_inst="14"/>
+        <instance addr="0x23021447" reg_inst="15"/>
+        <instance addr="0x24028447" reg_inst="16"/>
+        <instance addr="0x24024447" reg_inst="17"/>
+        <instance addr="0x24022447" reg_inst="18"/>
+        <instance addr="0x24021447" reg_inst="19"/>
+        <instance addr="0x25028447" reg_inst="20"/>
+        <instance addr="0x25024447" reg_inst="21"/>
+        <instance addr="0x25022447" reg_inst="22"/>
+        <instance addr="0x25021447" reg_inst="23"/>
+        <instance addr="0x26028447" reg_inst="24"/>
+        <instance addr="0x26024447" reg_inst="25"/>
+        <instance addr="0x26022447" reg_inst="26"/>
+        <instance addr="0x26021447" reg_inst="27"/>
+        <instance addr="0x27028447" reg_inst="28"/>
+        <instance addr="0x27024447" reg_inst="29"/>
+        <instance addr="0x27022447" reg_inst="30"/>
+        <instance addr="0x27021447" reg_inst="31"/>
+    </register>
+    <register name="EQ_CORE_FIR_WOF">
+        <instance addr="0x20028448" reg_inst="0"/>
+        <instance addr="0x20024448" reg_inst="1"/>
+        <instance addr="0x20022448" reg_inst="2"/>
+        <instance addr="0x20021448" reg_inst="3"/>
+        <instance addr="0x21028448" reg_inst="4"/>
+        <instance addr="0x21024448" reg_inst="5"/>
+        <instance addr="0x21022448" reg_inst="6"/>
+        <instance addr="0x21021448" reg_inst="7"/>
+        <instance addr="0x22028448" reg_inst="8"/>
+        <instance addr="0x22024448" reg_inst="9"/>
+        <instance addr="0x22022448" reg_inst="10"/>
+        <instance addr="0x22021448" reg_inst="11"/>
+        <instance addr="0x23028448" reg_inst="12"/>
+        <instance addr="0x23024448" reg_inst="13"/>
+        <instance addr="0x23022448" reg_inst="14"/>
+        <instance addr="0x23021448" reg_inst="15"/>
+        <instance addr="0x24028448" reg_inst="16"/>
+        <instance addr="0x24024448" reg_inst="17"/>
+        <instance addr="0x24022448" reg_inst="18"/>
+        <instance addr="0x24021448" reg_inst="19"/>
+        <instance addr="0x25028448" reg_inst="20"/>
+        <instance addr="0x25024448" reg_inst="21"/>
+        <instance addr="0x25022448" reg_inst="22"/>
+        <instance addr="0x25021448" reg_inst="23"/>
+        <instance addr="0x26028448" reg_inst="24"/>
+        <instance addr="0x26024448" reg_inst="25"/>
+        <instance addr="0x26022448" reg_inst="26"/>
+        <instance addr="0x26021448" reg_inst="27"/>
+        <instance addr="0x27028448" reg_inst="28"/>
+        <instance addr="0x27024448" reg_inst="29"/>
+        <instance addr="0x27022448" reg_inst="30"/>
+        <instance addr="0x27021448" reg_inst="31"/>
+    </register>
+    <rule attn_type="CS" node_inst="0:31">
+        <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
+        <expr type="and">
+            <expr type="reg" value1="EQ_CORE_FIR"/>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+            </expr>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0:31">
+        <!-- WOF & ~MASK & ~ACT0 & ACT1 -->
+        <expr type="and">
+            <expr type="reg" value1="EQ_CORE_FIR_WOF"/>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+            </expr>
+            <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+        </expr>
+    </rule>
+    <rule attn_type="UCS" node_inst="0:31">
+        <!-- FIR & ~MASK & ACT0 & ACT1 -->
+        <expr type="and">
+            <expr type="reg" value1="EQ_CORE_FIR"/>
+            <expr type="not">
+                <expr type="reg" value1="EQ_CORE_FIR_MASK"/>
+            </expr>
+            <expr type="reg" value1="EQ_CORE_FIR_ACT0"/>
+            <expr type="reg" value1="EQ_CORE_FIR_ACT1"/>
+        </expr>
+    </rule>
+    <bit pos="0">IFU SRAM recoverable error (ICACHE parity error, etc)</bit>
+    <bit pos="1">TC checkstop</bit>
+    <bit pos="2">IFU RegFile recoverable error</bit>
+    <bit pos="3">IFU RegFile core checkstop</bit>
+    <bit pos="4">IFU logic recoverable error</bit>
+    <bit pos="5">IFU logic core checkstop</bit>
+    <bit pos="6">reserved</bit>
+    <bit pos="7">VSU Inference Accumulator recoverable error</bit>
+    <bit pos="8">Recovery core checkstop</bit>
+    <bit pos="9">VSU Slice Targeted File (STF) recoverable error</bit>
+    <bit pos="10">reserved</bit>
+    <bit pos="11">ISU logic recoverable error</bit>
+    <bit pos="12">ISU logic core checkstop</bit>
+    <bit pos="13">ISU recoverable if not in MT window</bit>
+    <bit pos="14">MCHK received while ME=0 - non recoverable</bit>
+    <bit pos="15">UE from L2</bit>
+    <bit pos="16">Number of UEs from L2 above threshold</bit>
+    <bit pos="17">UE on CI load</bit>
+    <bit pos="18">MMU TLB parity recoverable error</bit>
+    <bit pos="19">MMU SLB parity recoverable error</bit>
+    <bit pos="20">reserved</bit>
+    <bit pos="21">MMU CXT recoverable error</bit>
+    <bit pos="22">MMU logic core checkstop</bit>
+    <bit pos="23">MMU system checkstop</bit>
+    <bit pos="24">VSU logic recoverable error</bit>
+    <bit pos="25">VSU logic core checkstop</bit>
+    <bit pos="26">Thread in maintenance mode and receives recovery request</bit>
+    <bit pos="27">reserved</bit>
+    <bit pos="28">PC system checkstop - Recoverable error received when recovery disabled</bit>
+    <bit pos="29">LSU SRAM recoverable error (DCACHE parity error, ERAT parity error, etc)</bit>
+    <bit pos="30">LSU set deleted</bit>
+    <bit pos="31">LSU RegFile recoverable error</bit>
+    <bit pos="32">LSU RegFile core checkstop</bit>
+    <bit pos="33">MMU TLB multi hit error occurred</bit>
+    <bit pos="34">MMU SLB multi hit error occurred</bit>
+    <bit pos="35">LSU ERAT multi hit error occurred</bit>
+    <bit pos="36">PC forward progress error</bit>
+    <bit pos="37">LSU logic recoverable error</bit>
+    <bit pos="38">LSU logic core checkstop</bit>
+    <bit pos="39">reserved</bit>
+    <bit pos="40">reserved</bit>
+    <bit pos="41">LSU system checkstop</bit>
+    <bit pos="42">reserved</bit>
+    <bit pos="43">PC thread hang recoverable error</bit>
+    <bit pos="44">reserved</bit>
+    <bit pos="45">PC logic checkstop</bit>
+    <bit pos="46">PC TimeBase Facility checkstop</bit>
+    <bit pos="47">PC TimeBase Facility checkstop</bit>
+    <bit pos="48">reserved</bit>
+    <bit pos="49">reserved</bit>
+    <bit pos="50">reserved</bit>
+    <bit pos="51">reserved</bit>
+    <bit pos="52">Hang Recovery Failed</bit>
+    <bit pos="53">Core Hang detected</bit>
+    <bit pos="54">reserved</bit>
+    <bit pos="55">Nest Hang detected</bit>
+    <bit pos="56">Other Core Chiplet recoverable error</bit>
+    <bit pos="57">Other Core Chiplet core checkstop</bit>
+    <bit pos="58">Other Core Chiplet system checkstop</bit>
+    <bit pos="59">SCOM satellite error detected</bit>
+    <bit pos="60">Debug Trigger error inject</bit>
+    <bit pos="61">SCOM or Firmware recoverable error inject</bit>
+    <bit pos="62">Firmware checkstop error inject</bit>
+    <bit pos="63">PHYP checkstop via SPRC/SPRD</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_core_thread_state.xml b/xml/p10/node_eq_core_thread_state.xml
index 49a68d5..d95ac0c 100644
--- a/xml/p10/node_eq_core_thread_state.xml
+++ b/xml/p10/node_eq_core_thread_state.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_CORE_THREAD_STATE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_CORE_THREAD_STATE" reg_type="SCOM">
     <register name="CORE_THREAD_STATE">
         <instance addr="0x20028412" reg_inst="0"/>
         <instance addr="0x20024412" reg_inst="1"/>
diff --git a/xml/p10/node_eq_l2_fir.xml b/xml/p10/node_eq_l2_fir.xml
index 4256626..d0d20ea 100644
--- a/xml/p10/node_eq_l2_fir.xml
+++ b/xml/p10/node_eq_l2_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_L2_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_L2_FIR" reg_type="SCOM">
     <local_fir config="" name="EQ_L2_FIR">
         <instance addr="0x20028000" reg_inst="0"/>
         <instance addr="0x20024000" reg_inst="1"/>
diff --git a/xml/p10/node_eq_l3_fir.xml b/xml/p10/node_eq_l3_fir.xml
index 69e61b1..42dd33b 100644
--- a/xml/p10/node_eq_l3_fir.xml
+++ b/xml/p10/node_eq_l3_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_L3_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_L3_FIR" reg_type="SCOM">
     <local_fir config="" name="EQ_L3_FIR">
         <instance addr="0x20018600" reg_inst="0"/>
         <instance addr="0x20014600" reg_inst="1"/>
@@ -55,7 +55,7 @@
     <bit pos="16">Received addr_error cresp on Snoop Machine or Castout Operation</bit>
     <bit pos="17">Received addr_error cresp for Prefetch Operation</bit>
     <bit pos="18">Asserts when the L3 returns presp_rty_other to a PowerBus hang.poll or hang.check RCMD. This is typically masked, but provides an indication that an operation hang has been detected and signalled.</bit>
-    <bit pos="19">lru invalid count error. Violation of requirement that, when not in dmap or fixed-member mode, each group must have a member with lru_cnt=0 for 1st class and a member with lru_cnt=0 for 2nd class if there is a 2nd class member. Will not assert when an lru_cnt=0 is found for a member that is disabled. This error (missing lru_cnt=0) is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds. On an L2-read or snoop, an LRU array is read, but errors aren't corrected because no LRU array write occurs. Thus, repeated reads to the location with the error may cause this bit to repeated assert. This bit may assert despite no error if the group and config have changed since the last time the CGC was accessed.</bit>
+    <bit pos="19">lru invalid count error. Violation of requirement that, when not in dmap or fixed-member mode, each group must have a member with lru_cnt=0 for 1st class and a member with lru_cnt=0 for 2nd class if there is a 2nd class member. Will not assert when an lru_cnt=0 is found for a member that is disabled. This error is typically masked because l3_lru_vic_sel_error is the true check for LRU errors. This is only a partial check (it doesn't check for multiple lru_cnt=0) and it can assert even when the LRU array contents are not used (error is in a class that isn't used) This error (missing lru_cnt=0) is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds. This bit may assert despite no error if the group and config have changed since the last time the CGC was accessed.</bit>
     <bit pos="20">spare20</bit>
     <bit pos="21">spare21</bit>
     <bit pos="22">spare22</bit>
@@ -64,7 +64,7 @@
     <bit pos="25">Cache Inhibited operation was hit in the L3 directory. This is usually a software bug.</bit>
     <bit pos="26">Snoop Machine or Read machine has performed a line delete from a cache read</bit>
     <bit pos="27">Indicates that this l3 has snooped an incoming lco and in which the source (rcmdx_source) is not proxime. This is likely due to a programming error and could result in multiple owners of a line</bit>
-    <bit pos="28">Indicates the LRU intended to victimize a line, but failed to select exactly one member for victimization. This asserts due to a LRU array bit error (lru_inval_cnt_err also asserts) or an algorithm or implementation error in the logic that generates the selection. The lru_inval_cnt_err, and thus this bit, may assert despite no error if the group and config have changed since the last time the CGC was accessed. This error is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds. On an l2-read or snoop, an LRU array is read, but errors aren't corrected because there is no LRU array write. Thus, repeated reads to the location with the error may cause this bit to repeated assert.</bit>
+    <bit pos="28">Indicates the L3 is inserting a line and thus a victimization might be needed (if there are no invalid line in the CGC), but the L3 failed to select exactly one member for (possible) victimization. This asserts due to a LRU array bit error (lru_inval_cnt_err may also asserts). This may assert despite no error if the group and config have changed since the last time the CGC was accessed. This error is recoverable - the L3 fails dispatch and then goes into random-victim- selection mode until it succeeds, at which time (sometimes prior to this) the error is overwritten. On an L2-read or snoop, an LRU array is read, but errors aren't checked or corrected because there is no LRU array write.</bit>
     <bit pos="29">All members are either column or line deleted in some CGC class</bit>
     <bit pos="30">Indicates that this l3 has snooped an incoming lco and we are the target however, our lco target id (set via SCOM in mode_reg1) does not match the chiplet id set by pb through input pins pb_ex_chiplet_id_dc Note that in chip-contained mode, the LCOs ID are often set to values that dont match the pb_ex_chiplet_id, thus this error is masked in that mode.</bit>
     <bit pos="31">Received ack_dead or ed_ack_dead cresp on CO, SN operation (pb write)</bit>
diff --git a/xml/p10/node_eq_local_fir.xml b/xml/p10/node_eq_local_fir.xml
index 7895c79..2f92278 100644
--- a/xml/p10/node_eq_local_fir.xml
+++ b/xml/p10/node_eq_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="EQ_LOCAL_FIR">
         <instance addr="0x20040100" reg_inst="0"/>
         <instance addr="0x21040100" reg_inst="1"/>
@@ -17,16 +17,16 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM1 - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM1 - pcb error</bit>
     <bit pos="8">THERMTRIP1 - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP1 - Fatal temperature indicator</bit>
     <bit pos="10">VOLTTRIP1 - Voltage sense error</bit>
-    <bit pos="11">THERM2 - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050033</bit>
+    <bit pos="11">THERM2 - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="12">THERM2 - pcb error</bit>
     <bit pos="13">THERMTRIP2 - Critical temperature indicator</bit>
     <bit pos="14">THERMTRIP2 - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_eq_ncu_fir.xml b/xml/p10/node_eq_ncu_fir.xml
index 1d40018..98756b3 100644
--- a/xml/p10/node_eq_ncu_fir.xml
+++ b/xml/p10/node_eq_ncu_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_NCU_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="EQ_NCU_FIR" reg_type="SCOM">
     <local_fir config="" name="EQ_NCU_FIR">
         <instance addr="0x20018640" reg_inst="0"/>
         <instance addr="0x20014640" reg_inst="1"/>
diff --git a/xml/p10/node_eq_ncu_fir_p10_10.xml b/xml/p10/node_eq_ncu_fir_p10_10.xml
new file mode 100644
index 0000000..93336fd
--- /dev/null
+++ b/xml/p10/node_eq_ncu_fir_p10_10.xml
@@ -0,0 +1,68 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_NCU_FIR" reg_type="SCOM">
+    <local_fir config="" name="EQ_NCU_FIR">
+        <instance addr="0x20018640" reg_inst="0"/>
+        <instance addr="0x20014640" reg_inst="1"/>
+        <instance addr="0x20012640" reg_inst="2"/>
+        <instance addr="0x20011640" reg_inst="3"/>
+        <instance addr="0x21018640" reg_inst="4"/>
+        <instance addr="0x21014640" reg_inst="5"/>
+        <instance addr="0x21012640" reg_inst="6"/>
+        <instance addr="0x21011640" reg_inst="7"/>
+        <instance addr="0x22018640" reg_inst="8"/>
+        <instance addr="0x22014640" reg_inst="9"/>
+        <instance addr="0x22012640" reg_inst="10"/>
+        <instance addr="0x22011640" reg_inst="11"/>
+        <instance addr="0x23018640" reg_inst="12"/>
+        <instance addr="0x23014640" reg_inst="13"/>
+        <instance addr="0x23012640" reg_inst="14"/>
+        <instance addr="0x23011640" reg_inst="15"/>
+        <instance addr="0x24018640" reg_inst="16"/>
+        <instance addr="0x24014640" reg_inst="17"/>
+        <instance addr="0x24012640" reg_inst="18"/>
+        <instance addr="0x24011640" reg_inst="19"/>
+        <instance addr="0x25018640" reg_inst="20"/>
+        <instance addr="0x25014640" reg_inst="21"/>
+        <instance addr="0x25012640" reg_inst="22"/>
+        <instance addr="0x25011640" reg_inst="23"/>
+        <instance addr="0x26018640" reg_inst="24"/>
+        <instance addr="0x26014640" reg_inst="25"/>
+        <instance addr="0x26012640" reg_inst="26"/>
+        <instance addr="0x26011640" reg_inst="27"/>
+        <instance addr="0x27018640" reg_inst="28"/>
+        <instance addr="0x27014640" reg_inst="29"/>
+        <instance addr="0x27012640" reg_inst="30"/>
+        <instance addr="0x27011640" reg_inst="31"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+    </local_fir>
+    <bit pos="0">H/W control error.</bit>
+    <bit pos="1">TLBIE control error.</bit>
+    <bit pos="2">TLBIE or SLBIEG received illegal fields from core.</bit>
+    <bit pos="3">Store address machine received addr_err cresp.</bit>
+    <bit pos="4">Load address machine received addr_err cresp.</bit>
+    <bit pos="5">Topology table error - tried accessing invalid entry</bit>
+    <bit pos="6">One the NCU machines triggerd PB into early hang recovery</bit>
+    <bit pos="7">MSGSND received addr_err</bit>
+    <bit pos="8">Store data parity error from regfile detected.</bit>
+    <bit pos="9">Store timed out on PB.</bit>
+    <bit pos="10">TLBIE master timed out on PB.</bit>
+    <bit pos="11">TLBIE snooper timed out waiting for core.</bit>
+    <bit pos="12">IMA received addr_err cresp.</bit>
+    <bit pos="13">TLBIE/sync machine received addr_err cresp.</bit>
+    <bit pos="14">PMISC received address error cresp.</bit>
+    <bit pos="15">Spare fir bits.</bit>
+    <bit pos="16">Spare fir bits.</bit>
+    <bit pos="17">Spare fir bits.</bit>
+    <bit pos="18">Spare fir bits.</bit>
+    <bit pos="19">PPE write received ack_dead</bit>
+    <bit pos="20">Darn ttype while darn not enabled.</bit>
+    <bit pos="21">Darn Address Error cresp.</bit>
+    <bit pos="22">Spare fir bits.</bit>
+    <bit pos="23">Spare fir bits.</bit>
+    <bit pos="24">Spare fir bits.</bit>
+    <bit pos="25">Spare fir bits.</bit>
+    <bit pos="26">Spare fir bits.</bit>
+    <bit pos="27">Spare fir bits.</bit>
+    <bit pos="28">Spare fir bits.</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_qme_fir.xml b/xml/p10/node_eq_qme_fir.xml
index aaaa854..0f0a3e1 100644
--- a/xml/p10/node_eq_qme_fir.xml
+++ b/xml/p10/node_eq_qme_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_QME_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="EQ_QME_FIR" reg_type="SCOM">
     <register name="EQ_QME_FIR">
         <instance addr="0x200E0000" reg_inst="0"/>
         <instance addr="0x210E0000" reg_inst="1"/>
@@ -84,12 +84,12 @@
     <bit pos="13">PGPE Heartbeat Lost indication from a hardware deadman timer controlled by QHB.  Intended to be reported as an interrupt to QME via action 10.</bit>
     <bit pos="14">Notification that BCE has not made forward progress in the time period corresponding to two scrub timer pulses (regardless of scrub enable).  The BCE</bit>
     <bit pos="15">Resclk TARGET_PSTATE Change Protocol Error. PGPE code bug.</bit>
-    <bit pos="16">PCB Network or Endpoint Reset occurred when QME was not halted. This should never occur during runtime (for lab debug use only) and MAY result in loss</bit>
+    <bit pos="16">Unexpected PCB Network or Endpoint Reset occurred when QME was not halted, had an active request to the PCB Slave, or the QME saw a reset without a</bit>
     <bit pos="17">Firmware cleared their Special Wakeup request in SPWU_{OTR|FSP|OCC|HYP}[ SPECIAL_WKUP_REQ] before the SPECIAL_WKUP_DONE was set.</bit>
     <bit pos="18">Indicates a window condition occurred where one firmware component set a new special wakeup right after a different firmware component cleared the</bit>
     <bit pos="19">Any of the Core External Interrupt wakeup sources (os, hyp, msgsnd, msgsndu) are present but disabled by the threads PECE (or UDEE) when it is in Stop</bit>
     <bit pos="20">Any of the Core External Interrupts (os, hyp, msgsnd, msgsndu) are present but the chiplet is deconfigured (based on the partial good region enable</bit>
-    <bit pos="21">Notification that RS4 engine has not made forward progress in the time period corresponding to two watchdog timer pulses (regardless of PPE watchdog</bit>
+    <bit pos="21">Reserved</bit>
     <bit pos="22">Data hang was detected in the powerbus logic, caused by a powerbus read command waiting for data that is lost.</bit>
     <bit pos="23">The PPE tried to write a protected address as defined by the SWPR[n] register</bit>
     <bit pos="24">DTC Sequencer read a UE from SRAM, causing it to abort its current sequence and disable itself in QMCR.</bit>
@@ -102,6 +102,6 @@
     <bit pos="31">Set based on the OR of three ERR[LOCAL_ACCESS_*_ERR] bits.</bit>
     <bit pos="32">CE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
     <bit pos="33">UE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
-    <bit pos="34">Implemented but not used. Input tied to 0.</bit>
+    <bit pos="34">A parity error was detected in one of the CCFG latches present in the Resonant Clock stepper logic in the QME.</bit>
     <bit pos="35">Implemented but not used. Input tied to 0.</bit>
 </attn_node>
diff --git a/xml/p10/node_eq_qme_fir_p10_10.xml b/xml/p10/node_eq_qme_fir_p10_10.xml
new file mode 100644
index 0000000..aaaa854
--- /dev/null
+++ b/xml/p10/node_eq_qme_fir_p10_10.xml
@@ -0,0 +1,107 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="EQ_QME_FIR" reg_type="SCOM">
+    <register name="EQ_QME_FIR">
+        <instance addr="0x200E0000" reg_inst="0"/>
+        <instance addr="0x210E0000" reg_inst="1"/>
+        <instance addr="0x220E0000" reg_inst="2"/>
+        <instance addr="0x230E0000" reg_inst="3"/>
+        <instance addr="0x240E0000" reg_inst="4"/>
+        <instance addr="0x250E0000" reg_inst="5"/>
+        <instance addr="0x260E0000" reg_inst="6"/>
+        <instance addr="0x270E0000" reg_inst="7"/>
+    </register>
+    <register name="EQ_QME_FIR_MASK">
+        <instance addr="0x200E0004" reg_inst="0"/>
+        <instance addr="0x210E0004" reg_inst="1"/>
+        <instance addr="0x220E0004" reg_inst="2"/>
+        <instance addr="0x230E0004" reg_inst="3"/>
+        <instance addr="0x240E0004" reg_inst="4"/>
+        <instance addr="0x250E0004" reg_inst="5"/>
+        <instance addr="0x260E0004" reg_inst="6"/>
+        <instance addr="0x270E0004" reg_inst="7"/>
+    </register>
+    <register name="EQ_QME_FIR_ACT0">
+        <instance addr="0x200E0008" reg_inst="0"/>
+        <instance addr="0x210E0008" reg_inst="1"/>
+        <instance addr="0x220E0008" reg_inst="2"/>
+        <instance addr="0x230E0008" reg_inst="3"/>
+        <instance addr="0x240E0008" reg_inst="4"/>
+        <instance addr="0x250E0008" reg_inst="5"/>
+        <instance addr="0x260E0008" reg_inst="6"/>
+        <instance addr="0x270E0008" reg_inst="7"/>
+    </register>
+    <register name="EQ_QME_FIR_ACT1">
+        <instance addr="0x200E000c" reg_inst="0"/>
+        <instance addr="0x210E000c" reg_inst="1"/>
+        <instance addr="0x220E000c" reg_inst="2"/>
+        <instance addr="0x230E000c" reg_inst="3"/>
+        <instance addr="0x240E000c" reg_inst="4"/>
+        <instance addr="0x250E000c" reg_inst="5"/>
+        <instance addr="0x260E000c" reg_inst="6"/>
+        <instance addr="0x270E000c" reg_inst="7"/>
+    </register>
+    <rule attn_type="CS" node_inst="0:7">
+        <!-- FIR & ~MASK & ~ACT0 & ~ACT1 -->
+        <expr type="and">
+            <expr type="reg" value1="EQ_QME_FIR"/>
+            <expr type="not">
+                <expr type="reg" value1="EQ_QME_FIR_MASK"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
+            </expr>
+        </expr>
+    </rule>
+    <rule attn_type="RE" node_inst="0:7">
+        <!-- FIR & ~MASK & ~ACT0 & ACT1 -->
+        <expr type="and">
+            <expr type="reg" value1="EQ_QME_FIR"/>
+            <expr type="not">
+                <expr type="reg" value1="EQ_QME_FIR_MASK"/>
+            </expr>
+            <expr type="not">
+                <expr type="reg" value1="EQ_QME_FIR_ACT0"/>
+            </expr>
+            <expr type="reg" value1="EQ_QME_FIR_ACT1"/>
+        </expr>
+    </rule>
+    <bit pos="0">PPE halted due to an error, which is an OR the 4 signals captured in ERR(0:3). This indication is intended to be reported to the OCC complex as an</bit>
+    <bit pos="1">PPE asserted debug trigger. Connected to PPEDBG[FIR_TRIGGER].  May be used by QME hcode to indicate an error to PRD or to induce a checkstop for</bit>
+    <bit pos="2">Used for TBD testing or workarounds</bit>
+    <bit pos="3">PPE asserted a watchdog timeout condition.</bit>
+    <bit pos="4">QME hardware detected its own timeout on the PCB Slave interface and forced a return code of 0x7.  Note: uses the Watchdog TSEL minus 2 bits (watchdog</bit>
+    <bit pos="5">Either the Block Copy Engine or QME PPE direct access received an error from  the Fabric.  A BCE error also causes an interrupt to the QME PPE, if it</bit>
+    <bit pos="6">SRAM Uncorrectable Error.</bit>
+    <bit pos="7">SRAM Correctable Error.  QME received corrected data, but SRAM content is bad until next scrub to that line. (Should be masked in the product;</bit>
+    <bit pos="8">Resonant Clock Table array Parity Error.</bit>
+    <bit pos="9">Hcode wrote the PIG to request a PCB interrupt before its previously requested interrupt had been completed (meaning PIG[PENDING_SOURCE(0)] = 1 OR</bit>
+    <bit pos="10">Scrub timer tick occurred when scrub is still pending (hardware defect or severe configuration error).  Unless the FIT timer is set to smaller than 16</bit>
+    <bit pos="11">Refer to ERR bits of the same name to see which Core instance.</bit>
+    <bit pos="12">Refer to ERR bits of the same name to see which Core instance.</bit>
+    <bit pos="13">PGPE Heartbeat Lost indication from a hardware deadman timer controlled by QHB.  Intended to be reported as an interrupt to QME via action 10.</bit>
+    <bit pos="14">Notification that BCE has not made forward progress in the time period corresponding to two scrub timer pulses (regardless of scrub enable).  The BCE</bit>
+    <bit pos="15">Resclk TARGET_PSTATE Change Protocol Error. PGPE code bug.</bit>
+    <bit pos="16">PCB Network or Endpoint Reset occurred when QME was not halted. This should never occur during runtime (for lab debug use only) and MAY result in loss</bit>
+    <bit pos="17">Firmware cleared their Special Wakeup request in SPWU_{OTR|FSP|OCC|HYP}[ SPECIAL_WKUP_REQ] before the SPECIAL_WKUP_DONE was set.</bit>
+    <bit pos="18">Indicates a window condition occurred where one firmware component set a new special wakeup right after a different firmware component cleared the</bit>
+    <bit pos="19">Any of the Core External Interrupt wakeup sources (os, hyp, msgsnd, msgsndu) are present but disabled by the threads PECE (or UDEE) when it is in Stop</bit>
+    <bit pos="20">Any of the Core External Interrupts (os, hyp, msgsnd, msgsndu) are present but the chiplet is deconfigured (based on the partial good region enable</bit>
+    <bit pos="21">Notification that RS4 engine has not made forward progress in the time period corresponding to two watchdog timer pulses (regardless of PPE watchdog</bit>
+    <bit pos="22">Data hang was detected in the powerbus logic, caused by a powerbus read command waiting for data that is lost.</bit>
+    <bit pos="23">The PPE tried to write a protected address as defined by the SWPR[n] register</bit>
+    <bit pos="24">DTC Sequencer read a UE from SRAM, causing it to abort its current sequence and disable itself in QMCR.</bit>
+    <bit pos="25">Correctable error detected on incoming data for a PowerBus read.</bit>
+    <bit pos="26">UE Detected on incoming data for a PowerBus read.</bit>
+    <bit pos="27">SUE Detected on incoming data for a PowerBus read.</bit>
+    <bit pos="28">A Powerbus Request address has hit an invalid entry in the TOPOLOGY XLATE TABLE [PBTXTR] REGISTER.  This is an unrecoverable error indicating the</bit>
+    <bit pos="29">Parity error detected on a powerbus tag.  Includes combined response ATAG/TTAG parity error as well as a data transaction RTAG parity error.</bit>
+    <bit pos="30">Code attempted to write the PIG register when the previous request was still pending i.e. PIG.PENDING_SOURCE(0)=1.</bit>
+    <bit pos="31">Set based on the OR of three ERR[LOCAL_ACCESS_*_ERR] bits.</bit>
+    <bit pos="32">CE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
+    <bit pos="33">UE detected on a read to the SSA located in the QME powerbus routing logic.</bit>
+    <bit pos="34">Implemented but not used. Input tied to 0.</bit>
+    <bit pos="35">Implemented but not used. Input tied to 0.</bit>
+</attn_node>
diff --git a/xml/p10/node_eq_spattn_fused.xml b/xml/p10/node_eq_spattn_fused.xml
index 400090b..b85b4d5 100644
--- a/xml/p10/node_eq_spattn_fused.xml
+++ b/xml/p10/node_eq_spattn_fused.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_SPATTN_FUSED" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_SPATTN_FUSED" reg_type="SCOM">
     <register name="EQ_SPATTN">
         <instance addr="0x20028499" reg_inst="0"/>
         <instance addr="0x20024499" reg_inst="1"/>
diff --git a/xml/p10/node_eq_spattn_normal.xml b/xml/p10/node_eq_spattn_normal.xml
index fa83655..c825380 100644
--- a/xml/p10/node_eq_spattn_normal.xml
+++ b/xml/p10/node_eq_spattn_normal.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="EQ_SPATTN_NORMAL" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="EQ_SPATTN_NORMAL" reg_type="SCOM">
     <register name="EQ_SPATTN">
         <instance addr="0x20028499" reg_inst="0"/>
         <instance addr="0x20024499" reg_inst="1"/>
diff --git a/xml/p10/node_gfir_cs.xml b/xml/p10/node_gfir_cs.xml
index 315a421..9b1cd40 100644
--- a/xml/p10/node_gfir_cs.xml
+++ b/xml/p10/node_gfir_cs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="GFIR_CS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="GFIR_CS" reg_type="SCOM">
     <register name="GFIR_REG_CS">
         <instance addr="0x570F001C" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_gfir_ha.xml b/xml/p10/node_gfir_ha.xml
index 960fe8a..adbcdd1 100644
--- a/xml/p10/node_gfir_ha.xml
+++ b/xml/p10/node_gfir_ha.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="GFIR_HA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="GFIR_HA" reg_type="SCOM">
     <register name="GFIR_REG_HA">
         <instance addr="0x570F002B" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_gfir_re.xml b/xml/p10/node_gfir_re.xml
index 1f9668c..9ba583b 100644
--- a/xml/p10/node_gfir_re.xml
+++ b/xml/p10/node_gfir_re.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="GFIR_RE" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="GFIR_RE" reg_type="SCOM">
     <register name="GFIR_REG_RE">
         <instance addr="0x570F001B" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_gfir_spa.xml b/xml/p10/node_gfir_spa.xml
index b957190..cc7112a 100644
--- a/xml/p10/node_gfir_spa.xml
+++ b/xml/p10/node_gfir_spa.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="GFIR_SPA" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="GFIR_SPA" reg_type="SCOM">
     <register name="GFIR_REG_SPA">
         <instance addr="0x570F001A" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_gfir_ucs.xml b/xml/p10/node_gfir_ucs.xml
index 99e9ed9..259456b 100644
--- a/xml/p10/node_gfir_ucs.xml
+++ b/xml/p10/node_gfir_ucs.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="GFIR_UCS" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="GFIR_UCS" reg_type="SCOM">
     <register name="GFIR_REG_UCS">
         <instance addr="0x570F002A" reg_inst="0"/>
     </register>
diff --git a/xml/p10/node_hca_fir.xml b/xml/p10/node_hca_fir.xml
index 26e5b15..0258cd4 100644
--- a/xml/p10/node_hca_fir.xml
+++ b/xml/p10/node_hca_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="HCA_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="HCA_FIR" reg_type="SCOM">
     <local_fir config="W" name="HCA_FIR">
         <instance addr="0x03011D40" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_int_cq_fir.xml b/xml/p10/node_int_cq_fir.xml
index bbbafa3..1b2aa69 100644
--- a/xml/p10/node_int_cq_fir.xml
+++ b/xml/p10/node_int_cq_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="INT_CQ_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="INT_CQ_FIR" reg_type="SCOM">
     <local_fir config="W" name="INT_CQ_FIR">
         <instance addr="0x02010830" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_iohs_dlp_fir.xml b/xml/p10/node_iohs_dlp_fir.xml
index 436a42c..010229d 100644
--- a/xml/p10/node_iohs_dlp_fir.xml
+++ b/xml/p10/node_iohs_dlp_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="IOHS_DLP_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="IOHS_DLP_FIR" reg_type="SCOM">
     <local_fir config="W" name="IOHS_DLP_FIR">
         <instance addr="0x18011000" reg_inst="0"/>
         <instance addr="0x19011000" reg_inst="1"/>
diff --git a/xml/p10/node_iohs_local_fir.xml b/xml/p10/node_iohs_local_fir.xml
index dd90685..a12b142 100644
--- a/xml/p10/node_iohs_local_fir.xml
+++ b/xml/p10/node_iohs_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="IOHS_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="IOHS_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="IOHS_LOCAL_FIR">
         <instance addr="0x18040100" reg_inst="0"/>
         <instance addr="0x19040100" reg_inst="1"/>
@@ -17,11 +17,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_lpc_fir.xml b/xml/p10/node_lpc_fir.xml
index d8448b2..5f960a7 100644
--- a/xml/p10/node_lpc_fir.xml
+++ b/xml/p10/node_lpc_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="LPC_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="LPC_FIR" reg_type="SCOM">
     <local_fir config="W" name="LPC_FIR">
         <instance addr="0x03012000" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_mc_dstl_fir.xml b/xml/p10/node_mc_dstl_fir.xml
index 5de66eb..15251de 100644
--- a/xml/p10/node_mc_dstl_fir.xml
+++ b/xml/p10/node_mc_dstl_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_DSTL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="MC_DSTL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="MC_DSTL_FIR">
         <instance addr="0x0C010D00" reg_inst="0"/>
         <instance addr="0x0C010D40" reg_inst="1"/>
@@ -54,4 +54,6 @@
     <bit pos="36">A parity error local to Subchhanel B occurred.</bit>
     <bit pos="37">Spare FIR bit 37.</bit>
     <bit pos="38">Spare FIR bit 38.</bit>
+    <bit pos="39">Indicates that this subchannel has significant traffic flow.</bit>
+    <bit pos="40">Indicates that this subchannel has significant traffic flow.</bit>
 </attn_node>
diff --git a/xml/p10/node_mc_dstl_fir_p10_10.xml b/xml/p10/node_mc_dstl_fir_p10_10.xml
new file mode 100644
index 0000000..5de66eb
--- /dev/null
+++ b/xml/p10/node_mc_dstl_fir_p10_10.xml
@@ -0,0 +1,57 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_DSTL_FIR" reg_type="SCOM">
+    <local_fir config="W2" name="MC_DSTL_FIR">
+        <instance addr="0x0C010D00" reg_inst="0"/>
+        <instance addr="0x0C010D40" reg_inst="1"/>
+        <instance addr="0x0D010D00" reg_inst="2"/>
+        <instance addr="0x0D010D40" reg_inst="3"/>
+        <instance addr="0x0E010D00" reg_inst="4"/>
+        <instance addr="0x0E010D40" reg_inst="5"/>
+        <instance addr="0x0F010D00" reg_inst="6"/>
+        <instance addr="0x0F010D40" reg_inst="7"/>
+        <action attn_type="CS" config="000"/>
+        <action attn_type="RE" config="010"/>
+        <action attn_type="SPA" config="100"/>
+        <action attn_type="UCS" config="110"/>
+        <action attn_type="HA" config="001"/>
+    </local_fir>
+    <bit pos="0">AFU initiated Checkstop on Subchannel A</bit>
+    <bit pos="1">AFU initiated Recoverable Attention on Subchannel A</bit>
+    <bit pos="2">AFU initiated Special Attention on Subchannel A</bit>
+    <bit pos="3">AFU initiated Application Interrupt Attention on Subchannel A</bit>
+    <bit pos="4">AFU initiated Checkstop on Subchannel B</bit>
+    <bit pos="5">AFU initiated Recoverable Attention on Subchannel B</bit>
+    <bit pos="6">AFU initiated Special Attention on Subchannel B</bit>
+    <bit pos="7">AFU initiated Application Interrupt Attention on Subchannel B</bit>
+    <bit pos="8">Error on parity bits protecting incoming command from MCS to DSTL.</bit>
+    <bit pos="9">A credit reset was attempted while rd and wdf buffers in use.</bit>
+    <bit pos="10">DSTL Configuration Register has taken a recoverable parity error.</bit>
+    <bit pos="11">DSTL Configuration Register has taken a fatal parity error.</bit>
+    <bit pos="12">DSTL Subchannel A, a counter took an underflow or overflow error.</bit>
+    <bit pos="13">DSTL Subchannel B, a counter took an underflow or overflow error.</bit>
+    <bit pos="14">DSTL Subchannel A timed out having valid commands and not sending any flits.</bit>
+    <bit pos="15">DSTL Subchannel B timed out having valid commands and not sending any flits.</bit>
+    <bit pos="16">DSTL has detected that attached buffer on subchannel A has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
+    <bit pos="17">DSTL has detected that attached buffer on subchannel B has used more tlxvc0 or tlxvc3 credits than it has been given.</bit>
+    <bit pos="18">DSTL Subchannel A observed link going down.</bit>
+    <bit pos="19">DSTL Subchannel B observed link going down.</bit>
+    <bit pos="20">DSTL Subchannel A has entered the fail state.</bit>
+    <bit pos="21">DSTL Subchannel B has entered the fail state.</bit>
+    <bit pos="22">Channel timeout has occured on Subchannel A index.</bit>
+    <bit pos="23">Channel timeout has occured on Subchannel B index.</bit>
+    <bit pos="24">Error info from decrypt</bit>
+    <bit pos="25">Error info from decrypt</bit>
+    <bit pos="26">Error info from decrypt</bit>
+    <bit pos="27">Error info from decrypt</bit>
+    <bit pos="28">Error info from decrypt</bit>
+    <bit pos="29">Error info from encrypt</bit>
+    <bit pos="30">Error info from encrypt</bit>
+    <bit pos="31">Error info from encrypt</bit>
+    <bit pos="32">Error info from encrypt</bit>
+    <bit pos="33">On Subchhanel A, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
+    <bit pos="34">On Subchhanel B, received an AFU initiated Application Interrupt Attention when one was already being processed and issued a retry.</bit>
+    <bit pos="35">A parity error local to Subchhanel A occurred.</bit>
+    <bit pos="36">A parity error local to Subchhanel B occurred.</bit>
+    <bit pos="37">Spare FIR bit 37.</bit>
+    <bit pos="38">Spare FIR bit 38.</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_fir.xml b/xml/p10/node_mc_fir.xml
index 18bcd59..1f2e6e2 100644
--- a/xml/p10/node_mc_fir.xml
+++ b/xml/p10/node_mc_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="MC_FIR" reg_type="SCOM">
     <local_fir config="W2" name="MC_FIR">
         <instance addr="0x0C010C00" reg_inst="0"/>
         <instance addr="0x0D010C00" reg_inst="1"/>
@@ -29,8 +29,8 @@
     <bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
     <bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
     <bit pos="17">Parity Error in WAT/Debug config register.</bit>
-    <bit pos="18">Reserved[18].</bit>
-    <bit pos="19">Reserved[19].</bit>
+    <bit pos="18">PBI received overcommit signal from READ0</bit>
+    <bit pos="19">PBI received ocercommit signal from READ1</bit>
     <bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
     <bit pos="21">Reserved[21].</bit>
     <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
diff --git a/xml/p10/node_mc_fir_p10_10.xml b/xml/p10/node_mc_fir_p10_10.xml
new file mode 100644
index 0000000..cac4ae2
--- /dev/null
+++ b/xml/p10/node_mc_fir_p10_10.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_FIR" reg_type="SCOM">
+    <local_fir config="W2" name="MC_FIR">
+        <instance addr="0x0C010C00" reg_inst="0"/>
+        <instance addr="0x0D010C00" reg_inst="1"/>
+        <instance addr="0x0E010C00" reg_inst="2"/>
+        <instance addr="0x0F010C00" reg_inst="3"/>
+        <action attn_type="CS" config="000"/>
+        <action attn_type="RE" config="010"/>
+        <action attn_type="SPA" config="100"/>
+        <action attn_type="UCS" config="110"/>
+        <action attn_type="HA" config="001"/>
+    </local_fir>
+    <bit pos="0">If '1', a MC recoverable error was detected.  See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
+    <bit pos="1">If 1, a MC non-recoverable error was detected.  See the MCERPTx register description for a list of errors that cause this FIR to be set.</bit>
+    <bit pos="2">If '1', an PowerBus protocol error was detected. (for example, a HPC_WR is snooped when a HPC_WR to the same address is active).</bit>
+    <bit pos="3">If '1', a command was issued to inband address space using a</bit>
+    <bit pos="4">If '1', an address match on more that one Memory BAR was detected.</bit>
+    <bit pos="5">If set, the ECC syndrome for PowerBus write data is non-zero (for chan0/1 in pbi01, chann2/3 in pbi23)</bit>
+    <bit pos="6">Reserved[6].</bit>
+    <bit pos="7">Reserved[7].</bit>
+    <bit pos="8">If '1', a command list state machine has timed out.</bit>
+    <bit pos="9">Reserved[9].</bit>
+    <bit pos="10">Reserved[10].</bit>
+    <bit pos="11">If '1', a MCS WAT0 event has occurred.</bit>
+    <bit pos="12">If '1', a MCS WAT1 event has occurred.</bit>
+    <bit pos="13">If '1', a MCS WAT2 event has occurred.</bit>
+    <bit pos="14">If '1', a MCS WAT3 event has occurred.</bit>
+    <bit pos="15">Plus One Prefetch generated command did not hit any BARs</bit>
+    <bit pos="16">Plus One Prefetch generated command hit config or mmio BAR</bit>
+    <bit pos="17">Parity Error in WAT/Debug config register.</bit>
+    <bit pos="18">Reserved[18].</bit>
+    <bit pos="19">Reserved[19].</bit>
+    <bit pos="20">Incoming Powerbus Command hit multiple valid configured topology IDs</bit>
+    <bit pos="21">Reserved[21].</bit>
+    <bit pos="22">Access to secure memory facility failed. Improper access privilege by originating thread.</bit>
+    <bit pos="23">Caused by multiple sync commands being received by an MC at a time, or while one is pending</bit>
+</attn_node>
diff --git a/xml/p10/node_mc_local_fir.xml b/xml/p10/node_mc_local_fir.xml
index 6d2f021..858c19c 100644
--- a/xml/p10/node_mc_local_fir.xml
+++ b/xml/p10/node_mc_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="MC_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="MC_LOCAL_FIR">
         <instance addr="0x0C040100" reg_inst="0"/>
         <instance addr="0x0D040100" reg_inst="1"/>
@@ -13,11 +13,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_mc_misc_fir.xml b/xml/p10/node_mc_misc_fir.xml
index 78681c5..7178c37 100644
--- a/xml/p10/node_mc_misc_fir.xml
+++ b/xml/p10/node_mc_misc_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_MISC_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="MC_MISC_FIR" reg_type="SCOM">
     <local_fir config="W2" name="MC_MISC_FIR">
         <instance addr="0x0C010F00" reg_inst="0"/>
         <instance addr="0x0D010F00" reg_inst="1"/>
diff --git a/xml/p10/node_mc_omi_dl_fir.xml b/xml/p10/node_mc_omi_dl_fir.xml
index 6ba1924..396d0f4 100644
--- a/xml/p10/node_mc_omi_dl_fir.xml
+++ b/xml/p10/node_mc_omi_dl_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_OMI_DL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="MC_OMI_DL_FIR" reg_type="SCOM">
     <local_fir config="W" name="MC_OMI_DL_FIR">
         <instance addr="0x0C011400" reg_inst="0"/>
         <instance addr="0x0C011800" reg_inst="1"/>
diff --git a/xml/p10/node_mc_ustl_fir.xml b/xml/p10/node_mc_ustl_fir.xml
index c487b59..1dd54bf 100644
--- a/xml/p10/node_mc_ustl_fir.xml
+++ b/xml/p10/node_mc_ustl_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MC_USTL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="MC_USTL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="MC_USTL_FIR">
         <instance addr="0x0C010E00" reg_inst="0"/>
         <instance addr="0x0C010E40" reg_inst="1"/>
@@ -54,7 +54,7 @@
     <bit pos="36">flit data pariry error from dl for chanb</bit>
     <bit pos="37">internal fifo parity error for chana</bit>
     <bit pos="38">internal fifo parity error for chanb</bit>
-    <bit pos="39">Bad response detected from chana. See cerrrpts and USTLBADRESP reg for more info</bit>
+    <bit pos="39">Bad response detected from chana. See cerrrpts and USTLBADRESP reg for more info.</bit>
     <bit pos="40">Bad response detected from chanb. See cerrrpts and USTLBADRESP reg for more info</bit>
     <bit pos="41">Bad data set for data that is not valid chana</bit>
     <bit pos="42">Bad data set for data that is not valid chanb</bit>
@@ -76,5 +76,5 @@
     <bit pos="58">recov register parity error</bit>
     <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
     <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
-    <bit pos="61">USTL spare FIR bits</bit>
+    <bit pos="61">Parity error on command bus between DSTL-USTL used for chan fail command tracking</bit>
 </attn_node>
diff --git a/xml/p10/node_mc_ustl_fir_p10_10.xml b/xml/p10/node_mc_ustl_fir_p10_10.xml
new file mode 100644
index 0000000..af22fbc
--- /dev/null
+++ b/xml/p10/node_mc_ustl_fir_p10_10.xml
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="MC_USTL_FIR" reg_type="SCOM">
+    <local_fir config="W2" name="MC_USTL_FIR">
+        <instance addr="0x0C010E00" reg_inst="0"/>
+        <instance addr="0x0C010E40" reg_inst="1"/>
+        <instance addr="0x0D010E00" reg_inst="2"/>
+        <instance addr="0x0D010E40" reg_inst="3"/>
+        <instance addr="0x0E010E00" reg_inst="4"/>
+        <instance addr="0x0E010E40" reg_inst="5"/>
+        <instance addr="0x0F010E00" reg_inst="6"/>
+        <instance addr="0x0F010E40" reg_inst="7"/>
+        <action attn_type="CS" config="000"/>
+        <action attn_type="RE" config="010"/>
+        <action attn_type="SPA" config="100"/>
+        <action attn_type="UCS" config="110"/>
+        <action attn_type="HA" config="001"/>
+    </local_fir>
+    <bit pos="0">Unexpected Flit Data showed up for Chana</bit>
+    <bit pos="1">Unexpected Flit Data showed up for Chanb</bit>
+    <bit pos="2">A unsupported template for a command flit for chana</bit>
+    <bit pos="3">A unsupported template for a command flit for chanb</bit>
+    <bit pos="4">Reserved.</bit>
+    <bit pos="5">Reserved.</bit>
+    <bit pos="6">WDF CE detected on buffer output</bit>
+    <bit pos="7">WDF UE detected on buffer output</bit>
+    <bit pos="8">WDF SUE detected on buffer output</bit>
+    <bit pos="9">WDF buffer overrun detected</bit>
+    <bit pos="10">WDF detected parity on USTL tag interface</bit>
+    <bit pos="11">WDF detected a scom sequencer error</bit>
+    <bit pos="12">WDF detected a pwctl sequencer error</bit>
+    <bit pos="13">WDF detected a parity error on the misc_reg scom register</bit>
+    <bit pos="14">Parity Error detected in WDF for CL pop</bit>
+    <bit pos="15">WDF detected a non-zero syndrome (CE ore UE) from USTL</bit>
+    <bit pos="16">WDF UE detected a parity error on the CMT interface from USTL, cmd parity err, or buffer manager parity error</bit>
+    <bit pos="17">Unused</bit>
+    <bit pos="18">Unused</bit>
+    <bit pos="19">Read Buffers overflowed/underflowed (more than 64 in use)</bit>
+    <bit pos="20">WRT CE detected on buffer output</bit>
+    <bit pos="21">WRT UE detected on buffer output</bit>
+    <bit pos="22">WRT SUE detected on buffer output</bit>
+    <bit pos="23">WRT detected a scom sequencer error</bit>
+    <bit pos="24">WRT detected a parity error on the misc_reg scom register</bit>
+    <bit pos="25">WRT Data Syndrome not equal to 0 for input for write buffer.</bit>
+    <bit pos="26">No buffer error; Buffer manager parity error.</bit>
+    <bit pos="27">A fail response set as checkstop occurred for chana</bit>
+    <bit pos="28">A fail response set as checkstop occurred for chanb</bit>
+    <bit pos="29">A fail response set as recoverable occurred for chana</bit>
+    <bit pos="30">A fail response set as recoverable occurred for chanb</bit>
+    <bit pos="31">A lol drop set as checkstop occurred for chana</bit>
+    <bit pos="32">A lol drop set as checkstop occurred for chanb</bit>
+    <bit pos="33">A lol drop set as recoverable occurred for chana</bit>
+    <bit pos="34">A lol drop set as recoverable occurred for chanb</bit>
+    <bit pos="35">flit data pariry error from dl for chana</bit>
+    <bit pos="36">flit data pariry error from dl for chanb</bit>
+    <bit pos="37">internal fifo parity error for chana</bit>
+    <bit pos="38">internal fifo parity error for chanb</bit>
+    <bit pos="39">Unexpected read or write response received, chana</bit>
+    <bit pos="40">Unexpected read or write response received, chanb</bit>
+    <bit pos="41">Bad data set for data that is not valid chana</bit>
+    <bit pos="42">Bad data set for data that is not valid chanb</bit>
+    <bit pos="43">Memory read data returned in template 0, chana</bit>
+    <bit pos="44">Memory read data returned in template 0, chanb</bit>
+    <bit pos="45">Recieved mmio response while in LOL mode chana</bit>
+    <bit pos="46">Recieved mmio response while in LOL mode chanb</bit>
+    <bit pos="47">valid bad data or SUE received channel a</bit>
+    <bit pos="48">Valid bad data or SUE received chanb</bit>
+    <bit pos="49">Data is valid in data buffers without a matching response, or more than 2 data flits with template 9</bit>
+    <bit pos="50">Data is valid in data buffers without a matching response,or more than 2 data flits with template 9</bit>
+    <bit pos="51">Commit state where commit data is not marked as valid</bit>
+    <bit pos="52">Commit state where commit data is not marked as valid</bit>
+    <bit pos="53">A fifo in the ustl chana overflowed</bit>
+    <bit pos="54">A fifo in the ustl chanb overflowed</bit>
+    <bit pos="55">Invalid command decoded in USTL FF subchannel A</bit>
+    <bit pos="56">Invalid command decoded in USTL FF subchannel B</bit>
+    <bit pos="57">Fatal register parity error</bit>
+    <bit pos="58">recov register parity error</bit>
+    <bit pos="59">A chana response with an invalid combination of dlength and/or dpart received</bit>
+    <bit pos="60">A chanb response with an invalid combination of dlength and/or dpart received</bit>
+    <bit pos="61">USTL spare FIR bits</bit>
+</attn_node>
diff --git a/xml/p10/node_mcd_fir.xml b/xml/p10/node_mcd_fir.xml
index 21e7678..1007ee9 100644
--- a/xml/p10/node_mcd_fir.xml
+++ b/xml/p10/node_mcd_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="MCD_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="MCD_FIR" reg_type="SCOM">
     <local_fir config="W" name="MCD_FIR">
         <instance addr="0x03010800" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_n0_local_fir.xml b/xml/p10/node_n0_local_fir.xml
index ac7b953..76e0d08 100644
--- a/xml/p10/node_n0_local_fir.xml
+++ b/xml/p10/node_n0_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="N0_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="N0_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="N0_LOCAL_FIR">
         <instance addr="0x02040100" reg_inst="0"/>
         <action attn_type="CS" config="000"/>
@@ -10,11 +10,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_n1_local_fir.xml b/xml/p10/node_n1_local_fir.xml
index 850f8a4..93c14cb 100644
--- a/xml/p10/node_n1_local_fir.xml
+++ b/xml/p10/node_n1_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="N1_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="N1_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="N1_LOCAL_FIR">
         <instance addr="0x03040100" reg_inst="0"/>
         <action attn_type="CS" config="000"/>
@@ -10,11 +10,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
@@ -64,12 +64,12 @@
     <bit pos="53">unused</bit>
     <bit pos="54">unused</bit>
     <bit pos="55">unused</bit>
-    <bit pos="56">unused</bit>
-    <bit pos="57">unused</bit>
-    <bit pos="58">unused</bit>
-    <bit pos="59">unused</bit>
-    <bit pos="60">unused</bit>
-    <bit pos="61">unused</bit>
-    <bit pos="62">unused</bit>
+    <bit pos="56">PowerBus chip quiesce failed - triggered by firmware</bit>
+    <bit pos="57">PowerBus system quiesce failed - triggered by firmware</bit>
+    <bit pos="58">Deadman timer expired during master core wakeup by SBE - triggered by firmware</bit>
+    <bit pos="59">Switch from cache contained into system mode failed - triggered by firmware</bit>
+    <bit pos="60">Hypervisor / Hostboot / OPAL initiated Terminate Immediate (TI) - triggered by firmware</bit>
+    <bit pos="61">reserved for software use</bit>
+    <bit pos="62">reserved for software use</bit>
     <bit pos="63">ext_local_xstop</bit>
 </attn_node>
diff --git a/xml/p10/node_n1_local_fir_p10_10.xml b/xml/p10/node_n1_local_fir_p10_10.xml
new file mode 100644
index 0000000..4a25a61
--- /dev/null
+++ b/xml/p10/node_n1_local_fir_p10_10.xml
@@ -0,0 +1,75 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="N1_LOCAL_FIR" reg_type="SCOM">
+    <local_fir config="W2" name="N1_LOCAL_FIR">
+        <instance addr="0x03040100" reg_inst="0"/>
+        <action attn_type="CS" config="000"/>
+        <action attn_type="RE" config="010"/>
+        <action attn_type="SPA" config="100"/>
+        <action attn_type="UCS" config="110"/>
+        <action attn_type="HA" config="001"/>
+    </local_fir>
+    <bit pos="0">CFIR - Parity or PCB access error</bit>
+    <bit pos="1">CPLT_CTRL - PCB access error</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
+    <bit pos="7">THERM - pcb error</bit>
+    <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
+    <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
+    <bit pos="10">VOLTTRIP - Voltage sense error</bit>
+    <bit pos="11">DBG - scom parity fail</bit>
+    <bit pos="12">reserved</bit>
+    <bit pos="13">reserved</bit>
+    <bit pos="14">reserved</bit>
+    <bit pos="15">reserved</bit>
+    <bit pos="16">reserved</bit>
+    <bit pos="17">reserved</bit>
+    <bit pos="18">reserved</bit>
+    <bit pos="19">reserved</bit>
+    <bit pos="20">Trace00 - scom parity err</bit>
+    <bit pos="21">Trace01 - scom parity err - Unused in Axon,PCI</bit>
+    <bit pos="22">unused</bit>
+    <bit pos="23">unused</bit>
+    <bit pos="24">unused</bit>
+    <bit pos="25">unused</bit>
+    <bit pos="26">unused</bit>
+    <bit pos="27">unused</bit>
+    <bit pos="28">unused</bit>
+    <bit pos="29">unused</bit>
+    <bit pos="30">unused</bit>
+    <bit pos="31">unused</bit>
+    <bit pos="32">unused</bit>
+    <bit pos="33">unused</bit>
+    <bit pos="34">unused</bit>
+    <bit pos="35">unused</bit>
+    <bit pos="36">unused</bit>
+    <bit pos="37">unused</bit>
+    <bit pos="38">unused</bit>
+    <bit pos="39">unused</bit>
+    <bit pos="40">unused</bit>
+    <bit pos="41">unused</bit>
+    <bit pos="42">unused</bit>
+    <bit pos="43">unused</bit>
+    <bit pos="44">unused</bit>
+    <bit pos="45">unused</bit>
+    <bit pos="46">unused</bit>
+    <bit pos="47">unused</bit>
+    <bit pos="48">unused</bit>
+    <bit pos="49">unused</bit>
+    <bit pos="50">unused</bit>
+    <bit pos="51">unused</bit>
+    <bit pos="52">unused</bit>
+    <bit pos="53">unused</bit>
+    <bit pos="54">unused</bit>
+    <bit pos="55">unused</bit>
+    <bit pos="56">PowerBus chip quiesce failed - triggered by firmware</bit>
+    <bit pos="57">PowerBus system quiesce failed - triggered by firmware</bit>
+    <bit pos="58">Deadman timer expired during master core wakeup by SBE - triggered by firmware</bit>
+    <bit pos="59">reserved for software use</bit>
+    <bit pos="60">reserved for software use</bit>
+    <bit pos="61">reserved for software use</bit>
+    <bit pos="62">reserved for software use</bit>
+    <bit pos="63">ext_local_xstop</bit>
+</attn_node>
diff --git a/xml/p10/node_nmmu_cq_fir.xml b/xml/p10/node_nmmu_cq_fir.xml
index 8cca801..52837a7 100644
--- a/xml/p10/node_nmmu_cq_fir.xml
+++ b/xml/p10/node_nmmu_cq_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="NMMU_CQ_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="NMMU_CQ_FIR" reg_type="SCOM">
     <local_fir config="W" name="NMMU_CQ_FIR">
         <instance addr="0x02010C00" reg_inst="0"/>
         <instance addr="0x03010C00" reg_inst="1"/>
diff --git a/xml/p10/node_nmmu_fir.xml b/xml/p10/node_nmmu_fir.xml
index de561b1..ff68bd9 100644
--- a/xml/p10/node_nmmu_fir.xml
+++ b/xml/p10/node_nmmu_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="NMMU_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="NMMU_FIR" reg_type="SCOM">
     <local_fir config="W" name="NMMU_FIR">
         <instance addr="0x02010C40" reg_inst="0"/>
         <instance addr="0x03010C40" reg_inst="1"/>
diff --git a/xml/p10/node_nx_cq_fir.xml b/xml/p10/node_nx_cq_fir.xml
index 6f6ccca..d6c70ef 100644
--- a/xml/p10/node_nx_cq_fir.xml
+++ b/xml/p10/node_nx_cq_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="NX_CQ_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="NX_CQ_FIR" reg_type="SCOM">
     <local_fir config="W" name="NX_CQ_FIR">
         <instance addr="0x02011080" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_nx_dma_eng_fir.xml b/xml/p10/node_nx_dma_eng_fir.xml
index 811c4d3..5733a80 100644
--- a/xml/p10/node_nx_dma_eng_fir.xml
+++ b/xml/p10/node_nx_dma_eng_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="NX_DMA_ENG_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="NX_DMA_ENG_FIR" reg_type="SCOM">
     <local_fir config="W" name="NX_DMA_ENG_FIR">
         <instance addr="0x02011100" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_occ_fir.xml b/xml/p10/node_occ_fir.xml
index 35f1bac..769f09a 100644
--- a/xml/p10/node_occ_fir.xml
+++ b/xml/p10/node_occ_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="OCC_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="OCC_FIR" reg_type="SCOM">
     <local_fir config="" name="OCC_FIR">
         <instance addr="0x01010800" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_pau_fir_0.xml b/xml/p10/node_pau_fir_0.xml
index 01cdddf..0458b31 100644
--- a/xml/p10/node_pau_fir_0.xml
+++ b/xml/p10/node_pau_fir_0.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_FIR_0" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PAU_FIR_0" reg_type="SCOM">
     <local_fir config="" name="PAU_FIR_0">
         <instance addr="0x10010C00" reg_inst="0"/>
         <instance addr="0x11010C00" reg_inst="3"/>
diff --git a/xml/p10/node_pau_fir_1.xml b/xml/p10/node_pau_fir_1.xml
index cacea0e..e8b9718 100644
--- a/xml/p10/node_pau_fir_1.xml
+++ b/xml/p10/node_pau_fir_1.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_FIR_1" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PAU_FIR_1" reg_type="SCOM">
     <local_fir config="" name="PAU_FIR_1">
         <instance addr="0x10010C40" reg_inst="0"/>
         <instance addr="0x11010C40" reg_inst="3"/>
diff --git a/xml/p10/node_pau_fir_2.xml b/xml/p10/node_pau_fir_2.xml
index 94c1492..12b0fbd 100644
--- a/xml/p10/node_pau_fir_2.xml
+++ b/xml/p10/node_pau_fir_2.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_FIR_2" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PAU_FIR_2" reg_type="SCOM">
     <local_fir config="" name="PAU_FIR_2">
         <instance addr="0x10010C80" reg_inst="0"/>
         <instance addr="0x11010C80" reg_inst="3"/>
@@ -36,7 +36,7 @@
     <bit pos="22">RXO Internal Errors.</bit>
     <bit pos="23">OTL RXI fifo overrun.</bit>
     <bit pos="24">OTL RXI control flit data run length invalid.</bit>
-    <bit pos="25">OTL RXI opcode utilizing dLength specifies dL=0b00.</bit>
+    <bit pos="25">OTL RXI opcode utilizing dLength specifies dL=0b00 or other invalid dL.</bit>
     <bit pos="26">OTL RXI bad data received vc2.</bit>
     <bit pos="27">OTL RXI dcp2 fifo overrun.</bit>
     <bit pos="28">OTL RXI vc1 fifo overrun.</bit>
diff --git a/xml/p10/node_pau_local_fir.xml b/xml/p10/node_pau_local_fir.xml
index 9156e0a..2ab83c4 100644
--- a/xml/p10/node_pau_local_fir.xml
+++ b/xml/p10/node_pau_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PAU_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="PAU_LOCAL_FIR">
         <instance addr="0x10040100" reg_inst="0"/>
         <instance addr="0x11040100" reg_inst="1"/>
@@ -13,11 +13,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_pau_phy_fir.xml b/xml/p10/node_pau_phy_fir.xml
index 7993d08..b88151f 100644
--- a/xml/p10/node_pau_phy_fir.xml
+++ b/xml/p10/node_pau_phy_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_PHY_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="PAU_PHY_FIR" reg_type="SCOM">
     <local_fir config="W" name="PAU_PHY_FIR">
         <instance addr="0x10012C00" reg_inst="0"/>
         <instance addr="0x11012C00" reg_inst="1"/>
@@ -36,4 +36,5 @@
     <bit pos="23">FIR Register - A PPE Code Thread Locked has occurred.</bit>
     <bit pos="24">FIR Register - A PPE Code FIR 6 has occurred.</bit>
     <bit pos="25">FIR Register - A PPE Code FIR 7 has occurred.</bit>
+    <bit pos="26">FIR Register- A SCOM FSM or FIR register parity error has occurred.</bit>
 </attn_node>
diff --git a/xml/p10/node_pau_phy_fir_p10_10.xml b/xml/p10/node_pau_phy_fir_p10_10.xml
new file mode 100644
index 0000000..7993d08
--- /dev/null
+++ b/xml/p10/node_pau_phy_fir_p10_10.xml
@@ -0,0 +1,39 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PAU_PHY_FIR" reg_type="SCOM">
+    <local_fir config="W" name="PAU_PHY_FIR">
+        <instance addr="0x10012C00" reg_inst="0"/>
+        <instance addr="0x11012C00" reg_inst="1"/>
+        <instance addr="0x12012C00" reg_inst="2"/>
+        <instance addr="0x13012C00" reg_inst="3"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+        <action attn_type="UCS" config="11"/>
+    </local_fir>
+    <bit pos="0">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO0).</bit>
+    <bit pos="1">FIR Register - A RX state machine parity or mode register parity error has occurred (IOO1).</bit>
+    <bit pos="2">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI0).</bit>
+    <bit pos="3">FIR Register - A RX state machine parity or mode register parity error has occurred (OMI1).</bit>
+    <bit pos="4">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO0).</bit>
+    <bit pos="5">FIR Register - A TX state machine parity or mode register parity error has occurred (IOO1).</bit>
+    <bit pos="6">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI0).</bit>
+    <bit pos="7">FIR Register - A TX state machine parity or mode register parity error has occurred (OMI1).</bit>
+    <bit pos="8">FIR Register - A TX ZCAL state machine parity or mode register parity error has occurred.</bit>
+    <bit pos="9">FIR Register - A PPE internal error has occurred.</bit>
+    <bit pos="10">FIR Register - A PPE external error has occurred.</bit>
+    <bit pos="11">FIR Register - A PPE Halt due to Watchdog or Interrupt has occurred.</bit>
+    <bit pos="12">FIR Register - A PPE Halt due to Debug has occurred.</bit>
+    <bit pos="13">FIR Register - PPE Halted.</bit>
+    <bit pos="14">FIR Register - A PPE Watchdog Timeout has occurred.</bit>
+    <bit pos="15">FIR Register - A PPE Array Scrub was missed.</bit>
+    <bit pos="16">FIR Register - A PPE Array uncorrectable error has occurred.</bit>
+    <bit pos="17">FIR Register - A PPE Array correctable error has occurred.</bit>
+    <bit pos="18">FIR Register - A PPE Code Recal Abort has occurred.</bit>
+    <bit pos="19">FIR Register - A PPE Code Fatal Error has occurred.</bit>
+    <bit pos="20">FIR Register - A PPE Code Warning has occurred.</bit>
+    <bit pos="21">FIR Register - A PPE Code DFT Error has occurred.</bit>
+    <bit pos="22">FIR Register - A PPE Code Recal Not Run has occurred.</bit>
+    <bit pos="23">FIR Register - A PPE Code Thread Locked has occurred.</bit>
+    <bit pos="24">FIR Register - A PPE Code FIR 6 has occurred.</bit>
+    <bit pos="25">FIR Register - A PPE Code FIR 7 has occurred.</bit>
+</attn_node>
diff --git a/xml/p10/node_pau_ptl_fir.xml b/xml/p10/node_pau_ptl_fir.xml
index 6c89c18..4086969 100644
--- a/xml/p10/node_pau_ptl_fir.xml
+++ b/xml/p10/node_pau_ptl_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PAU_PTL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PAU_PTL_FIR" reg_type="SCOM">
     <local_fir config="W" name="PAU_PTL_FIR">
         <instance addr="0x10011800" reg_inst="0"/>
         <instance addr="0x11011800" reg_inst="1"/>
diff --git a/xml/p10/node_pb_ext_fir.xml b/xml/p10/node_pb_ext_fir.xml
index cfc1b5e..2e4aad4 100644
--- a/xml/p10/node_pb_ext_fir.xml
+++ b/xml/p10/node_pb_ext_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PB_EXT_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PB_EXT_FIR" reg_type="SCOM">
     <local_fir config="" name="PB_EXT_FIR">
         <instance addr="0x030113AE" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_pb_station_fir.xml b/xml/p10/node_pb_station_fir.xml
deleted file mode 100644
index 5ec21f1..0000000
--- a/xml/p10/node_pb_station_fir.xml
+++ /dev/null
@@ -1,46 +0,0 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PB_STATION_FIR" reg_type="SCOM">
-    <local_fir config="" name="PB_STATION_FIR">
-        <instance addr="0x03011200" reg_inst="0"/>
-        <instance addr="0x03011240" reg_inst="1"/>
-        <instance addr="0x03011280" reg_inst="2"/>
-        <instance addr="0x030112C0" reg_inst="3"/>
-        <instance addr="0x03011000" reg_inst="4"/>
-        <instance addr="0x03011040" reg_inst="5"/>
-        <instance addr="0x03011080" reg_inst="6"/>
-        <instance addr="0x030110C0" reg_inst="7"/>
-        <instance addr="0x03011100" reg_inst="8"/>
-        <instance addr="0x03011140" reg_inst="9"/>
-        <instance addr="0x03011180" reg_inst="10"/>
-        <instance addr="0x030111C0" reg_inst="11"/>
-        <instance addr="0x03011300" reg_inst="12"/>
-        <instance addr="0x03011340" reg_inst="13"/>
-        <instance addr="0x03011380" reg_inst="14"/>
-        <instance addr="0x030113C0" reg_inst="15"/>
-        <action attn_type="CS" config="00"/>
-        <action attn_type="RE" config="01"/>
-        <action attn_type="SPA" config="10"/>
-    </local_fir>
-    <bit pos="0">protocol_error</bit>
-    <bit pos="1">overflow_error</bit>
-    <bit pos="2">hw_parity_error</bit>
-    <bit pos="3">fir_spare_3</bit>
-    <bit pos="4">coherency_error</bit>
-    <bit pos="5">cresp_addr_error</bit>
-    <bit pos="6">cresp_error</bit>
-    <bit pos="7">hang_recovery_limit_error</bit>
-    <bit pos="8">fir_spare_8</bit>
-    <bit pos="9">hang_recovery_gte_level1</bit>
-    <bit pos="10">force_mp_ipl</bit>
-    <bit pos="11">pb_cmd_snooper_error</bit>
-    <bit pos="12">data_overflow_error</bit>
-    <bit pos="13">data_protocol_error</bit>
-    <bit pos="14">data_route_error</bit>
-    <bit pos="15">fir_compab_trigger</bit>
-    <bit pos="16">link0_protocol_error</bit>
-    <bit pos="17">link0_overflow_error</bit>
-    <bit pos="18">link0_hw_parity_error</bit>
-    <bit pos="19">link1_protocol_error</bit>
-    <bit pos="20">link1_overflow_error</bit>
-    <bit pos="21">link1_hw_parity_error</bit>
-</attn_node>
diff --git a/xml/p10/node_pb_station_fir_en1.xml b/xml/p10/node_pb_station_fir_en1.xml
new file mode 100644
index 0000000..60ba586
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_en1.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_EN1" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_EN1">
+        <instance addr="0x03011200" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_en2.xml b/xml/p10/node_pb_station_fir_en2.xml
new file mode 100644
index 0000000..ea2010d
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_en2.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_EN2" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_EN2">
+        <instance addr="0x03011240" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_en3.xml b/xml/p10/node_pb_station_fir_en3.xml
new file mode 100644
index 0000000..e12e88e
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_en3.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_EN3" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_EN3">
+        <instance addr="0x03011280" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_en4.xml b/xml/p10/node_pb_station_fir_en4.xml
new file mode 100644
index 0000000..61e45e4
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_en4.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_EN4" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_EN4">
+        <instance addr="0x030112C0" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_eq.xml b/xml/p10/node_pb_station_fir_eq.xml
new file mode 100644
index 0000000..0ebb2f1
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_eq.xml
@@ -0,0 +1,38 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_EQ" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_EQ">
+        <instance addr="0x03011000" reg_inst="0"/>
+        <instance addr="0x03011040" reg_inst="1"/>
+        <instance addr="0x03011080" reg_inst="2"/>
+        <instance addr="0x030110C0" reg_inst="3"/>
+        <instance addr="0x03011100" reg_inst="4"/>
+        <instance addr="0x03011140" reg_inst="5"/>
+        <instance addr="0x03011180" reg_inst="6"/>
+        <instance addr="0x030111C0" reg_inst="7"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_es1.xml b/xml/p10/node_pb_station_fir_es1.xml
new file mode 100644
index 0000000..d3f365c
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_es1.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_ES1" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_ES1">
+        <instance addr="0x03011300" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_es2.xml b/xml/p10/node_pb_station_fir_es2.xml
new file mode 100644
index 0000000..a94616f
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_es2.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_ES2" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_ES2">
+        <instance addr="0x03011340" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_es3.xml b/xml/p10/node_pb_station_fir_es3.xml
new file mode 100644
index 0000000..1a17938
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_es3.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_20" name="PB_STATION_FIR_ES3" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_ES3">
+        <instance addr="0x03011380" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">inactive_link_error</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">active_link_error</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_es3_p10_10.xml b/xml/p10/node_pb_station_fir_es3_p10_10.xml
new file mode 100644
index 0000000..3439137
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_es3_p10_10.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PB_STATION_FIR_ES3" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_ES3">
+        <instance addr="0x03011380" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pb_station_fir_es4.xml b/xml/p10/node_pb_station_fir_es4.xml
new file mode 100644
index 0000000..8fa5e09
--- /dev/null
+++ b/xml/p10/node_pb_station_fir_es4.xml
@@ -0,0 +1,31 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10,P10_20" name="PB_STATION_FIR_ES4" reg_type="SCOM">
+    <local_fir config="" name="PB_STATION_FIR_ES4">
+        <instance addr="0x030113C0" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+        <action attn_type="SPA" config="10"/>
+    </local_fir>
+    <bit pos="0">protocol_error</bit>
+    <bit pos="1">overflow_error</bit>
+    <bit pos="2">hw_parity_error</bit>
+    <bit pos="3">fir_spare_3</bit>
+    <bit pos="4">coherency_error</bit>
+    <bit pos="5">cresp_addr_error</bit>
+    <bit pos="6">cresp_error</bit>
+    <bit pos="7">hang_recovery_limit_error</bit>
+    <bit pos="8">fir_spare_8</bit>
+    <bit pos="9">hang_recovery_gte_level1</bit>
+    <bit pos="10">force_mp_ipl</bit>
+    <bit pos="11">pb_cmd_snooper_error</bit>
+    <bit pos="12">data_overflow_error</bit>
+    <bit pos="13">data_protocol_error</bit>
+    <bit pos="14">data_route_error</bit>
+    <bit pos="15">fir_compab_trigger</bit>
+    <bit pos="16">link0_protocol_error</bit>
+    <bit pos="17">link0_overflow_error</bit>
+    <bit pos="18">link0_hw_parity_error</bit>
+    <bit pos="19">link1_protocol_error</bit>
+    <bit pos="20">link1_overflow_error</bit>
+    <bit pos="21">link1_hw_parity_error</bit>
+</attn_node>
diff --git a/xml/p10/node_pbaf_fir.xml b/xml/p10/node_pbaf_fir.xml
index 0eb283d..8d6c940 100644
--- a/xml/p10/node_pbaf_fir.xml
+++ b/xml/p10/node_pbaf_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PBAF_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PBAF_FIR" reg_type="SCOM">
     <local_fir config="" name="PBAF_FIR">
         <instance addr="0x03011DC0" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_pbao_fir.xml b/xml/p10/node_pbao_fir.xml
index 6e2318f..3753302 100644
--- a/xml/p10/node_pbao_fir.xml
+++ b/xml/p10/node_pbao_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PBAO_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PBAO_FIR" reg_type="SCOM">
     <local_fir config="" name="PBAO_FIR">
         <instance addr="0x01010CC0" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
diff --git a/xml/p10/node_pci_etu_fir.xml b/xml/p10/node_pci_etu_fir.xml
index 65d43c4..d64ba50 100644
--- a/xml/p10/node_pci_etu_fir.xml
+++ b/xml/p10/node_pci_etu_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PCI_ETU_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PCI_ETU_FIR" reg_type="SCOM">
     <local_fir config="W" name="PCI_ETU_FIR">
         <instance addr="0x08010908" reg_inst="0"/>
         <instance addr="0x08010948" reg_inst="1"/>
diff --git a/xml/p10/node_pci_fir.xml b/xml/p10/node_pci_fir.xml
index bd72203..bd68142 100644
--- a/xml/p10/node_pci_fir.xml
+++ b/xml/p10/node_pci_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PCI_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PCI_FIR" reg_type="SCOM">
     <local_fir config="W" name="PCI_FIR">
         <instance addr="0x08010840" reg_inst="0"/>
         <instance addr="0x08010880" reg_inst="1"/>
diff --git a/xml/p10/node_pci_iop_fir.xml b/xml/p10/node_pci_iop_fir.xml
index 97cce0a..035f31c 100644
--- a/xml/p10/node_pci_iop_fir.xml
+++ b/xml/p10/node_pci_iop_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PCI_IOP_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PCI_IOP_FIR" reg_type="SCOM">
     <local_fir config="" name="PCI_IOP_FIR">
         <instance addr="0x08011100" reg_inst="0"/>
         <instance addr="0x08011500" reg_inst="1"/>
diff --git a/xml/p10/node_pci_local_fir.xml b/xml/p10/node_pci_local_fir.xml
index b992eff..8c4afdf 100644
--- a/xml/p10/node_pci_local_fir.xml
+++ b/xml/p10/node_pci_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PCI_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PCI_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="PCI_LOCAL_FIR">
         <instance addr="0x08040100" reg_inst="0"/>
         <instance addr="0x09040100" reg_inst="1"/>
@@ -11,11 +11,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
diff --git a/xml/p10/node_pci_nest_fir.xml b/xml/p10/node_pci_nest_fir.xml
index 6f5b261..d594ebe 100644
--- a/xml/p10/node_pci_nest_fir.xml
+++ b/xml/p10/node_pci_nest_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PCI_NEST_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="PCI_NEST_FIR" reg_type="SCOM">
     <local_fir config="W" name="PCI_NEST_FIR">
         <instance addr="0x03011840" reg_inst="0"/>
         <instance addr="0x03011880" reg_inst="1"/>
diff --git a/xml/p10/node_psihb_fir.xml b/xml/p10/node_psihb_fir.xml
index fa696a5..fa6cde8 100644
--- a/xml/p10/node_psihb_fir.xml
+++ b/xml/p10/node_psihb_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="PSIHB_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_20" name="PSIHB_FIR" reg_type="SCOM">
     <local_fir config="" name="PSIHB_FIR">
         <instance addr="0x03011D00" reg_inst="0"/>
         <action attn_type="CS" config="00"/>
@@ -19,13 +19,13 @@
     <bit pos="11">PB parity error</bit>
     <bit pos="12">FSP tried access to trusted space</bit>
     <bit pos="13">Unexpected PB CRESP or DATA</bit>
-    <bit pos="14">Interrupt register change while interrupt still pending</bit>
-    <bit pos="15">PSI Interrupt address Error</bit>
-    <bit pos="16">OCC Interrupt address Error</bit>
-    <bit pos="17">FSI Interrupt address Error</bit>
-    <bit pos="18">LPC Interrupt address Error</bit>
-    <bit pos="19">LOCAL ERROR Interrupt address Error</bit>
-    <bit pos="20">HOST ERROR Interrupt address Error</bit>
+    <bit pos="14">Spare firs tied to zero</bit>
+    <bit pos="15">Spare firs tied to zero</bit>
+    <bit pos="16">Spare firs tied to zero</bit>
+    <bit pos="17">Spare firs tied to zero</bit>
+    <bit pos="18">Spare firs tied to zero</bit>
+    <bit pos="19">Spare firs tied to zero</bit>
+    <bit pos="20">Spare firs tied to zero</bit>
     <bit pos="21">PSI global error bit 0</bit>
     <bit pos="22">PSI global error bit 1</bit>
     <bit pos="23">Upstream error</bit>
diff --git a/xml/p10/node_psihb_fir_p10_10.xml b/xml/p10/node_psihb_fir_p10_10.xml
new file mode 100644
index 0000000..fa696a5
--- /dev/null
+++ b/xml/p10/node_psihb_fir_p10_10.xml
@@ -0,0 +1,36 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<attn_node model_ec="P10_10" name="PSIHB_FIR" reg_type="SCOM">
+    <local_fir config="" name="PSIHB_FIR">
+        <instance addr="0x03011D00" reg_inst="0"/>
+        <action attn_type="CS" config="00"/>
+        <action attn_type="RE" config="01"/>
+    </local_fir>
+    <bit pos="0">CE from PowerBus data</bit>
+    <bit pos="1">UE from PowerBus data</bit>
+    <bit pos="2">SUE from PowerBus data</bit>
+    <bit pos="3">Interrupt Condition present in PSIHB</bit>
+    <bit pos="4">Interrupt from FSP is being processed</bit>
+    <bit pos="5">CE from PSILL data</bit>
+    <bit pos="6">UE from PSILL data</bit>
+    <bit pos="7">Error bit set, ignores the interrupt mask</bit>
+    <bit pos="8">Invalid TType Hit on PHB or FSP bar</bit>
+    <bit pos="9">Invalid CResp returned to command issued by PSIHB</bit>
+    <bit pos="10">PowerBus time out waiting for data grant</bit>
+    <bit pos="11">PB parity error</bit>
+    <bit pos="12">FSP tried access to trusted space</bit>
+    <bit pos="13">Unexpected PB CRESP or DATA</bit>
+    <bit pos="14">Interrupt register change while interrupt still pending</bit>
+    <bit pos="15">PSI Interrupt address Error</bit>
+    <bit pos="16">OCC Interrupt address Error</bit>
+    <bit pos="17">FSI Interrupt address Error</bit>
+    <bit pos="18">LPC Interrupt address Error</bit>
+    <bit pos="19">LOCAL ERROR Interrupt address Error</bit>
+    <bit pos="20">HOST ERROR Interrupt address Error</bit>
+    <bit pos="21">PSI global error bit 0</bit>
+    <bit pos="22">PSI global error bit 1</bit>
+    <bit pos="23">Upstream error</bit>
+    <bit pos="24">Spare fir</bit>
+    <bit pos="25">Spare fir</bit>
+    <bit pos="26">Spare fir</bit>
+    <bit pos="27">fir parity Error</bit>
+</attn_node>
diff --git a/xml/p10/node_tp_local_fir.xml b/xml/p10/node_tp_local_fir.xml
index 6c82c2f..ba5bf15 100644
--- a/xml/p10/node_tp_local_fir.xml
+++ b/xml/p10/node_tp_local_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="TP_LOCAL_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="TP_LOCAL_FIR" reg_type="SCOM">
     <local_fir config="W2" name="TP_LOCAL_FIR">
         <instance addr="0x01040100" reg_inst="0"/>
         <action attn_type="CS" config="000"/>
@@ -10,11 +10,11 @@
     </local_fir>
     <bit pos="0">CFIR - Parity or PCB access error</bit>
     <bit pos="1">CPLT_CTRL - PCB access error</bit>
-    <bit pos="2">CC - PCB access error - read and clear nn03000F</bit>
-    <bit pos="3">CC - Clock Control Error - read and clear nn03000F</bit>
-    <bit pos="4">PSC - PSCOM access error - read and clear nn01001</bit>
-    <bit pos="5">PSC - internal or ring interface error - read and clear nn01001</bit>
-    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out check ERR_STATUS_REG 0xnn050013</bit>
+    <bit pos="2">CC - PCB access error</bit>
+    <bit pos="3">CC - Clock Control Error</bit>
+    <bit pos="4">PSC - PSCOM access error</bit>
+    <bit pos="5">PSC - internal or ring interface error</bit>
+    <bit pos="6">THERM - pwr_comp_err, skitter_comp_err, scan_init_version_reg_parity_err_out , count_state_err_out</bit>
     <bit pos="7">THERM - pcb error</bit>
     <bit pos="8">THERMTRIP - Critical temperature indicator</bit>
     <bit pos="9">THERMTRIP - Fatal temperature indicator</bit>
@@ -31,12 +31,12 @@
     <bit pos="20">Trace00 - scom parity err</bit>
     <bit pos="21">ITR - FMU error</bit>
     <bit pos="22">ITR - PCB error</bit>
-    <bit pos="23">PCB Master - timeout - read and clear 000F001F - RECOV</bit>
-    <bit pos="24">I2CM - Parity errors, Can be considered as recoverable error</bit>
+    <bit pos="23">PCB Master - timeout</bit>
+    <bit pos="24">I2CM - Parity errors</bit>
     <bit pos="25">TOD - any error</bit>
     <bit pos="26">TOD - access error PIB</bit>
     <bit pos="27">TOD - unused tie0</bit>
-    <bit pos="28">PCB Slave - read and clear nn0F001F RECOV</bit>
+    <bit pos="28">Error reported from one or more PCB Slaves</bit>
     <bit pos="29">SBE - PPE int hardware error</bit>
     <bit pos="30">SBE - PPE ext hardware error</bit>
     <bit pos="31">SBE- PPE code error</bit>
@@ -46,23 +46,23 @@
     <bit pos="35">SBE - unused tie0</bit>
     <bit pos="36">SBE - unused tie0</bit>
     <bit pos="37">SBE - PPE triggers DBG</bit>
-    <bit pos="38">OTP - SCOM access errors &amp; single ecc correctable errors. Can be considered as Recoverable type.</bit>
+    <bit pos="38">OTP - SCOM access errors &amp; single ecc correctable errors</bit>
     <bit pos="39">TPIO External Trigger</bit>
-    <bit pos="40">PCB Master - DECMCAST_GRP_ERR - read and clear 000F001F - RECOV</bit>
-    <bit pos="41">PCB Master - Parity ERR - read and clear 000F001F - RECOV</bit>
+    <bit pos="40">PCB Master - Multicast group member count underrun (MC misconfig)</bit>
+    <bit pos="41">PCB Master - Parity ERR</bit>
     <bit pos="42">RCS - OSC0 Error</bit>
     <bit pos="43">RCS - OSC1 Error</bit>
-    <bit pos="44">RCS - Delay line 0 unlock</bit>
-    <bit pos="45">RCS - Delay line 1 unlock</bit>
+    <bit pos="44">RCS - Up/down counter A unlock</bit>
+    <bit pos="45">RCS - Up/down counter B unlock</bit>
     <bit pos="46">PIBMEM</bit>
     <bit pos="47">PIBMEM</bit>
-    <bit pos="48">OTP - Combination of ecc uncorrectable error and correctable error counter overflow - Can be considered as checkstop</bit>
-    <bit pos="49">DPLL_FIR_NEST_DCO_EMPTY</bit>
-    <bit pos="50">DPLL_FIR_NEST_DCO_FULL</bit>
-    <bit pos="51">DPLL_FIR_NEST_INT_ERROR</bit>
-    <bit pos="52">DPLL_FIR_PAU_DCO_EMPTY</bit>
-    <bit pos="53">DPLL_FIR_PAU_DCO_FULL</bit>
-    <bit pos="54">DPLL_FIR_PAU_INT_ERROR</bit>
+    <bit pos="48">OTP - ECC UE or CE count overflow</bit>
+    <bit pos="49">Nest DPLL: DCO empty</bit>
+    <bit pos="50">Nest DPLL: DCO full</bit>
+    <bit pos="51">Nest DPLL: internal error</bit>
+    <bit pos="52">PAU DPLL: DCO empty</bit>
+    <bit pos="53">PAU DPLL: DCO full</bit>
+    <bit pos="54">PAU DPLL: internal error</bit>
     <bit pos="55">SPI Master 0 Err</bit>
     <bit pos="56">SPI Master 1 Err</bit>
     <bit pos="57">SPI Master 2 Err</bit>
diff --git a/xml/p10/node_vas_fir.xml b/xml/p10/node_vas_fir.xml
index 0a90314..d64212d 100644
--- a/xml/p10/node_vas_fir.xml
+++ b/xml/p10/node_vas_fir.xml
@@ -1,5 +1,5 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<attn_node model_ec="P10_10" name="VAS_FIR" reg_type="SCOM">
+<attn_node model_ec="P10_10,P10_20" name="VAS_FIR" reg_type="SCOM">
     <local_fir config="W" name="VAS_FIR">
         <instance addr="0x02011400" reg_inst="0"/>
         <action attn_type="CS" config="00"/>