diff --git a/p9_cfam.hpp b/p9_cfam.hpp
index 07b251d..0cf5c02 100644
--- a/p9_cfam.hpp
+++ b/p9_cfam.hpp
@@ -6,8 +6,12 @@
 {
 namespace p9
 {
+
+static constexpr uint32_t P9_DD10_CHIPID           = 0x120D1049;
+
 static constexpr uint16_t P9_FSI_A_SI1S            = 0x081C;
 static constexpr uint16_t P9_LL_MODE_REG           = 0x0840;
+static constexpr uint16_t P9_FSI2PIB_CHIPID        = 0x100A;
 static constexpr uint16_t P9_FSI2PIB_INTERRUPT     = 0x100B;
 static constexpr uint16_t P9_FSI2PIB_TRUE_MASK     = 0x100D;
 static constexpr uint16_t P9_CBS_CS                = 0x2801;
diff --git a/procedures/p9/vcs_workaround.cpp b/procedures/p9/vcs_workaround.cpp
index 07e7fd0..1cb51b5 100644
--- a/procedures/p9/vcs_workaround.cpp
+++ b/procedures/p9/vcs_workaround.cpp
@@ -39,6 +39,18 @@
     Targeting targets;
     const auto& master = *(targets.begin());
 
+    // First determine if we need to run this workaround (not needed on chips
+    // which are not DD1.0)
+    // Mixing DD1.0 parts with other levels is not allowed so just look
+    // at the first chip
+    auto chipID = readReg(master, P9_FSI2PIB_CHIPID);
+    if (chipID != P9_DD10_CHIPID)
+    {
+        log<level::INFO>("P9 procedure vcsWorkaround not needed",
+                         entry("CHIPID=0x%08X", chipID));
+        return;
+    }
+
     log<level::INFO>("Running P9 procedure vcsWorkaround",
                      entry("NUM_PROCS=%d", targets.size()));