tree fc71cfc4f0edcfa0040c547edc04abf968f0ddbb
parent 91bf93e0d37d831d8186e1540954f7894a74fed5
author Jayanth Othayoth <ojayanth@in.ibm.com> 1662723598 -0500
committer Jayanth Othayoth <ojayanth@in.ibm.com> 1663057249 -0500

 PHAL: Added clock register data in the clock daily data logger

    Informational log includes all the present clock register information
    required for clock debug.

Tested:
    "Clock0": "Functional",
    "Clock0 path": "/bmc0/i2c-0/oscrefclk0",
    "Clock0_0x00": " 37 d0 40 03 00 bf 00 02",
    "Clock0_0x08": " 01 00 00 00 00 00 21 0b",
    "Clock0_0x10": " 17 12 01 00 30 24 04 72",
    :: ::
    "Clock0_0xe0": " 00 00 00 00 00 00 00 00",
    "Clock0_0xe8": " 00 00 c1 00 00 00 00 00",
    "Clock0_0xf0": " 00 00 00 00 00 00 00 00",
    "Clock0_0xf8": " 00 00 00 00 00 00 00 00"

Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: Ic536337f494febfa92162c0387cf2995e24e9b10