diff --git a/p9_procedures.cpp b/p9_procedures.cpp
index 37a3b10..188fec0 100644
--- a/p9_procedures.cpp
+++ b/p9_procedures.cpp
@@ -13,20 +13,86 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
+#include <phosphor-logging/log.hpp>
+#include "cfam_access.hpp"
+#include "p9_cfam.hpp"
+#include "targeting.hpp"
+
 namespace openpower
 {
 namespace p9
 {
 
+using namespace phosphor::logging;
+using namespace openpower::cfam::access;
+using namespace openpower::cfam::p9;
+using namespace openpower::targeting;
+
 void startHost()
 {
+    Targeting targets;
+    const auto& master = *(targets.begin());
 
+    log<level::INFO>("Running P9 procedure startHost",
+                     entry("NUM_PROCS=%d", targets.size()));
+
+
+    //Ensure asynchronous clock mode is set
+    writeReg(master, P9_LL_MODE_REG, 0x00000001);
+
+    //Clock mux select override
+    for (const auto& t : targets)
+    {
+        writeRegWithMask(t, P9_ROOT_CTRL8,
+                         0x0000000C, 0x0000000C);
+    }
+
+    //Enable P9 checkstop to be reported to the BMC
+
+    //Setup FSI2PIB to report checkstop
+    writeReg(master, P9_FSI_A_SI1S, 0x20000000);
+
+    //Enable Xstop/ATTN interrupt
+    writeReg(master, P9_FSI2PIB_TRUE_MASK, 0x60000000);
+
+    //Arm it
+    writeReg(master, P9_FSI2PIB_INTERRUPT, 0xFFFFFFFF);
+
+    //Kick off the SBE to start the boot
+
+    //First ensure ISTEP stepping isn't enabled
+    writeReg(master, P9_SCRATCH_REGISTER_8, 0x20000000);
+
+    //Start the SBE
+    writeRegWithMask(master, P9_CBS_CS, 0x80000000, 0x80000000);
 }
 
 
 void vcsWorkaround()
 {
+    Targeting targets;
+    const auto& master = *(targets.begin());
 
+    log<level::INFO>("Running P9 procedure vcsWorkaround",
+                     entry("NUM_PROCS=%d", targets.size()));
+
+    //Set asynchronous clock mode
+    writeReg(master, P9_LL_MODE_REG, 0x00000001);
+
+    for (const auto& t : targets)
+    {
+        //Unfence PLL controls
+        writeRegWithMask(t, P9_ROOT_CTRL0,
+                         0x00000000, 0x00010000);
+
+        //Assert Perv chiplet endpoint reset
+        writeRegWithMask(t, P9_PERV_CTRL0,
+                         0x40000000, 0x40000000);
+
+        //Enable Nest PLL
+        writeRegWithMask(t, P9_PERV_CTRL0,
+                         0x00000001, 0x00000001);
+    }
 }
 
 }