Fix related P10 SPI mux settings
Existing code set all 32 bits to true for the CFAM 2818
register. Which is not correct because First 4 bits are
for the SPI mux related settings in cfam 2818 register.
Fixed with correct settings based register definition
Tested: Verified in hardware
Signed-off-by: Jayanth Othayoth <ojayanth@in.ibm.com>
Change-Id: I3b9281bee1980a355cc44238dccace2441d625b6
diff --git a/procedures/phal/set_SPI_mux.cpp b/procedures/phal/set_SPI_mux.cpp
index 4300a81..eebd23b 100644
--- a/procedures/phal/set_SPI_mux.cpp
+++ b/procedures/phal/set_SPI_mux.cpp
@@ -38,7 +38,7 @@
for (const auto& t : targets)
{
- writeReg(t, P10_ROOT_CTRL8, 0xFFFFFFFF);
+ writeRegWithMask(t, P10_ROOT_CTRL8, 0xF0000000, 0xF0000000);
}
}