tree dbe1418c544e8fe4085d59f083c412627c0ad546
parent f7f3f4ab5a5dbaf23abdb1e219eaaf112fea5690
author Ramesh Iyyar <rameshi1@in.ibm.com> 1600760811 -0500
committer Jayanth Othayoth <ojayanth@in.ibm.com> 1603089885 +0000

phal: Added HW callout info into PEL

- If any hardware procedure (hwp) failed during execution of ipling then
  that particular hwp will request the required hardware's (which are defined
  error xml of respective hwp) need to be callout. So, this patch will create
  PEL records based on given FFDC (First Failure Data Collection) by phal
  during failure.

- Also, this patch will deconfigure (marking hardware as non-functional
  i.e update HWAS_STATE attribute with respective bitfield value in POWER CEC
  device tree) required hardwares which are given as part of phal ffdc data.

- Used "libfmt" to format trace with field value instead adding as entry
  in journal so, while debugging it will be easy instead looking each entry.

TestedBy:

"User Data 1": {
    "Section Version": "1",
    "Sub-section type": "1",
    "Created by": "0x2000",
    "HWP_CDG_TGT_01_CO_PRIORITY": "MEDIUM",
    "HWP_CDG_TGT_01_CO_REQ": "true",
    "HWP_CDG_TGT_01_DECONF_REQ": "false",
    "HWP_CDG_TGT_01_GUARD_REQ": "false",
    "HWP_CDG_TGT_01_GUARD_TYPE": "GARD_Fatal",
    "HWP_CDG_TGT_01_LOC_CODE": "Ufcs-P0-C15",
    "HWP_CDG_TGT_01_PHYS_PATH": "physical:sys-0/node-0/proc-0",
    "HWP_FFDC_ATTR_CP_REFCLOCK_SELECT_VALUE": "00",
    "HWP_FFDC_RCS_CLOCK_TEST_IN": "01",
    "HWP_FFDC_READ_SNS1LTH": "0c000000",
    "HWP_HW_CO_01_CLK_POS": "0",
    "HWP_HW_CO_01_HW_ID": "PROC_REF_CLOCK",
    "HWP_HW_CO_01_LOC_CODE": "Ufcs-P0-C15",
    "HWP_HW_CO_01_PHYS_PATH": "physical:sys-0/node-0/proc-0",
    "HWP_HW_CO_01_PRIORITY": "HIGH",
    "HWP_RC": "RC_CLOCK_TEST_OUT_RCS_ERR",
    "HWP_RC_DESC": "One or more processor reference clocks not toggling",
    "LOG000 2020-09-22 04:12:58": "Running p10_clock_test HWP on processor 0\n",
    "LOG001 2020-09-22 04:12:58": "inf: p10_clock_test:60
p10_clock_test: Entering ...\n",
    "LOG002 2020-09-22 04:12:58": "inf: p10_clock_test_latches:106
p10_clock_test_latches: Entering
...\n",
    "LOG003 2020-09-22 04:12:58": "err: CLOCK_TEST_OUT_RCS_ERR:4036
One or more processor reference clocks not toggling\n",
    "LOG004 2020-09-22 04:12:58": "err: _setHwpError:120 _setHwpError:
Creating HWP error 0x927e1c\n",
    "LOG005 2020-09-22 04:12:58": "inf: addErrorInfo:344
addErrorInfo: Adding cdg (1:0:0), pri: 1, gtyp: 227\n",
    "LOG006 2020-09-22 04:12:58": "err: p10_clock_test_latches:130 Clock A is bad\n",
    "LOG007 2020-09-22 04:12:58": "err: p10_clock_test:76
p10_clock_test_latches(i_target_chip, true) failed.\n",
    "LOG008 2020-09-22 04:12:58": "HWP clock_test failed on proc 0, rc=2124995320\n",
    "_PID": "1209"
},
"User Data 2": {
    "Section Version": "1",
    "Sub-section type": "1",
    "Created by": "0x2000",
    "Data": [
        {
            "LocationCode": "Ufcs-P0-C15",
            "MRUs": [
                {
                    "ID": 65536,
                    "Priority": "H"
                }
            ],
            "Priority": "H"
        },
        {
            "Deconfigured": false,
            "Guarded": false,
            "LocationCode": "Ufcs-P0-C15",
            "MRUs": [
                {
                    "ID": 65536,
                    "Priority": "M"
                }
            ],
            "Priority": "M"
        }
    ]
}

Signed-off-by: Ramesh Iyyar <rameshi1@in.ibm.com>
Change-Id: I4462c46747598166b085990e1d82cb2998b9e06b