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Matt Spinlerf716f322017-02-28 09:37:38 -06001/**
2 * Copyright © 2017 IBM Corporation
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
Matt Spinler6419b632017-02-28 10:10:50 -060016#include <phosphor-logging/log.hpp>
17#include "cfam_access.hpp"
18#include "p9_cfam.hpp"
19#include "targeting.hpp"
20
Matt Spinlerf716f322017-02-28 09:37:38 -060021namespace openpower
22{
23namespace p9
24{
25
Matt Spinler6419b632017-02-28 10:10:50 -060026using namespace phosphor::logging;
27using namespace openpower::cfam::access;
28using namespace openpower::cfam::p9;
29using namespace openpower::targeting;
30
Matt Spinler83e37322017-03-09 11:23:17 -060031
32/**
33 * @brief Starts the self boot engine on P9 position 0 to kick off a boot.
34 * @return void
35 */
Matt Spinlerf716f322017-02-28 09:37:38 -060036void startHost()
37{
Matt Spinler6419b632017-02-28 10:10:50 -060038 Targeting targets;
39 const auto& master = *(targets.begin());
Matt Spinlerf716f322017-02-28 09:37:38 -060040
Matt Spinler6419b632017-02-28 10:10:50 -060041 log<level::INFO>("Running P9 procedure startHost",
42 entry("NUM_PROCS=%d", targets.size()));
43
Matt Spinler6419b632017-02-28 10:10:50 -060044 //Ensure asynchronous clock mode is set
45 writeReg(master, P9_LL_MODE_REG, 0x00000001);
46
47 //Clock mux select override
48 for (const auto& t : targets)
49 {
50 writeRegWithMask(t, P9_ROOT_CTRL8,
51 0x0000000C, 0x0000000C);
52 }
53
54 //Enable P9 checkstop to be reported to the BMC
55
56 //Setup FSI2PIB to report checkstop
57 writeReg(master, P9_FSI_A_SI1S, 0x20000000);
58
59 //Enable Xstop/ATTN interrupt
60 writeReg(master, P9_FSI2PIB_TRUE_MASK, 0x60000000);
61
62 //Arm it
63 writeReg(master, P9_FSI2PIB_INTERRUPT, 0xFFFFFFFF);
64
65 //Kick off the SBE to start the boot
66
67 //First ensure ISTEP stepping isn't enabled
68 writeReg(master, P9_SCRATCH_REGISTER_8, 0x20000000);
69
70 //Start the SBE
71 writeRegWithMask(master, P9_CBS_CS, 0x80000000, 0x80000000);
Matt Spinlerf716f322017-02-28 09:37:38 -060072}
73
74
Matt Spinlerf716f322017-02-28 09:37:38 -060075}
76}
Matt Spinler83e37322017-03-09 11:23:17 -060077