x86-power-control: srcrev bump fc1ecc5910..35aa665e01
Jason M. Bills (1):
Handle unexpected power-on during power cycle flow
(From meta-intel rev: 95ca72c5c8073935ea0af9fa64e36de3171bbfd2)
Change-Id: I3d3925f939be8a590eb3463ba42615bb886b243d
Signed-off-by: Andrew Geissler <openbmcbump-github@yahoo.com>
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
diff --git a/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb b/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb
index 7dd149e..83a0e53 100755
--- a/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb
+++ b/meta-intel/meta-common/recipes-intel/chassis/x86-power-control_git.bb
@@ -2,7 +2,7 @@
DESCRIPTION = "Chassis Power Control service for Intel based platforms"
SRC_URI = "git://github.com/openbmc/x86-power-control.git;protocol=ssh"
-SRCREV = "fc1ecc59100d21c953501703bc5db9e02e25b333"
+SRCREV = "35aa665e01cf9d735ba4aeb3818a60caab376692"
PV = "1.0+git${SRCPV}"