power-sequencer: make pgood timeout configurable
The IBM system1 utilizes a FPGA to power on and off the chassis. This
FPGA can take up to 10 seconds to power on and on occasion it hits the
default 10s timeout, causing an error log to be logged.
Make the pgood timeout configurable so systems can override the timeout
if needed.
Tested:
- Confirmed by default config.h had 10 for the PGOOD_TIMEOUT
- Confirmed when overrode to 30 in a bbappend that it changed to 30
within the config.h
Change-Id: I31ef65ee9f331c4690d68789e435241539804221
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>
diff --git a/meson.build b/meson.build
index afaae3f..d11437a 100644
--- a/meson.build
+++ b/meson.build
@@ -155,6 +155,7 @@
conf.set('SEQUENCER', sequencer_class)
conf.set10('DEVICE_ACCESS', get_option('device-access'))
conf.set10('IBM_VPD', get_option('ibm-vpd'))
+conf.set('PGOOD_TIMEOUT', get_option('pgood-timeout-value'))
configure_file(output: 'config.h', configuration: conf)