tree 537492c10219f8739eaac110d2da0f7e61b1d524
parent 71172458ba5c9f78c5a1a206f4533c806081ed12
author Andrew Geissler <geissonator@yahoo.com> 1743607539 -0500
committer Shawn McCarney <shawnmm@us.ibm.com> 1743774608 +0000

power-sequencer: make pgood timeout configurable

The IBM system1 utilizes a FPGA to power on and off the chassis. This
FPGA can take up to 10 seconds to power on and on occasion it hits the
default 10s timeout, causing an error log to be logged.

Make the pgood timeout configurable so systems can override the timeout
if needed.

Tested:
- Confirmed by default config.h had 10 for the PGOOD_TIMEOUT
- Confirmed when overrode to 30 in a bbappend that it changed to 30
  within the config.h

Change-Id: I31ef65ee9f331c4690d68789e435241539804221
Signed-off-by: Andrew Geissler <geissonator@yahoo.com>