tree 8803a897ce21c6d80eba304c95a51a2ed09ed354
parent f61f1fe0299eebf8749b6a43a858716f8e8e3ab2
author P Dheeraj Srujan Kumar <p.dheeraj.srujan.kumar@intel.com> 1672347756 -0800
committer P Dheeraj Srujan Kumar <p.dheeraj.srujan.kumar@intel.com> 1675983934 -0800

Revamp HSBP clock enabling code flow

This commit enhances the existing HSBP clock enabling logic
by eliminating most of the hardcoded register addresses, mapping
tables etc. The revamped code pulls all the configuration from the
Dbus object exposed by entity-manager, i.e. all the required hardware
information is moved into a configuration file, thereby reducing
hardcoding of values. This approch also makes it flexible to add
any number/type of clock buffers and also have flexibility in
mapping the drives (i.e. in case the hardware maps the HSBP drives
differently, only a configuratioon change is all that is needed
without having to touch the code).
Below is a template of configuration that needs to be appended
into the baseboard configuration file:
{
	"RootI2cBus": 4,
	"HsbpSupported": [
		"HSBP_1",
		"HSBP_2",
		"HSBP_3"
	],
	"HSBP_1": [
		"CPU0_NVME1",
		"CPU0_NVME2",
		"CPU0_NVME3",
		"CPU0_NVME4",
		"CPU0_NVME5",
		"CPU0_NVME6",
		"CPU0_NVME7",
		"CPU0_NVME8"
	],
	"HSBP_2": [
		"CPU1_NVME1",
		"CPU1_NVME2",
		"CPU1_NVME3",
		"CPU1_NVME4",
		"CPU1_NVME5",
		"CPU1_NVME6",
		"CPU1_NVME7",
		"CPU1_NVME8"
	],
	"HSBP_3": [
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-"
	],
	"ClockBuffer": [
		"abcd"
	],
	"IoExpander": [
		"efgh"
	],
	"Name": "HSBP Config",
	"Type": "HSBPConfiguration"
},
{
	"Address": "0x12",
	"Bus": 4,
	"Mode": "SMBus",
	"OutCtrlBaseAddr": "0x81",
	"OutCtrlByteCount": 2,
	"Byte0": [
		"CPU0_NVME5",
		"CPU0_NVME2",
		"CPU0_NVME8",
		"CPU0_NVME4",
		"CPU0_NVME1",
		"CPU0_NVME6",
		"CPU0_NVME7",
		"CPU0_NVME3"
	],
	"Byte1": [
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-"
	],
	"Name": "CPU0 Clock Buffer",
	"Type": "abcd"
},
{
	"Address": "0x34",
	"Bus": 4,
	"Mode": "IO",
	"OutCtrlBaseAddr": "0x81",
	"OutCtrlByteCount": 2,
	"Byte0": [
		"CPU1_NVME1",
		"CPU1_NVME2",
		"CPU1_NVME3",
		"CPU1_NVME4",
		"CPU1_NVME5",
		"CPU1_NVME6",
		"CPU1_NVME7",
		"CPU1_NVME8"
	],
	"Byte1": [
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-"
	],
	"Name": "CPU1 Clock Buffer",
	"Type": "abcd"
},
{
	"Address": "0x56",
	"Bus": 4,
	"ConfIORegAddr": "0x06",
	"OutCtrlBaseAddr": "0x02",
	"OutCtrlByteCount": 2,
	"IO0": [
		"CPU1_NVME1",
		"CPU1_NVME2",
		"CPU1_NVME3",
		"CPU1_NVME4",
		"CPU1_NVME5",
		"CPU1_NVME6",
		"CPU1_NVME7",
		"CPU1_NVME8"
	],
	"IO1": [
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-",
		"-"
	],
	"Name": "IO Expander",
	"Type": "efgh"
}

TESTED:
 - On BMC boot, the connected HSBP drives were detected and
   respective clock was enabled
 - Hot Swapped couple of drives and confirmed the respective
   clocks being enabled (The clocks were disabled for the Drives
   which were removed)
 - Verified by i2cdump of clock buffer(s) and checking respective
   registers

Change-Id: Ice2b3b4f9d16df6d572ab34c8ea0cfddf657554c
Signed-off-by: P Dheeraj Srujan Kumar <p.dheeraj.srujan.kumar@intel.com>