lots of changes
diff --git a/objects/control_bmc_obj.c b/objects/control_bmc_obj.c
index 7e9965f..9ceaf9b 100644
--- a/objects/control_bmc_obj.c
+++ b/objects/control_bmc_obj.c
@@ -14,46 +14,94 @@
static const gchar* dbus_object_path = "/org/openbmc/control";
static const gchar* dbus_name = "org.openbmc.control.Bmc";
+//this probably should come from some global SOC config
+
+#define LPC_BASE 0x1e789000
+#define LPC_HICR6 0x80
+#define LPC_HICR7 0x88
+#define LPC_HICR8 0x8c
+
+#define SPI_BASE 0x1e630000
+#define SCU_BASE 0x1e780000
+#define UART_BASE 0x1e783000
+#define COM_BASE 0x1e789000
+#define GPIO_BASE 0x1e6e2000
static GDBusObjectManagerServer *manager = NULL;
+void* memmap(int mem_fd,uint32_t* base)
+{
+ void* bmcreg;
+ bmcreg = mmap(NULL, getpagesize(),
+ PROT_READ | PROT_WRITE, MAP_SHARED, mem_fd, base);
+
+ if (bmcreg == MAP_FAILED) {
+ perror("Unable to map LPC register memory");
+ exit(1);
+ }
+ return bmcreg;
+}
+
+void reg_init()
+{
+ g_print("BMC init\n");
+ // BMC init done here
+
+ void *bmcreg;
+ int mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
+ if (mem_fd < 0) {
+ perror("Unable to open /dev/mem");
+ exit(1);
+ }
+
+ bmcreg = memmap(mem_fd,LPC_BASE);
+ devmem(bmcreg+LPC_HICR6,0x00000500); //Enable LPC FWH cycles, Enable LPC to AHB bridge
+ devmem(bmcreg+LPC_HICR7,0x30000E00); //32M PNOR
+ devmem(bmcreg+LPC_HICR8,0xFE0001FF);
+
+ //flash controller
+ bmcreg = memmap(mem_fd,SPI_BASE);
+ devmem(bmcreg+0x00,0x00000003);
+ devmem(bmcreg+0x04,0x00002404);
+
+ //UART
+
+
+ bmcreg = memmap(mem_fd,UART_BASE);
+ devmem(bmcreg+0x00,0x00000000); //Set Baud rate divisor -> 13 (Baud 115200)
+ devmem(bmcreg+0x04,0x00000000); //Set Baud rate divisor -> 13 (Baud 115200)
+ devmem(bmcreg+0x08,0x000000c1); //Disable Parity, 1 stop bit, 8 bits
+ bmcreg = memmap(mem_fd,COM_BASE);
+ devmem(bmcreg+0x9C,0x00000000); //Set routing UART1 -> COM 1
+
+ bmcreg = memmap(mem_fd,SCU_BASE);
+ devmem(bmcreg+0x00,0x13008CE7);
+ devmem(bmcreg+0x04,0x0370E677);
+ devmem(bmcreg+0x20,0xDF48F7FF);
+ devmem(bmcreg+0x24,0xC738F202);
+
+
+ //GPIO
+ bmcreg = memmap(mem_fd,GPIO_BASE);
+ devmem(bmcreg+0x84,0x00fff0c0); //Enable UART1
+ devmem(bmcreg+0x70,0x120CE406);
+ devmem(bmcreg+0x80,0xCB000000);
+ devmem(bmcreg+0x88,0x01C000FF);
+ devmem(bmcreg+0x8c,0xC1C000FF);
+ devmem(bmcreg+0x90,0x003FA009);
+
+
+ close(mem_fd);
+}
+
static gboolean
on_init (Control *control,
GDBusMethodInvocation *invocation,
gpointer user_data)
{
- g_print("BMC init\n");
- // BMC init done here
- /*
- devmem(0x1e789080,0x00000500); //Enable LPC FWH cycles, Enable LPC to AHB bridge
- devmem(0x1e789088,0x30000E00); //32M PNOR
- devmem(0x1e78908C,0xFE0001FF);
-
- //flash controller
- devmem(0x1e630000,0x00000003);
- devmem(0x1e630004,0x00002404);
-
- //UART
- devmem(0x1e6e2084,0x00fff0c0); //Enable UART1
- devmem(0x1e783000,0x00000000); //Set Baud rate divisor -> 13 (Baud 115200)
- devmem(0x1e783004,0x00000000); //Set Baud rate divisor -> 13 (Baud 115200)
- devmem(0x1e783008,0x000000c1); //Disable Parity, 1 stop bit, 8 bits
- devmem(0x1E78909C,0x00000000); //Set routing UART1 -> COM 1
-
-
- //GPIO
- devmem(0x1e6e2070,0x120CE406);
- devmem(0x1e6e2080,0xCB000000);
- devmem(0x1e6e2088,0x01C000FF);
- devmem(0x1e6e208c,0xC1C000FF);
- devmem(0x1e6e2090,0x003FA009);
-
- devmem(0x1E780000,0x13008CE7);
- devmem(0x1E780004,0x0370E677);
- devmem(0x1E780020,0xDF48F7FF);
- devmem(0x1E780024,0xC738F202);
-*/
-
+ #ifdef __arm__
+ reg_init();
+ #endif
control_complete_init(control,invocation);
control_emit_goto_system_state(control,"STANDBY");
@@ -106,7 +154,6 @@
}
/* Export all objects */
g_dbus_object_manager_server_set_connection (manager, connection);
-
}
static void