Refactor SST host processor interface
In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.
This is a pure refactor with no functional change.
Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.
Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 6d0cfea..f7b4fd5 100755
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -67,6 +67,7 @@
if (CPU_INFO)
add_executable (cpuinfoapp src/cpuinfo_main.cpp src/speed_select.cpp
+ src/sst_mailbox.cpp
src/cpuinfo_utils.cpp)
target_link_libraries (cpuinfoapp ${SYSTEMD_LIBRARIES})
target_link_libraries (cpuinfoapp ${DBUSINTERFACE_LIBRARIES})