Refactor SST host processor interface
In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.
This is a pure refactor with no functional change.
Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.
Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
diff --git a/include/cpuinfo_utils.hpp b/include/cpuinfo_utils.hpp
index ab2ea92..926c2d1 100644
--- a/include/cpuinfo_utils.hpp
+++ b/include/cpuinfo_utils.hpp
@@ -47,4 +47,43 @@
*/
void hostStateSetup(const std::shared_ptr<sdbusplus::asio::connection>& conn);
+constexpr uint64_t bit(uint8_t index)
+{
+ return (1ull << index);
+}
+
+/**
+ * Extract a bitfield from an input data by shifting and masking.
+ *
+ * @tparam Dest Destination type - mostly useful to avoid an extra static_cast
+ * at the call site. Defaults to the Src type if unspecified.
+ * @tparam Src Automatically deduced from the first positional parameter.
+ *
+ * @param data Input data.
+ * @param loBit 0-based index of the least significant bit to return.
+ * @param hiBit 0-based index of the most significant bit to return.
+ */
+template <typename Dest = std::monostate, typename Src>
+auto mask(Src data, unsigned int loBit, unsigned int hiBit)
+{
+ assert(hiBit >= loBit);
+ uint64_t d = data;
+ d >>= loBit;
+ d &= (1ull << (hiBit - loBit + 1)) - 1;
+ if constexpr (std::is_same_v<Dest, std::monostate>)
+ {
+ return static_cast<Src>(d);
+ }
+ else
+ {
+ return static_cast<Dest>(d);
+ }
+}
+
+namespace dbus
+{
+boost::asio::io_context& getIOContext();
+std::shared_ptr<sdbusplus::asio::connection> getConnection();
+} // namespace dbus
+
} // namespace cpu_info