Refactor SST host processor interface
In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.
This is a pure refactor with no functional change.
Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.
Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
diff --git a/src/cpuinfo_main.cpp b/src/cpuinfo_main.cpp
index c9dd3e5..1d91f17 100644
--- a/src/cpuinfo_main.cpp
+++ b/src/cpuinfo_main.cpp
@@ -636,9 +636,9 @@
int main(int argc, char* argv[])
{
// setup connection to dbus
- boost::asio::io_service io;
+ boost::asio::io_service& io = cpu_info::dbus::getIOContext();
std::shared_ptr<sdbusplus::asio::connection> conn =
- std::make_shared<sdbusplus::asio::connection>(io);
+ cpu_info::dbus::getConnection();
// CPUInfo Object
conn->request_name(cpu_info::cpuInfoObject);