Refactor SST host processor interface
In order to support future host processors that use a different
interface to SST, separate the SST logic into 1) high-level discovery
logic + D-Bus interfaces, and 2) low-level backend processor interface.
This is a pure refactor with no functional change.
Tested:
Ran sst-compare-redfish-os.py tool on platform with SPR host CPU, and
verified no mismatches reported.
Used sst-info.sh to change configs and verify new config was reflected
in Redfish.
Change-Id: I6825eb7541cbe2214844e7b64d462f2688dedcec
Signed-off-by: Jonathan Doman <jonathan.doman@intel.com>
diff --git a/src/cpuinfo_utils.cpp b/src/cpuinfo_utils.cpp
index e30a275..1c69e6a 100644
--- a/src/cpuinfo_utils.cpp
+++ b/src/cpuinfo_utils.cpp
@@ -288,4 +288,18 @@
initialized = true;
}
+namespace dbus
+{
+boost::asio::io_context& getIOContext()
+{
+ static boost::asio::io_context ioc;
+ return ioc;
+}
+std::shared_ptr<sdbusplus::asio::connection> getConnection()
+{
+ static auto conn =
+ std::make_shared<sdbusplus::asio::connection>(getIOContext());
+ return conn;
+}
+} // namespace dbus
} // namespace cpu_info