| commit | 8f789c3ac4fa47e02bc4862c50390dbf043be80c | [log] [tgz] |
|---|---|---|
| author | Tony Lee <tony.lee@quantatw.com> | Wed Jul 10 20:01:43 2024 +0800 |
| committer | Zhikui Ren <zhikui.ren@intel.com> | Thu Dec 05 17:52:05 2024 +0000 |
| tree | 2a4cc09461565ca327364156c23f2b9b80def4d9 | |
| parent | 8049822c9e3313583e31c18ba36c7b5ddc31fbe3 [diff] |
Enable MemoryLocation properties to be customized
-Enable MemoryLocation properties to be customized by a json table.
Example of memoryLocationTable.json:
{
"<MemoryDeviceLocator>": {
"MemoryController": 1,
"Socket":48,
"Slot":0,
"Channel":0
}
}
-Add attribute "memoryController", "slot", "channel", "socket" in
MemoryLocation.
Tested:
memoryLocationTable.json:
{
"DIMM4": {
"MemoryController": 1,
"Socket":48,
"Slot":0,
"Channel":0
}
}
with the change:
curl -k -X GET http://${bmc}/redfish/v1/Systems/system/Memory/dimm1
{
"@odata.id": "/redfish/v1/Systems/system/Memory/dimm1",
"@odata.type": "#Memory.v1_11_0.Memory",
"AllowedSpeedsMHz": [],
"BaseModuleType": "RDIMM",
"BusWidthBits": 80,
"CapacityMiB": 49152,
"DataWidthBits": 64,
"ErrorCorrection": "SingleBitECC",
"FirmwareRevision": "0",
"Id": "dimm1",
"Location": {
"PartLocation": {
"LocationType": "Slot",
"ServiceLabel": "DIMM4"
}
},
"Manufacturer": "",
"MemoryDeviceType": "DDR5",
"MemoryLocation": {
"Channel": 0,
"MemoryController": 1,
"Slot": 0,
"Socket": 48
}
without the change:
curl -k -X GET http://${bmc}/redfish/v1/Systems/system/Memory/dimm1
{
"@odata.id": "/redfish/v1/Systems/system/Memory/dimm1",
"@odata.type": "#Memory.v1_11_0.Memory",
"AllowedSpeedsMHz": [],
"BaseModuleType": "RDIMM",
"BusWidthBits": 80,
"CapacityMiB": 49152,
"DataWidthBits": 64,
"ErrorCorrection": "SingleBitECC",
"FirmwareRevision": "0",
"Id": "dimm1",
"Location": {
"PartLocation": {
"LocationType": "Slot",
"ServiceLabel": "DIMM4"
}
},
"Manufacturer": "",
"MemoryDeviceType": "DDR5",
"MemoryLocation": {
"Channel": 0,
"MemoryController": 0,
"Slot": 0,
"Socket": 0
}
Change-Id: Ic5ff09715a619907f06d06af33aa0d1755c8b4f3
Signed-off-by: Tony Lee <tony.lee@quantatw.com>
The main application in this repo is smbiosmdrv2app, capable of parsing a binary SMBIOS table and publishing the system information on D-Bus, to be consumed by other OpenBMC applications.
The SMBIOS table is usually sent to the BMC by the host firmware (BIOS). The system designer can theoretically choose any transport and mechanism for sending the SMBIOS data, but there are at least two implementation today:
The primary API is a set of Intel OEM IPMI commands called Managed Data Region version 2 (MDRv2), which provides a means for host firmware to send data through the VGA shared memory region. MDRv2 has a concept of multiple agents, each maintaining a "directory" containing directory entries (aka data sets). The host can query for the existence and version of directories to determine when it needs to send an updated SMBIOS table.
intel-ipmi-oem implements the IPMI command handlers, routing commands and data to the correct agent (e.g. smbios-mdr). The D-Bus interface between the IPMI handler and smbios-mdr is largely a mirror of IPMI commands.
phosphor-ipmi-blobs is an alternative implementation of a generic IPMI blob transfer API. Compared to MDRv2, it is simpler and easier to use, but also transfers the data in-band with the IPMI commands and therefore slower than using a shared memory region (which may or may not be a concern).
phosphor-ipmi-blobs provides a blob manager shared library for ipmid which implements the IPMI commands. In turn, it loads blob handler libraries that each implement support for specific blobs. Here in smbios-mdr we provide such a blob handler for the /smbios blob. It works by writing the data into /var/lib/smbios/smbios2 (the local persistent cache for the SMBIOS table) and calling the AgentSynchronizeData D-Bus method to trigger smbios-mdr to reload and parse the table from that file.
cpuinfoapp is an Intel-specific application that uses I2C and PECI to gather more details about Xeon CPUs that aren't included in the SMBIOS table for some reason. It also implements discovery and control for Intel Speed Select Technology (SST).