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gerrit.openbmc.org / openbmc / x86-power-control / 41a49aa647a3c7458b2c9c5fe90ca26ec79e2b4e
commit41a49aa647a3c7458b2c9c5fe90ca26ec79e2b4e[log] [tgz]
authorJason M. Bills <jason.m.bills@linux.intel.com>Wed Mar 03 16:03:25 2021 -0800
committerJason M. Bills <jason.m.bills@linux.intel.com>Mon Mar 08 12:29:03 2021 -0800
treee33f58136cc404cefd075450515fff580b98d1b1
parentfb957331e6a162047be6b75695ea8c1fc174cf63 [diff]
Use phosphor::logging instead of std::cerr

After moving part of the logs to phosphor::logging, it caused
the messages to get logged out of order depending on if they
came from phosphor::logging or std::cerr.

This change moves all logs to phosphor::logging so they all
appear in the correct order again.

Also fixed a minor typo.

Tested:
Performed a power cycle and confirmed that the logs all look
as expected.

Change-Id: I25f677097d2f6552e09536c3078bb08e1d985986
Signed-off-by: Jason M. Bills <jason.m.bills@linux.intel.com>
1 file changed
tree: e33f58136cc404cefd075450515fff580b98d1b1
  1. cmake/
  2. i2c/
  3. power-control-x86/
  4. .clang-format
  5. CMakeLists.txt
  6. LICENSE
  7. MAINTAINERS
  8. README.md
README.md

X86 power control

This repository contains an OpenBMC compliant implementation of power control for x86 servers. It relies on a number of features to do its job. It has several intentional design goals.

  1. The BMC should maintain the Host state machine internally, and be able to track state changes.
  2. The implementation should either give the requested power control result, or should log an error on the failure it detected.
  3. The BMC should support all the common operations, hard power on/off/cycle, soft power on/off/cycle.

At this point in time, this daemon targets Lewisburg based, dual socket x86 server platforms, such as S2600WFT. It is likely that other platforms will work as well.

Because this relies on the hardware passthrough support in the AST2500 to function, it requires a few patches to work correctly.

This patch adds support to UBOOT to keep the passthrough enabled https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-common/ recipes-bsp/u-boot/files/0005-enable-passthrough-in-uboot.patch

The DTS file for your platform will need the following GPIO definitions RESET_BUTTON RESET_OUT POWER_BUTTON POWER_OUT

On an aspeed, these are generally connected to E0, E1, E2, and E3 respectively. An example of this is available in the s2600WF config.

This patch allows the passthrough to be reenabled to the default condition when the appropriate pin is released. This allows power control to take control when needed by a user power action, but leave the hardware in control a majority of the time, reducing the possibility of bricking a system due to a failed BMC.

https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0002-Enable-pass-through-on-GPIOE1-and-GPIOE3-free.patch https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0003-Enable-GPIOE0-and-GPIOE2-pass-through-by-default.patch https://github.com/Intel-BMC/openbmc/blob/intel/meta-openbmc-mods/meta-ast2500/recipes-kernel/linux/linux-aspeed/0006-Allow-monitoring-of-power-control-input-GPIOs.patch

Caveats: This implementation does not currently implement the common targets that other implementations do. There were several attempts to, but all ended in timing issues and boot inconsistencies during stress operations.

Build Options

USE_PLT_RST

The POST Complete GPIO is usually held asserted by BIOS after POST complete and de-asserts on reset. This de-assert behavior is currently used to detect warm resets.

Some systems are adding support for a PLT_RST eSPI signal that can be used to more accurately detect warm resets. When this option is enabled, x86-power-control will use PLT_RST to detect warm resets instead of POST Complete.