commit | 439b9c3a0835b40bc052c272e53fa250de3212da | [log] [tgz] |
---|---|---|
author | Patrick Williams <patrick@stwcx.xyz> | Fri Jul 22 19:26:53 2022 -0500 |
committer | Patrick Williams <patrick@stwcx.xyz> | Fri Jul 22 19:26:53 2022 -0500 |
tree | 83eadcbabaa31798288cb533e58d18c7626e2b53 | |
parent | 787975ca2aaee5649912921ee772925842f2bfd0 [diff] |
sdbusplus: use shorter type aliases The sdbusplus headers provide shortened aliases for many types. Switch to using them to provide better code clarity and shorter lines. Possible replacements are for: * bus_t * exception_t * manager_t * match_t * message_t * object_t * slot_t Signed-off-by: Patrick Williams <patrick@stwcx.xyz> Change-Id: I73186ee02f4d3c85736516fa0bc036c76262e16e
This repository contains an OpenBMC compliant implementation of power control for x86 servers. It relies on a number of features to do its job. It has several intentional design goals.
This daemon has been successfully used on a variety of server platforms; it should be able to support platforms with power control GPIOs similar to those in its config file.
x86-power-control uses default json file (power-config-host0.json) for GPIO configuration. However this can be customized by producing your own power-config-host0.json file.
Definitions can be configured by two type:
For the platform having direct GPIO access can use the type GPIO and define like below.
{ "Name" : "PostComplete", "LineName" : "POST_COMPLETE", "Type" : "GPIO" },
For the platform not having direct GPIO access can use dbus based event monitor by using the type DBUS.
{ "Name" : "PowerButton", "DbusName" : "xyz.openbmc_project.Chassis.Event", "Path" : "/xyz/openbmc_project/Chassis/Event", "Interface" : "xyz.openbmc_project.Chassis.Event", "Property" : "PowerButton_Host1", "Type" : "DBUS" },
x86-power-control will monitor the property change from the given DbusName and take appropriate action. *define Property as a bool variable.
Caveats: This implementation does not currently implement the common targets that other implementations do. There were several attempts to, but all ended in timing issues and boot inconsistencies during stress operations.
Enable chassis system power reset to allow removing power and restoring back.
The POST Complete GPIO is usually held asserted by BIOS after POST complete and de-asserts on reset. This de-assert behavior is currently used to detect warm resets.
Some systems are adding support for a PLT_RST eSPI signal that can be used to more accurately detect warm resets. When this option is enabled, x86-power-control will use PLT_RST to detect warm resets instead of POST Complete.
See https://github.com/Intel-BMC/host-misc-comm-manager for implementation example.