commit | 48aa1f05d51c2f2cc86e9592a3569e022f9171c8 | [log] [tgz] |
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author | Patrick Williams <patrick@stwcx.xyz> | Wed May 10 07:50:30 2023 -0500 |
committer | Patrick Williams <patrick@stwcx.xyz> | Wed May 10 07:50:30 2023 -0500 |
tree | 5be61209f2d1be8b1fc23f2284ff3b937a6c0d83 | |
parent | f56ef594d779e5992584b9fd7e83c5643b73a456 [diff] |
clang-format: copy latest and re-format clang-format-16 has some backwards incompatible changes that require additional settings for best compatibility and re-running the formatter. Copy the latest .clang-format from the docs repository and reformat the repository. Change-Id: I844971bd190187ba9ef2e8cf16809e2d16317ec4 Signed-off-by: Patrick Williams <patrick@stwcx.xyz>
This repository contains an OpenBMC compliant implementation of power control for x86 servers. It relies on a number of features to do its job. It has several intentional design goals.
This daemon has been successfully used on a variety of server platforms; it should be able to support platforms with power control GPIOs similar to those in its config file.
x86-power-control uses default json file (power-config-host0.json) for GPIO configuration. However this can be customized by producing your own power-config-host0.json file.
Definitions can be configured by two type: GPIO and DBUS
For the platform having direct GPIO access can use the type GPIO and define like below.
{ "Name": "PostComplete", "LineName": "POST_COMPLETE", "Type": "GPIO" }
For the platform not having direct GPIO access can use dbus based event monitor by using the type DBUS.
{ "Name": "PowerButton", "DbusName": "xyz.openbmc_project.Chassis.Event", "Path": "/xyz/openbmc_project/Chassis/Event", "Interface": "xyz.openbmc_project.Chassis.Event", "Property": "PowerButton_Host1", "Type": "DBUS" }
x86-power-control will monitor the property change from the given DbusName and take appropriate action. *define Property as a bool variable.
Caveats: This implementation does not currently implement the common targets that other implementations do. There were several attempts to, but all ended in timing issues and boot inconsistencies during stress operations.
Enable chassis system power reset to allow removing power and restoring back.
The POST Complete GPIO is usually held asserted by BIOS after POST complete and de-asserts on reset. This de-assert behavior is currently used to detect warm resets.
Some systems are adding support for a PLT_RST eSPI signal that can be used to more accurately detect warm resets. When this option is enabled, x86-power-control will use PLT_RST to detect warm resets instead of POST Complete.
See https://github.com/Intel-BMC/host-misc-comm-manager for implementation example.