| commit | 74eb00d3fac8a193288eaabf2b05fe7938139ab1 | [log] [tgz] |
|---|---|---|
| author | Marc Olberding <molberding@nvidia.com> | Wed Nov 12 17:29:19 2025 -0800 |
| committer | Marc Olberding <molberding@nvidia.com> | Mon Nov 17 14:26:20 2025 -0800 |
| tree | 03e1640dc55fbac0b44be22ec85a51b638ec2ba2 | |
| parent | 4ad47bff770dd6c4d6a872f189b4fd794c9f1f1c [diff] |
Fix null access on configs with no post complete Fix null access to unitinialized dbus APIs when we don't provide post complete Tested: loaded on nvl32-obmc and AC cycled, no dump Change-Id: Icf88697a7d3a7a1482f15b665521ed07215aba5e Signed-off-by: Marc Olberding <molberding@nvidia.com>
This repository contains an OpenBMC compliant implementation of power control for x86 servers. It relies on a number of features to do its job. It has several intentional design goals.
This daemon has been successfully used on a variety of server platforms; it should be able to support platforms with power control GPIOs similar to those in its config file.
x86-power-control uses default json file (power-config-host0.json) for GPIO configuration. However this can be customized by producing your own power-config-host0.json file.
Definitions can be configured by two type: GPIO and DBUS
For the platform having direct GPIO access can use the type GPIO and define like below.
{ "Name": "PostComplete", "LineName": "POST_COMPLETE", "Type": "GPIO" }
For the platform not having direct GPIO access can use dbus based event monitor by using the type DBUS.
{ "Name": "PowerButton", "DbusName": "xyz.openbmc_project.Chassis.Event", "Path": "/xyz/openbmc_project/Chassis/Event", "Interface": "xyz.openbmc_project.Chassis.Event", "Property": "PowerButton_Host1", "Type": "DBUS" }
x86-power-control will monitor the property change from the given DbusName and take appropriate action. *define Property as a bool variable.
Caveats: This implementation does not currently implement the common targets that other implementations do. There were several attempts to, but all ended in timing issues and boot inconsistencies during stress operations.
Enable chassis system power reset to allow removing power and restoring back.
The POST Complete GPIO is usually held asserted by BIOS after POST complete and de-asserts on reset. This de-assert behavior is currently used to detect warm resets.
Some systems are adding support for a PLT_RST eSPI signal that can be used to more accurately detect warm resets. When this option is enabled, x86-power-control will use PLT_RST to detect warm resets instead of POST Complete.
See https://github.com/Intel-BMC/host-misc-comm-manager for implementation example.