Palmetto Live VPD
diff --git a/openpower/package/hostboot/hostboot-0001-Disable-centaur-memory-throttle.patch b/openpower/package/hostboot/hostboot-0001-Disable-centaur-memory-throttle.patch
new file mode 100644
index 0000000..06eb3f1
--- /dev/null
+++ b/openpower/package/hostboot/hostboot-0001-Disable-centaur-memory-throttle.patch
@@ -0,0 +1,95 @@
+From 79836dad6267a420ccdd5d3a050ea012227cc9e3 Mon Sep 17 00:00:00 2001
+From: Dean Sanner <dsanner@us.ibm.com>
+Date: Thu, 30 Oct 2014 10:39:12 -0500
+Subject: [PATCH] Disable centaur memory throttle
+
+Change-Id: I86098af366a60b8132f802d8304f1ef883cff542
+---
+ .../mss_thermal_init/mss_thermal_init.C | 3 +-
+ src/usr/hwpf/hwp/initfiles/mba_def.initfile | 49 ----------------------
+ 2 files changed, 2 insertions(+), 50 deletions(-)
+
+diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+index c295d0f..c607f9b 100644
+--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
++++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+@@ -586,7 +586,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
+
+ // Write the IPL Safe Mode Throttles
+ // For centaur DD2 and above since OCC only writes runtime throttles for this
+-
++#if 0
+ uint8_t l_enable_safemode_throttle = 0;
+ l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE, &i_target, l_enable_safemode_throttle);
+ if (l_rc) return l_rc;
+@@ -618,6 +618,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
+ if (l_rc) return l_rc;
+ }
+ }
++#endif
+
+ FAPI_INF("*** %s COMPLETE ***", procedure_name);
+ return l_rc;
+diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+index 4a66dca..2dad4f4 100644
+--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
++++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+@@ -1516,55 +1516,6 @@ scom 0x0301040E {
+ #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT
+ #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT
+
+-
+-
+-scom 0x03010416 {
+- bits , scom_data , ATTR_FUNCTIONAL, expr;
+- 0:14 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA , 1 , any; # cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
+- 15:30 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP , 1 , any; # cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
+- 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR
+- 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight
+- 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight
+- 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
+- 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
+- 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
+- 52 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
+- 53 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1); # cfg_nm_change_after_sync
+-}
+-
+-
+-#Register Name N/M Throttling Control
+-#Mnemonic MBA_FARB4Q
+-#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use
+-#Description N/M throttling control (Centaur only)
+-#MBA_FARB4Q(0:1) cfg_rhmr_en 01 Track only (only FIRs will go off, signaling when a block would have occurred)
+-#MBA_FARB4Q(2) cfg_rhmr_secondary_en 0 Secondary Structure disabled (this is for repair sequence)
+-#MBA_FARB4Q(3) cfg_rhmr_hash_swizzle_en 0 Disable swizzling hash (so we don't switch which rows correspond to which counters)
+-#MBA_FARB4Q(4:9) Reserved 000000 Don't Care
+-#MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight)
+-#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks*
+-#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group
+-#MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care
+-#MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode
+-# -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
+-# -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLE_DENOMINATOR
+-#*I think this corresponds to protecting a row from being hammered 64K times.
+-
+-scom 0x03010417 {
+- bits , scom_data , ATTR_FUNCTIONAL, expr;
+- 0:1 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 2 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
+- 27:41 , SYS.ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
+- 42:55 , SYS.ATTR_MRW_MEM_THROTTLE_DENOMINATOR , 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
+-}
+-
+-
+ # ATTR_EFF_DIMM_TYPE
+ # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
+
+--
+1.9.1
+