diff --git a/openpower/configs/hostboot/mihawk.config b/openpower/configs/hostboot/mihawk.config
new file mode 100755
index 0000000..4f257c4
--- /dev/null
+++ b/openpower/configs/hostboot/mihawk.config
@@ -0,0 +1,73 @@
+# The BMC MBOX Protocol is used to access PNOR
+unset SFC_IS_AST2500
+unset SFC_IS_AST2400
+set   PNORDD_IS_BMCMBOX
+unset PNORDD_IS_SFC
+unset BMC_DOES_SFC_INIT
+unset SFC_IS_IBM_DPSS
+set   ALLOW_MICRON_PNOR
+set   ALLOW_MACRONIX_PNOR
+
+# VPD options.
+set MVPD_READ_FROM_HW
+set MVPD_WRITE_TO_HW
+set MVPD_READ_FROM_PNOR
+set MVPD_WRITE_TO_PNOR
+set DJVPD_READ_FROM_HW
+unset DJVPD_WRITE_TO_HW
+set DJVPD_READ_FROM_PNOR
+set DJVPD_WRITE_TO_PNOR
+set MEMVPD_READ_FROM_HW
+set MEMVPD_WRITE_TO_HW
+set MEMVPD_READ_FROM_PNOR
+set MEMVPD_WRITE_TO_PNOR
+set PVPD_READ_FROM_HW
+set PVPD_WRITE_TO_HW
+set PVPD_READ_FROM_PNOR
+set PVPD_WRITE_TO_PNOR
+unset CDIMM_FORMAT_FOR_CVPD
+
+# gpio config
+set GPIODD
+unset PALMETTO_VDDR
+
+# Enable Consecutive SBE Updates
+set   SBE_UPDATE_CONSECUTIVE
+unset SBE_UPDATE_INDEPENDENT
+unset SBE_UPDATE_SEQUENTIAL
+unset SBE_UPDATE_SIMULTANEOUS
+unset NO_SBE_UPDATES
+
+unset PCIE_HOTPLUG_CONTROLLER
+
+# turn on console output
+set CONSOLE
+set BMC_AST2500
+
+unset DISABLE_HOSTBOOT_RUNTIME
+
+# Compile in hostboot runtime PRD
+set HBRT_PRD
+
+# Compile in hb rt HTMGT : Load/Start OCC
+set HTMGT
+set START_OCC_DURING_BOOT
+unset CONSOLE_OUTPUT_OCC_COMM
+
+#PNOR flags
+unset PNOR_TWO_SIDE_SUPPORT
+
+set BMC_BT_LPC_IPMI
+
+# Enable IPLtime + Runtime Checktop Analysis
+set ENABLE_CHECKSTOP_ANALYSIS
+set IPLTIME_CHECKSTOP_ANALYSIS
+
+# set for trace debug to console
+unset CONSOLE_OUTPUT_TRACE
+set CONSOLE_OUTPUT_FFDCDISPLAY
+
+
+set SECUREBOOT
+set TPMDD
+set TPM_NUVOTON
diff --git a/openpower/configs/mihawk_defconfig b/openpower/configs/mihawk_defconfig
new file mode 100644
index 0000000..fe797d3
--- /dev/null
+++ b/openpower/configs/mihawk_defconfig
@@ -0,0 +1,72 @@
+BR2_powerpc64le=y
+BR2_powerpc_power8=y
+BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_OP_BUILD_PATH)/patches/mihawk-patches"
+BR2_BINUTILS_EXTRA_CONFIG_OPTIONS="--enable-targets=powerpc64-linux"
+BR2_GCC_VERSION_6_X=y
+BR2_EXTRA_GCC_CONFIG_OPTIONS="--enable-targets=powerpc64-linux --disable-libsanitizer"
+BR2_TOOLCHAIN_BUILDROOT_CXX=y
+BR2_TARGET_GENERIC_HOSTNAME="skiroot"
+BR2_ROOTFS_DEVICE_CREATION_DYNAMIC_EUDEV=y
+BR2_ROOTFS_DEVICE_TABLE="../openpower/device_table.txt"
+BR2_TARGET_GENERIC_GETTY_PORT="hvc0"
+BR2_ENABLE_LOCALE_WHITELIST="C de en es fr it ja ko pt_BR ru zh_CN zh_TW"
+BR2_GENERATE_LOCALE="en_US.UTF-8 de_DE.UTF-8 es_ES.UTF-8 fr_FR.UTF-8 it_IT.UTF-8 ja_JP.UTF-8 ko_KR.UTF-8 pt_BR.UTF-8 ru_RU.UTF-8 zh_CN.UTF-8 zh_TW.UTF-8"
+BR2_SYSTEM_ENABLE_NLS=y
+BR2_ROOTFS_USERS_TABLES="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/users-table"
+BR2_ROOTFS_OVERLAY="../openpower/overlay"
+BR2_ROOTFS_POST_BUILD_SCRIPT="../openpower/scripts/fixup-target-var ../openpower/scripts/firmware-whitelist"
+BR2_LINUX_KERNEL=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION=y
+BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="5.2.1"
+BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_OP_BUILD_PATH)/linux"
+BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
+BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_EXTERNAL_OP_BUILD_PATH)/configs/linux/skiroot_defconfig"
+BR2_LINUX_KERNEL_ZIMAGE_EPAPR=y
+BR2_LINUX_KERNEL_XZ=y
+BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y
+BR2_PACKAGE_BUSYBOX_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL)/configs/busybox.fragment"
+BR2_PACKAGE_BUSYBOX_SHOW_OTHERS=y
+BR2_PACKAGE_LINUX_FIRMWARE=y
+BR2_PACKAGE_LINUX_FIRMWARE_BNX2X=y
+BR2_PACKAGE_LINUX_FIRMWARE_CXGB4_T4=y
+BR2_PACKAGE_CRYPTSETUP=y
+BR2_PACKAGE_IPMITOOL=y
+BR2_PACKAGE_IPMITOOL_USB=y
+BR2_PACKAGE_MDADM=y
+BR2_PACKAGE_NCURSES_WCHAR=y
+BR2_PACKAGE_DROPBEAR=y
+# BR2_PACKAGE_DROPBEAR_SERVER is not set
+BR2_PACKAGE_ETHTOOL=y
+BR2_PACKAGE_LRZSZ=y
+BR2_PACKAGE_NETCAT=y
+BR2_PACKAGE_RSYNC=y
+BR2_PACKAGE_SUDO=y
+BR2_PACKAGE_UTIL_LINUX_AGETTY=y
+BR2_TARGET_ROOTFS_CPIO_XZ=y
+BR2_TARGET_ROOTFS_INITRAMFS=y
+BR2_OPENPOWER_PLATFORM=y
+BR2_OPENPOWER_POWER9=y
+BR2_HOSTBOOT_CONFIG_FILE="mihawk.config"
+BR2_OPENPOWER_MACHINE_XML_GITHUB_PROJECT_VALUE="mihawk-xml"
+BR2_OPENPOWER_MACHINE_XML_VERSION="b9929ba9fd96d78da01bce8a2a157851dce9e5cb"
+BR2_OPENPOWER_MACHINE_XML_FILENAME="mihawk.xml"
+BR2_OPENPOWER_SYSTEM_XML_FILENAME="MIHAWK_hb.system.xml"
+BR2_OPENPOWER_MRW_XML_FILENAME="MIHAWK_hb.mrw.xml"
+BR2_OPENPOWER_BIOS_XML_FILENAME="MIHAWK_bios.xml"
+BR2_OPENPOWER_PNOR_XML_LAYOUT_FILENAME="defaultPnorLayout_64.xml"
+BR2_OPENPOWER_CONFIG_NAME="mihawk"
+BR2_OPENPOWER_PNOR_FILENAME="mihawk.pnor"
+BR2_HOSTBOOT_BINARY_SBE_FILENAME="nimbus_sbe.img.ecc"
+BR2_HOSTBOOT_BINARY_SBEC_FILENAME="centaur_sbec_pad.img.ecc"
+BR2_HOSTBOOT_BINARY_WINK_FILENAME="p9n.ref_image.hdr.bin.ecc"
+BR2_IMA_CATALOG_FILENAME="ima_catalog.bin"
+BR2_OPENPOWER_TARGETING_BIN_FILENAME="MIHAWK_HB.targeting.bin"
+BR2_OPENPOWER_TARGETING_ECC_FILENAME="MIHAWK_HB.targeting.bin.ecc"
+BR2_PACKAGE_PETITBOOT=y
+BR2_PACKAGE_PETITBOOT_MTD=y
+BR2_CAPP_UCODE_BIN_FILENAME="cappucode.bin"
+BR2_PACKAGE_LOADKEYS=y
+BR2_IMA_CATALOG_DTS="POWER9"
+BR2_OPENPOWER_SECUREBOOT_NO_KEY_TRANSITION=y
+BR2_OPENPOWER_SECUREBOOT_SIGN_MODE="development"
+BR2_BUILD_PNOR_SQUASHFS=y
diff --git a/openpower/patches/mihawk-patches/occ/occ-0001-Modify-modify-amec-power-sensor-calculation.patch b/openpower/patches/mihawk-patches/occ/occ-0001-Modify-modify-amec-power-sensor-calculation.patch
new file mode 100644
index 0000000..7f94247
--- /dev/null
+++ b/openpower/patches/mihawk-patches/occ/occ-0001-Modify-modify-amec-power-sensor-calculation.patch
@@ -0,0 +1,45 @@
+From d614a89e71564d8d300e25fb76c5a4553fe35876 Mon Sep 17 00:00:00 2001
+From: joy_chu <joy_chu@wistron.com>
+Date: Mon, 22 Jul 2019 18:57:17 +0800
+Subject: [PATCH] Modify: modify amec power sensor calculation
+
+The offset value will be added to APSS raw value when APSS raw value is not 0.
+
+Signed-off-by: joy_chu <joy_chu@wistron.com>
+---
+ src/occ_405/amec/amec_sensors_power.c | 18 +++++++++++-------
+ 1 file changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
+index 5c0ec54..2612598 100755
+--- a/src/occ_405/amec/amec_sensors_power.c
++++ b/src/occ_405/amec/amec_sensors_power.c
+@@ -173,14 +173,18 @@ uint32_t amec_value_from_apss_adc(uint8_t i_chan)
+         // Read Raw Value in mA (divide masked channel data by 2)
+         l_raw = (G_dcom_slv_inbox_rx.adc[i_chan] & APSS_12BIT_ADC_MASK)/2;
+         // Apply offset and gain
+-        if (l_offset & 0x80000000)
++        // Add offset if Raw Value is not zero
++	if (l_raw != 0)
+         {
+-            // Negative offset
+-            l_raw -= (~l_offset + 1);
+-        }
+-        else
+-        {
+-            l_raw += l_offset;
++            if (l_offset & 0x80000000)
++            {
++                // Negative offset
++                l_raw -= (~l_offset + 1);
++	    }
++	    else
++            {
++                l_raw += l_offset;
++            }
+         }
+         //Check to see if l_raw is negative.  If so, set raw to 0
+         if (l_raw & 0x8000)
+-- 
+2.7.4
+