Merge pull request #124 from brihh/master
sync opbuild with latest hostboot commits.
diff --git a/openpower/package/habanero-xml/habanero-xml-0001-Revert-Merge-pull-request-18-from-open-power-bofferd.patch b/openpower/package/habanero-xml/habanero-xml-0001-Revert-Merge-pull-request-18-from-open-power-bofferd.patch
deleted file mode 100644
index 0a921c5..0000000
--- a/openpower/package/habanero-xml/habanero-xml-0001-Revert-Merge-pull-request-18-from-open-power-bofferd.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From b1eb2395a4bf796603cb34aa5913f43b84c42855 Mon Sep 17 00:00:00 2001
-From: Bill Hoffa <wghoffa@us.ibm.com>
-Date: Tue, 31 Mar 2015 07:56:06 -0500
-Subject: [PATCH] Revert "Merge pull request #18 from
- open-power/bofferdn-hab-loadline"
-
-This reverts commit ddb962894919657517f0d9bca4540a427953f987, reversing
-changes made to a98bf456ff5d9f18dc2af1ffc59d67a302029a76.
-
-Conflicts:
- habanero.xml
----
- habanero.xml | 48 ++++++++++++++++++++++++------------------------
- 1 file changed, 24 insertions(+), 24 deletions(-)
-
-diff --git a/habanero.xml b/habanero.xml
-index 8768f72..1aa85a8 100644
---- a/habanero.xml
-+++ b/habanero.xml
-@@ -4967,6 +4967,30 @@
- <default>1</default>
- </attribute>
- <attribute>
-+ <id>PROC_R_DISTLOSS_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_DISTLOSS_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_LOADLINE_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_LOADLINE_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_VRM_VOFFSET_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_VRM_VOFFSET_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
- <id>PROC_X_BUS_WIDTH</id>
- <default>2</default>
- </attribute>
-@@ -6996,30 +7020,6 @@
- <default>0</default>
- </attribute>
- <attribute>
-- <id>PROC_R_DISTLOSS_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_DISTLOSS_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_LOADLINE_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_LOADLINE_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_VRM_VOFFSET_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_VRM_VOFFSET_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
- <id>PSI_BRIDGE_BASE_ADDR</id>
- <default>0,0x0000000000000000</default>
- </attribute>
---
-1.8.2.2
-
diff --git a/openpower/package/hostboot/hostboot-0002-Disable-centaur-memory-throttle.patch b/openpower/package/hostboot/hostboot-0002-Disable-centaur-memory-throttle.patch
deleted file mode 100644
index 632738c..0000000
--- a/openpower/package/hostboot/hostboot-0002-Disable-centaur-memory-throttle.patch
+++ /dev/null
@@ -1,94 +0,0 @@
-From 79836dad6267a420ccdd5d3a050ea012227cc9e3 Mon Sep 17 00:00:00 2001
-From: Dean Sanner <dsanner@us.ibm.com>
-Date: Thu, 30 Oct 2014 10:39:12 -0500
-Subject: [PATCH] Disable centaur memory throttle
-
-Change-Id: I86098af366a60b8132f802d8304f1ef883cff542
----
- .../mss_thermal_init/mss_thermal_init.C | 3 +-
- src/usr/hwpf/hwp/initfiles/mba_def.initfile | 49 ----------------------
- 2 files changed, 2 insertions(+), 50 deletions(-)
-
-diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-index c295d0f..c607f9b 100644
---- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-+++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-@@ -586,7 +586,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
-
- // Write the IPL Safe Mode Throttles
- // For centaur DD2 and above since OCC only writes runtime throttles for this
--
-+#if 0
- uint8_t l_enable_safemode_throttle = 0;
- l_rc = FAPI_ATTR_GET(ATTR_CENTAUR_EC_ENABLE_SAFEMODE_THROTTLE, &i_target, l_enable_safemode_throttle);
- if (l_rc) return l_rc;
-@@ -618,6 +618,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
- if (l_rc) return l_rc;
- }
- }
-+#endif
-
- FAPI_INF("*** %s COMPLETE ***", procedure_name);
- return l_rc;
-diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-index 4a66dca..2dad4f4 100644
---- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-@@ -1516,55 +1516,6 @@ scom 0x0301040E {
- #cfg_nm_ras_weight, bits 45:47 = ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT
- #cfg_nm_cas_weight, bits 48:50 = ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT
-
--
--
--scom 0x03010416 {
-- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 0:14 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_MBA , 1 , any; # cfg_nm_n_per_mba MSS_MEM_THROTTLE_NUMERATOR_PER_MBA
-- 15:30 , ATTR_MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP , 1 , any; # cfg_nm_n_per_chip MSS_MEM_THROTTLE_NUMERATOR_PER_CHIP
-- 31:44 , ATTR_MSS_MEM_THROTTLE_DENOMINATOR , 1 , any; # cfg_nm_m MSS_MEM_THROTTLE_DENOMINATOR
-- 45:47 , ATTR_MSS_THROTTLE_CONTROL_RAS_WEIGHT , 1 , any; # cfg_nm_ras_weight
-- 48:50 , ATTR_MSS_THROTTLE_CONTROL_CAS_WEIGHT , 1 , any; # cfg_nm_cas_weight
-- 51 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2 ) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
-- 51 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_per_slot_enabled Set to 0 for CDIMM, Set to 1 for everything else
-- 52 , 0b0 , 1 , (ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 1); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
-- 52 , 0b1 , 1 , ((ATTR_EFF_DIMM_TYPE == 1) || ((ATTR_EFF_DIMM_TYPE == 2) && (ATTR_EFF_CUSTOM_DIMM == 0)) || (ATTR_EFF_DIMM_TYPE == 3)); # cfg_nm_count_other_mba_dis Set to 0 for CDIMM, Set to 1 for everything else
-- 53 , 0b1 , 1 , (ATTR_CENTAUR_EC_ENABLE_NM_CHANGE_AFTER_SYNC == 1); # cfg_nm_change_after_sync
--}
--
--
--#Register Name N/M Throttling Control
--#Mnemonic MBA_FARB4Q
--#Attributes PAR:EVEN Bit Field Mnemonic Attribute or Setting to use
--#Description N/M throttling control (Centaur only)
--#MBA_FARB4Q(0:1) cfg_rhmr_en 01 Track only (only FIRs will go off, signaling when a block would have occurred)
--#MBA_FARB4Q(2) cfg_rhmr_secondary_en 0 Secondary Structure disabled (this is for repair sequence)
--#MBA_FARB4Q(3) cfg_rhmr_hash_swizzle_en 0 Disable swizzling hash (so we don't switch which rows correspond to which counters)
--#MBA_FARB4Q(4:9) Reserved 000000 Don't Care
--#MBA_FARB4Q(10:11) cfg_rhmr_decrement_weight 01 Decrement by 1 (minimum weight)
--#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 1111111 Slowest rate of decrements. Once ever 2^14 or 16K DRAM clocks*
--#MBA_FARB4Q(12:18) cfg_rhmr_primary_decr_intv 0000011 decrement every 512 DRAM clocks for 100K accesses to hash group
--#MBA_FARB4Q(19:25) cfg_rhmr_secondary_decr_intv 0000000 Don't care
--#MBA_FARB4Q(26) cfg_rhmr_sim_en 0 Disable sim mode
--# -- bits 27:41 (cfg_emer_n) = ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP
--# -- bits 42:55 (cfg_emer_m) = ATTR_MRW_MEM_THROTTLE_DENOMINATOR
--#*I think this corresponds to protecting a row from being hammered 64K times.
--
--scom 0x03010417 {
-- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 0:1 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 2 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 3 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 4:9 , 0b000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 10:11 , 0b01 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 12:18 , 0b0000011 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 19:25 , 0b0000000 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 26 , 0b0 , 1 , (ATTR_CENTAUR_EC_ENABLE_ROW_HAMMER_FEATURE == 1);
-- 27:41 , SYS.ATTR_MRW_SAFEMODE_MEM_THROTTLE_NUMERATOR_PER_CHIP, 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
-- 42:55 , SYS.ATTR_MRW_MEM_THROTTLE_DENOMINATOR , 1 , (ATTR_CENTAUR_EC_ENABLE_SAFE_MODE_THROTTLE == 1);
--}
--
--
- # ATTR_EFF_DIMM_TYPE
- # CDIMM = 0, RDIMM = 1, UDIMM = 2, LRDIMM = 3
-
---
-1.9.1
\ No newline at end of file
diff --git a/openpower/package/hostboot/hostboot-0017-Do-not-fail-IPL-for-missing-OSYS-SS-data.patch b/openpower/package/hostboot/hostboot-0002-Do-not-fail-IPL-for-missing-OSYS-SS-data.patch
similarity index 100%
rename from openpower/package/hostboot/hostboot-0017-Do-not-fail-IPL-for-missing-OSYS-SS-data.patch
rename to openpower/package/hostboot/hostboot-0002-Do-not-fail-IPL-for-missing-OSYS-SS-data.patch
diff --git a/openpower/package/hostboot/hostboot-0004-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch b/openpower/package/hostboot/hostboot-0004-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch
deleted file mode 100644
index bb5a0ae..0000000
--- a/openpower/package/hostboot/hostboot-0004-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch
+++ /dev/null
@@ -1,544 +0,0 @@
-From 114bf3bb36fffe6c3c9c5894ebaae5772edb35ff Mon Sep 17 00:00:00 2001
-From: Andrew Geissler <andrewg@us.ibm.com>
-Date: Sat, 28 Feb 2015 12:28:05 -0600
-Subject: [PATCH] Revert "SW294127:INITPROC: FSP&Hostboot - fast exit power down"
-
-This reverts commit bffe97031429bd5656930f7453c496ce2594e5e6.
----
- .../mss_draminit_mc/mss_draminit_mc.C | 19 +-
- src/usr/hwpf/hwp/initfiles/mba_def.initfile | 423 +++++---------------
- 2 files changed, 118 insertions(+), 324 deletions(-)
-
-diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
-index 53f3132..350efb7 100644
---- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
-+++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
-@@ -5,7 +5,7 @@
- /* */
- /* OpenPOWER HostBoot Project */
- /* */
--/* Contributors Listed Below - COPYRIGHT 2012,2015 */
-+/* Contributors Listed Below - COPYRIGHT 2012,2014 */
- /* [+] International Business Machines Corp. */
- /* */
- /* */
-@@ -22,7 +22,7 @@
- /* permissions and limitations under the License. */
- /* */
- /* IBM_PROLOG_END_TAG */
--// $Id: mss_draminit_mc.C,v 1.48 2014/12/05 15:37:43 dcadiga Exp $
-+// $Id: mss_draminit_mc.C,v 1.47 2014/09/24 14:48:18 dcadiga Exp $
- //------------------------------------------------------------------------------
- // *! (C) Copyright International Business Machines Corp. 2011
- // *! All Rights Reserved -- Property of IBM
-@@ -46,7 +46,6 @@
- //------------------------------------------------------------------------------
- // Version:| Author: | Date: | Comment:
- //---------|----------|---------|-----------------------------------------------
--// 1.48 | dcadiga |05-DEC-14| Powerdown control at initfile
- // 1.47 | dcadiga |09-SEP-14| Removed SPARE cke disable step
- // 1.46 | gollub |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock)
- // 1.45 | dcadiga |14-FEB-14| Periodic Cal Fix for DD2
-@@ -255,14 +254,12 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target)
-
- // Step Five: Setup Power Management
- FAPI_INF( "+++ Setting Up Power Management +++");
-- FAPI_INF( "+++ POWER MANAGEMENT HANDLED AT INITFILE +++");
-- //Procedure commented out because domain reduction enablement now handled at the initfile
-- //rc = mss_enable_power_management(l_mbaChiplets[i]);
-- //if(rc)
-- //{
-- // FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-- // return rc;
-- //}
-+ rc = mss_enable_power_management(l_mbaChiplets[i]);
-+ if(rc)
-+ {
-+ FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
-+ return rc;
-+ }
-
- }
-
-diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-index 61eba9e..88aafb9 100644
---- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-+++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
-@@ -1,9 +1,9 @@
--#-- $Id: mba_def.initfile,v 1.70 2014/12/05 16:21:33 yctschan Exp $
-+
-+#-- $Id: mba_def.initfile,v 1.69 2014/09/24 14:44:15 asaetow Exp $
- #-- CHANGE HISTORY:
- #--------------------------------------------------------------------------------
- #-- Version:|Author: | Date: | Comment:
- #-- --------|--------|--------|--------------------------------------------------
--#-- 1.70|yctschan|12/05/14| Updated settings for fast exit power down
- #-- 1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround.
- #-- 1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date
- #-- 1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time.
-@@ -144,12 +144,93 @@ define def_equal_test = (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
- # <valueType>uint32</valueType>
- # <enum>DISABLE = 0</enum>
-
-+#<attribute>
-+# <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
-+#Dimensions are [port][dimm] A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
-+#creator: mss_eff_cnfg
-+#consumer: various
-+#firmware notes: none</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+# <array> 2 2</array>
-+# <persistRuntime/>
-+#</attribute>
-+#
-+#<attribute>
-+# <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Specifies the number of master ranks per DIMM.</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+# <array> 2 2</array>
-+#</attribute>
-+#
-+#<attribute>
-+# <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
-+#values are 0,1,2, 4 up to 32
-+#creator: mss_eff_cnfg
-+#consumer: various
-+#firmware notes: none</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+# <array> 2 2</array>
-+# <persistRuntime/>
-+#</attribute>
-+#
-+#<attribute>
-+# <id>ATTR_EFF_DRAM_BANKS</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Number of DRAM banks. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
-+#creator: mss_eff_cnfg
-+#consumer: various
-+#firmware notes: none</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+#</attribute>
-+#
-+#<attribute>
-+# <id>ATTR_EFF_DRAM_ROWS</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Number of DRAM rows. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
-+#creator: mss_eff_cnfg
-+#consumer: various
-+#firmware notes: none</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+#</attribute>
-+#
-+#<attribute>
-+# <id>ATTR_EFF_DRAM_COLS</id>
-+# <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
-+# <description>Number of DRAM columns. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg. Each memory channel will have a value.
-+#creator: mss_eff_cnfg
-+#consumer: various
-+#firmware notes: none</description>
-+# <valueType>uint8</valueType>
-+# <writeable/>
-+# <odmVisable/>
-+# <odmChangeable/>
-+#</attribute
-
-
- # mba tmr0 register timings are added to the value below
- define def_margin1 = (1);
- define def_margin2 = (0);
--define def_margin_pup_fast = (0);
-+define def_margin_pup_fast = (7);
- define def_margin_pup_slow = (0);
- define def_margin_rdtag = (4);
-
-@@ -263,22 +344,6 @@ define def_C3c_C4C_ddr4 = ((def_2b_1socket_ddr4)||(def_2b_
- define def_C4A_ddr4 = ((def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_ddr4_cdimm )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4)||(def_3a_1socket_ddr4)||(def_3a_2socket_ddr4)||(def_4a_ddr4_cdimm));
- define def_IS5D = ((def_5d_1socket )||(def_5d_2socket));
-
--# ODT Mappings
--define def_odt_mapping_1a = (def_1a_1socket);
--define def_odt_mapping_1b1dimm = (def_1b_1socket ||def_3a_1socket ||def_3a_1socket_ddr4 ||def_3b_1socket ||def_3c_1socket_ddr4);
--define def_odt_mapping_1b2dimm = (def_3c_2socket_ddr4 ||def_1b_2socket ||def_3a_2socket ||def_3a_2socket_ddr4 ||def_3b_2socket);
--#define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_1b_cdimm ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm);
--define def_odt_mapping_1bcdimm = (def_1a_2socket ||def_3a_cdimm ||def_3a_ddr4_cdimm ||def_3b_cdimm ||def_3b_ddr4_cdimm ||def_3c_cdimm ||def_3c_ddr4_cdimm);
--define def_odt_mapping_1c2dimm = (def_1c_2socket_odt);
--define def_odt_mapping_1c1dimm = (def_1c_1socket_odt);
--define def_odt_mapping_1ccdimm = (def_1c_cdimm ||def_4a_cdimm ||def_4a_ddr4_cdimm ||def_4b_ddr4_cdimm ||def_4c_ddr4_cdimm);
--define def_odt_mapping_1dx82dimm = (def_1d_2socket);
--define def_odt_mapping_1dx4 = (def_1d_1socket);
--define def_odt_mapping_2abc = (def_2a_1socket ||def_2a_2socket ||def_2a_1socket_ddr4 ||def_2a_2socket_ddr4 ||def_2a_cdimm ||def_2a_ddr4_cdimm ||def_2b_1socket ||def_2b_2socket ||def_2b_1socket_ddr4 ||def_2b_2socket_ddr4 ||def_2b_cdimm ||def_2b_ddr4_cdimm ||def_2c_1socket ||def_2c_2socket ||def_2c_1socket_ddr4 ||def_2c_2socket_ddr4 ||def_2c_ddr4_cdimm);
--define def_odt_mapping_56781lrdm = (def_5b_1socket ||def_5c_1socket ||def_7a_1socket ||def_7a_1socket_ddr4 ||def_7b_1socket ||def_7b_1socket_ddr4 ||def_7c_1socket ||def_7c_1socket_ddr4);
--define def_odt_mapping_56782lrdm = (def_5b_2socket ||def_5c_2socket ||def_7a_2socket ||def_7a_2socket_ddr4 ||def_7b_2socket ||def_7b_2socket_ddr4 ||def_7c_2socket ||def_7c_2socket_ddr4);
--define def_odt_mapping_5d1dimm = (def_5d_1socket);
--define def_odt_mapping_5d2dimm = (def_5d_2socket);
-
-
- #gdial std_size ( MBA_SRQ.mba_tmr1q_cfg_tfaw, MBA_SRQ.pc.MBAREF0Q_cfg_trfc, MBA_SRQ.pc.MBAREF0Q_cfg_refr_tsv_stack, MBA_SRQ.pc.MBARPC0Q_cfg_pup_pdn, MBA_SRQ.pc.MBARPC0Q_cfg_pdn_pup, MBA_SRQ.pc.MBARPC0Q_cfg_pup_avail, MBA_SRQ.mba_tmr0q_RRSMSR_dly , MBA_SRQ.mba_tmr0q_RRSMDR_dly, MBA_SRQ.mba_tmr0q_WWSMSR_dly, MBA_SRQ.mba_tmr0q_WWSMDR_dly , MBA_SRQ.MBA_TMR0Q_Trrd, MBA_SRQ.srqdbg.cfg_std_size_id)=
-@@ -1944,31 +2009,29 @@ scom 0x03010432 {
- #
- scom 0x03010434 {
- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 2 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); # cfg_min_max_domains 36
-- 2 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); # cfg_min_max_domains 36
--# 3:5 , 0b001 , 1 , any; # cfg_min_max_domains 36
-- 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt
-- 6:10 , 0b00011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail - performance enhancemnt
-- 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b01100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b01111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b10011 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b10110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b11001 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-- 6:10 , 0b11100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail 36
-+# 3:5 , 0b010 , 1 , any; # cfg_min_max_domains 36
-+ 6:10 , 0b00100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail - performance enhancemnt
-+ 6:10 , 0b00100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly4 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail - performance enhancemnt
-+ 6:10 , 0b00101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b00101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly5 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b00110 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b00110 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly6 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b00111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b00111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly7 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b01000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b01000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly8 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b01101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b01101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10000 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10000 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10100 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10100 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10111 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b10111 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b11010 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b11010 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b11101 + def_margin_pup_slow , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail 36
-+ 6:10 , 0b11101 + def_margin_pup_fast , 1 , (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail 36
- 11:15 , 0b00011 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup 37
- 11:15 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup 37
- 11:15 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup 37
-@@ -1977,286 +2040,20 @@ scom 0x03010434 {
- 16:20 , 0b00100 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn 38
- 16:20 , 0b00101 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn 38
- 16:20 , 0b00110 , 1 , (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn 38
-- 22 , 0b0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0);
-- 22 , 0b1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0);
-+ 22 , 0b0 , 1 , any; # cfg_min_domain_reduction_enable set to 1 to enable power controls
- 23:32 , 0b0000000011, 1 , any; # Set min doman reduction time to 30.7 us (10.245us * 3)
- 42 , 0b1 , 1 , any; # Force SpareCKE sync
-- 43 , 0b1 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval
-+ 43 , 0b0 , 1 , any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval
- }
-
--# had to shifts the data to be able to get it into the proper positions
--define shift_pwr_map1 = (ATTR_VPD_CKE_PWR_MAP >> 60);
--define shift_pwr_map2 = (ATTR_VPD_CKE_PWR_MAP >> 56);
--define shift_pwr_map3 = (ATTR_VPD_CKE_PWR_MAP >> 52);
--define shift_pwr_map4 = (ATTR_VPD_CKE_PWR_MAP >> 48);
--define shift_pwr_map5 = (ATTR_VPD_CKE_PWR_MAP >> 44);
--define shift_pwr_map6 = (ATTR_VPD_CKE_PWR_MAP >> 40);
--define shift_pwr_map7 = (ATTR_VPD_CKE_PWR_MAP >> 36);
--define shift_pwr_map8 = (ATTR_VPD_CKE_PWR_MAP >> 32);
--define shift_pwr_map9 = (ATTR_VPD_CKE_PWR_MAP >> 28);
--define shift_pwr_map10 = (ATTR_VPD_CKE_PWR_MAP >> 24);
--define shift_pwr_map11 = (ATTR_VPD_CKE_PWR_MAP >> 20);
--define shift_pwr_map12 = (ATTR_VPD_CKE_PWR_MAP >> 16);
--define shift_pwr_map13 = (ATTR_VPD_CKE_PWR_MAP >> 12);
--define shift_pwr_map14 = (ATTR_VPD_CKE_PWR_MAP >> 8);
--define shift_pwr_map15 = (ATTR_VPD_CKE_PWR_MAP >> 4);
--
- # MBAPC1Q power control settings reg 1
- #
- scom 0x03010435 {
- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 0:3 , shift_pwr_map1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_rd_cke 36
-- 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 0:3 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 0:3 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 0:3 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 0:3 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 0:3 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 0:3 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_rd_cke 36
-- 4:7 , shift_pwr_map2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk1_rd_cke 36
-- 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 4:7 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 4:7 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 4:7 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 4:7 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 4:7 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 4:7 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 4:7 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 8:11 , shift_pwr_map3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_rd_cke 36
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 8:11 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 8:11 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 8:11 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 8:11 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 8:11 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 12:15 , shift_pwr_map4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_rd_cke 36
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 12:15 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 12:15 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 12:15 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 12:15 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 12:15 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 16:19 , shift_pwr_map5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_rd_cke 36
-- 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 16:19 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 16:19 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 16:19 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 16:19 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 16:19 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 16:19 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 20:23 , shift_pwr_map6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_rd_cke 36
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 20:23 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 20:23 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 20:23 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 20:23 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 20:23 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 20:23 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 20:23 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
--}
--
--
--scom 0x03010435 {
-- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 24:27 , shift_pwr_map7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_rd_cke 37
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 24:27 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 24:27 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 24:27 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 24:27 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 28:31 , shift_pwr_map8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_rd_cke 37
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 28:31 , 0x9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 28:31 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 28:31 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 28:31 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 32:35 , shift_pwr_map9 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk0_wr_cke 38
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 32:35 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 32:35 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 32:35 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 32:35 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 36:39 , shift_pwr_map10, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 32:35 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1); # cfg_mrnk0_wr_cke 38
-- 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1);
-- 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 36:39 , 0xE , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 36:39 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 36:39 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 36:39 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 36:39 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 36:39 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 36:39 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 40:43 , shift_pwr_map11, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk2_wr_cke 38
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 40:43 , 0xA , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 40:43 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 40:43 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 40:43 , 0x8 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 40:43 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 44:47 , shift_pwr_map12, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk3_wr_cke 38
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 44:47 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 44:47 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 44:47 , 0xC , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 44:47 , 0x4 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 44:47 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-+ 0:63 , ATTR_VPD_CKE_PWR_MAP , 1 , any; # data from VP now
- }
-
-
--scom 0x03010435 {
-- bits , scom_data , ATTR_FUNCTIONAL, expr;
-- 48:51 , shift_pwr_map13, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk4_wr_cke 38
-- 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 48:51 , 0x7 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 48:51 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 48:51 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 48:51 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 48:51 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 48:51 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 52:55 , shift_pwr_map14, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk5_wr_cke 38
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 52:55 , 0xB , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 52:55 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 52:55 , 0x3 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 52:55 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 52:55 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 52:55 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 52:55 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 56:59 , shift_pwr_map15, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk6_wr_cke 38
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 56:59 , 0x6 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 56:59 , 0xF , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 56:59 , 0x2 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 56:59 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
-- 60:63 , ATTR_VPD_CKE_PWR_MAP, 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a == 1); # cfg_mrnk7_wr_cke 38
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm == 1);
-- 60:63 , 0x5 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm == 1);
-- 60:63 , 0xD , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
-- 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4 == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
-- 60:63 , 0x1 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm == 1);
-- 60:63 , 0x0 , 1 , (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm == 1);
--}
-
- ###########################
- # MBA CKE mapping tables #
---
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0006-sbe-pnor.patch b/openpower/package/hostboot/hostboot-0006-sbe-pnor.patch
deleted file mode 100644
index cbf25e1..0000000
--- a/openpower/package/hostboot/hostboot-0006-sbe-pnor.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 961d01024912ce7b0547095d38921bdd61ae8cd8 Mon Sep 17 00:00:00 2001
-From: Brian Horton <brianh@linux.ibm.com>
-Date: Wed, 11 Mar 2015 10:14:31 -0500
-Subject: [PATCH] fix SBE/PNOR merge issues
-
-Change-Id: I74752dbfa50fc78be66a9f185a7c6bc4d31732cd
----
- src/usr/sbe/sbe_update.C | 4 ++--
- 1 files changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/usr/sbe/sbe_update.C b/src/usr/sbe/sbe_update.C
-index a559229..5ac4909 100644
---- a/src/usr/sbe/sbe_update.C
-+++ b/src/usr/sbe/sbe_update.C
-@@ -1791,8 +1791,8 @@ namespace SBE
- reinterpret_cast<void*>(SBE_IMG_VADDR),
- ((io_sbeState.seeprom_side_to_update ==
- EEPROM::SBE_PRIMARY ) ?
-- PNOR::SBE_SEEPROM0 :
-- PNOR::SBE_SEEPROM1 ),
-+ SBE_SEEPROM0 :
-+ SBE_SEEPROM1 ),
- PNOR::WORKING,
- imageWasUpdated );
-
---
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0006_POWER_CONTROL_CAPABLE.patch b/openpower/package/hostboot/hostboot-0006_POWER_CONTROL_CAPABLE.patch
new file mode 100644
index 0000000..e7a902b
--- /dev/null
+++ b/openpower/package/hostboot/hostboot-0006_POWER_CONTROL_CAPABLE.patch
@@ -0,0 +1,181 @@
+From c474b26291b009f7a9c97e2bf94ad2917f11b1b9 Mon Sep 17 00:00:00 2001
+From: Dan Crowell <dcrowell@us.ibm.com>
+Date: Sun, 22 Mar 2015 23:03:57 -0500
+Subject: [PATCH] Add support for POWER_CONTROL_CAPABLE to ISDIMMs
+
+Change-Id: If9de980385cac7706b321a9fefc1158dc540b7e0
+---
+ .../usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H | 11 +++-
+ .../hwp/mvpd_accessors/getControlCapableData.C | 54 ++++++++++----------
+ src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C | 16 ++++++
+ src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C | 3 +
+ 4 files changed, 55 insertions(+), 29 deletions(-)
+
+diff --git a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H
+index 07ea5fc..810cb40 100644
+--- a/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H
++++ b/src/include/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.H
+@@ -46,11 +46,14 @@ namespace getAttrData
+ const uint8_t NUM_PORTS = 2; //Each MBA has 2 ports
+ const uint8_t NUM_DIMMS = 2; //Each port has 2 DIMMs
+ const uint8_t NUM_RANKS = 4; //Number of ranks
+- const uint8_t PORT_SECTION_SIZE = 64; //Each port has 64 bytes
++ //Each port has 64 bytes of space, but only 62 bytes is useable
++ const uint8_t PORT_SECTION_SIZE = 64;
++ const uint8_t PORT_SECTION_USED = 62;
+
+ struct port_attributes
+ {
+- uint8_t port_attr[PORT_SECTION_SIZE];
++ uint8_t port_attr[PORT_SECTION_USED];
++ uint8_t nonport_data[PORT_SECTION_SIZE-PORT_SECTION_USED];
+ };
+ struct mba_attributes
+ {
+@@ -102,6 +105,7 @@ namespace getAttrData
+ UINT32_BY2 =0x0004, // uint32_t [2]
+ UINT32_BY2_BY2 =0x0005, // uint32_t [2][2]
+ UINT64 =0x0006, // uint64_t
++ UINT8 =0x0007, // uint8_t
+ };
+ const uint16_t OUTPUT_TYPE_MASK = 0x00FF;
+
+@@ -111,6 +115,7 @@ namespace getAttrData
+ typedef uint32_t UINT32_BY2_t [2];
+ typedef uint32_t UINT32_BY2_BY2_t [2][2];
+ typedef uint64_t UINT64_t;
++ typedef uint8_t UINT8_t;
+
+ // Special processing
+ // Rules:
+@@ -343,6 +348,8 @@ template<>class MBvpdAttrDataType<fapi::ATTR_VPD_TSYS_ADR>
+ { public: typedef fapi::ATTR_VPD_TSYS_ADR_Type Type; };
+ template<>class MBvpdAttrDataType<fapi::ATTR_VPD_TSYS_DP18>
+ { public: typedef fapi::ATTR_VPD_TSYS_DP18_Type Type; };
++template<>class MBvpdAttrDataType<fapi::ATTR_VPD_POWER_CONTROL_CAPABLE>
++ { public: typedef fapi::ATTR_VPD_POWER_CONTROL_CAPABLE_Type Type; };
+
+
+ // Template function that checks that the type is as expected.
+diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C b/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C
+index 4e4fe02..90afda6 100644
+--- a/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C
++++ b/src/usr/hwpf/hwp/mvpd_accessors/getControlCapableData.C
+@@ -5,7 +5,7 @@
+ /* */
+ /* OpenPOWER HostBoot Project */
+ /* */
+-/* Contributors Listed Below - COPYRIGHT 2014 */
++/* Contributors Listed Below - COPYRIGHT 2014,2015 */
+ /* [+] International Business Machines Corp. */
+ /* */
+ /* */
+@@ -40,38 +40,38 @@ fapi::ReturnCode getControlCapableData(
+ const fapi::Target &i_mbTarget,
+ uint8_t & o_val)
+ {
+- //Record:VSPD, Keyword:MR, offset: 253, 1 byte.
+- const uint32_t MR_KEYWORD_SIZE = 255;
++ fapi::ReturnCode l_rc;
+
+- struct mr_keyword
+- {
+- uint8_t filler[253];
+- uint8_t position; //offset 253
+- uint8_t extraFiller[MR_KEYWORD_SIZE-sizeof(filler)-sizeof(position)];
+- };
+-
+- fapi::ReturnCode l_fapirc;
+- mr_keyword * l_pMrBuffer = new mr_keyword;
+- uint32_t l_MrBufsize = MR_KEYWORD_SIZE;
+- do{
+-
+- l_fapirc = fapiGetMBvpdField(fapi::MBVPD_RECORD_VSPD,
+- fapi::MBVPD_KEYWORD_MR,
+- i_mbTarget,
+- reinterpret_cast<uint8_t *>(l_pMrBuffer),
+- l_MrBufsize);
+- if(l_fapirc)
++ FAPI_DBG("getControlCapableData: start");
++ do {
++ // ATTR_VPD_POWER_CONTROL_CAPABLE is at the membuf level, but the
++ // getMBvpdAttr() function takes a mba, so need to do a
++ // conversion
++ std::vector<fapi::Target> l_mbas;
++ l_rc = fapiGetChildChiplets( i_mbTarget,
++ fapi::TARGET_TYPE_MBA_CHIPLET,
++ l_mbas );
++ if( l_rc )
+ {
+- FAPI_ERR("getControlCapableData: Read of MR Keyword failed");
++ FAPI_ERR("getControlCapableData: fapiGetChildChiplets failed");
+ break;
+ }
+- o_val = l_pMrBuffer->position;
+
+- }while(0);
++ // If we don't have any functional MBAs then we will fail in
++ // the other function so just return a default value here
++ if( l_mbas.empty() )
++ {
++ o_val = fapi::ENUM_ATTR_VPD_POWER_CONTROL_CAPABLE_NONE;
++ break;
++ }
+
+- delete l_pMrBuffer;
+- l_pMrBuffer = NULL;
++ // Call a VPD Accessor HWP to get the data
++ FAPI_EXEC_HWP(l_rc, getMBvpdAttr,
++ l_mbas[0], ATTR_VPD_POWER_CONTROL_CAPABLE,
++ &o_val, sizeof(ATTR_VPD_POWER_CONTROL_CAPABLE_Type));
++ } while(0);
++ FAPI_ERR("getControlCapableData: end");
+
+- return l_fapirc;
++ return l_rc;
+ }
+ }
+diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C
+index b13e4f9..7be8ed2 100644
+--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C
++++ b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttr.C
+@@ -976,6 +976,22 @@ fapi::ReturnCode returnValue (const MBvpdAttrDef* i_pAttrDef,
+ (*(UINT64_t*)o_pVal) = l_value;
+ break ;
+ }
++ case UINT8: // uint8_t
++ {
++ // make sure return value size is correct
++ if (sizeof(UINT8_t) != i_valSize)
++ {
++ l_fapirc = sizeMismatch(sizeof(UINT8_t),
++ i_valSize,
++ i_pAttrDef->iv_attrId);
++ break; //return with error
++ }
++
++ // only 1 value is present, it isn't stored per mba/port
++ uint8_t l_value = (reinterpret_cast<uint8_t*>(i_pBuffer))[l_attrOffset];
++ (*(UINT8_t*)o_pVal) = l_value;
++ break ;
++ }
+ default: // Hard to do, but needs to be caught
+ FAPI_ERR("returnValue: invalid output type 0x%04x for"
+ " attribute ID 0x%08x",
+diff --git a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C
+index 4b18e40..5a599b5 100644
+--- a/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C
++++ b/src/usr/hwpf/hwp/mvpd_accessors/getMBvpdAttrData.C
+@@ -178,6 +178,9 @@ const MBvpdAttrDef g_MBVPD_ATTR_DEF_array [] =
+ {ATTR_VPD_DRAM_2N_MODE_ENABLED,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,48,UINT8_BY2,0},
+ {ATTR_VPD_TSYS_ADR,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT00,0},
+ {ATTR_VPD_TSYS_DP18,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,49,UINT8_BY2|PORT11,0},
++
++// Membuf-level data that is stored within MR
++ {ATTR_VPD_POWER_CONTROL_CAPABLE,ALL_DIMM,ALL_VER,MBVPD_KEYWORD_MR,253,UINT8,0},
+ };
+
+ const uint32_t g_MBVPD_ATTR_DEF_array_size =
+--
+1.7.4.1
+
diff --git a/openpower/package/hostboot/hostboot-0007-mss-thermal-init-SW297647_and_undo.patch b/openpower/package/hostboot/hostboot-0007-mss-thermal-init-SW297647_and_undo.patch
deleted file mode 100644
index f6eafe5..0000000
--- a/openpower/package/hostboot/hostboot-0007-mss-thermal-init-SW297647_and_undo.patch
+++ /dev/null
@@ -1,95 +0,0 @@
-From 430bf7d7b8194bf7789db053999464390e143fdc Mon Sep 17 00:00:00 2001
-From: Brian Horton <brianh@linux.ibm.com>
-Date: Wed, 11 Mar 2015 16:13:11 -0500
-Subject: [PATCH] mss thermal patch from Mike Pradik
-
-AND undeo 1.18 attribute change
-
-Change-Id: I0c3e9d126077fb18bb771909631e0491da4b5f99
----
- .../mss_thermal_init/mss_thermal_init.C | 26 ++++++++++++++++----
- 1 files changed, 21 insertions(+), 5 deletions(-)
-
-diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-index e09f47f..dc21852 100644
---- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-+++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
-@@ -22,7 +22,7 @@
- /* permissions and limitations under the License. */
- /* */
- /* IBM_PROLOG_END_TAG */
--// $Id: mss_thermal_init.C,v 1.19 2015/02/12 23:23:56 pardeik Exp $
-+// $Id: mss_thermal_init.C,v 1.18c CHANGED IN OPENPOWER PATCH brianh Exp $
- // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $
- //------------------------------------------------------------------------------
- // *! (C) Copyright International Business Machines Corp. 2011
-@@ -49,6 +49,8 @@
- //------------------------------------------------------------------------------
- // Version:| Author: | Date: | Comment:
- //---------|----------|---------|-----------------------------------------------
-+// 1.18v | brianhk |11-MAR-15| undo 1.18 change
-+// 1.18u | pardeik |03-MAR-15| user version to be like v1.20
- // 1.18 | pardeik |12-FEB-15| change ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP to
- // | a centaur target (was system)
- // 1.17 | pardeik |19-NOV-14| Use MRW attribute for SC address map for ISDIMMs
-@@ -160,6 +162,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
- const uint8_t I2C_BUS_ENCODE_PRIMARY = 0;
- const uint8_t I2C_BUS_ENCODE_SECONDARY = 8;
- const uint8_t MAX_NUM_DIMM_SENSORS = 8;
-+ const uint8_t MAX_I2C_BUSSES = 2;
-
- // Variable declaration
- uint8_t l_dimm_ranks_array[l_NUM_MBAS][l_NUM_PORTS][l_NUM_DIMMS]; // Number of ranks for each configured DIMM in each MBA
-@@ -249,6 +252,19 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
- l_custom_dimm[i] = fapi::ENUM_ATTR_EFF_CUSTOM_DIMM_NO;
- }
-
-+ // zero out the l_dimm_ranks_array so it is initialized for later use if there is a deconfigured MBA
-+ for (uint8_t i = 0; i < l_NUM_MBAS; i++)
-+ {
-+ for (uint8_t j = 0; j < l_NUM_PORTS; j++)
-+ {
-+ for (uint8_t k = 0; k < l_NUM_DIMMS; k++)
-+ {
-+ l_dimm_ranks_array[i][j][k]=0;
-+ }
-+ }
-+
-+ }
-+
- for (uint8_t mba_index = 0; mba_index < l_target_mba_array.size(); mba_index++){
- l_rc = FAPI_ATTR_GET(ATTR_CHIP_UNIT_POS, &l_target_mba_array[mba_index], l_mba_pos);
- if (l_rc) return l_rc;
-@@ -279,7 +295,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
- else
- {
- // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are)
-- l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, &i_target, l_dimm_sensor_cache_addr_map);
-+ l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, NULL, l_dimm_sensor_cache_addr_map);
- if (l_rc) return l_rc;
- }
-
-@@ -399,9 +415,9 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
-
- l_cdimm_number_dimm_temp_sensors = 0;
- // cycle through both primary and secondary i2c busses, determine i2c address and enable bits
-- for (uint8_t k = 0; k < 2; k++)
-+ for (uint8_t k = 0; k < MAX_I2C_BUSSES; k++)
- {
-- for (uint8_t i = 0; i < 8; i++)
-+ for (uint8_t i = 0; i < MAX_NUM_DIMM_SENSORS; i++)
- {
- if (k == 0)
- {
-@@ -492,7 +508,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
- // Iterate through the num_ranks array to determine what DIMMs are plugged
- // Enable sensor monitoring for each plugged DIMM
- uint32_t l_iterator = 0;
-- for (uint32_t i = 0; i < 2; i++){
-+ for (uint32_t i = 0; i < l_NUM_MBAS; i++){
- if (l_dimm_ranks_array[i][0][0] != 0){
- l_ecmd_rc |= l_data_scac_enable.setBit(l_iterator);
- }
---
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0007_mss_thermal_undo.patch b/openpower/package/hostboot/hostboot-0007_mss_thermal_undo.patch
new file mode 100644
index 0000000..455b3c7
--- /dev/null
+++ b/openpower/package/hostboot/hostboot-0007_mss_thermal_undo.patch
@@ -0,0 +1,43 @@
+From d7b5b4a29107c17ad97b2c25cec11f51df485ea1 Mon Sep 17 00:00:00 2001
+From: Brian Horton <brianh@linux.ibm.com>
+Date: Tue, 31 Mar 2015 13:26:40 -0500
+Subject: [PATCH] undo 1.18 change
+
+Change-Id: I477dd4a478fc3c752a7f4f9dd1dff9f03ce39cc1
+---
+ .../mss_thermal_init/mss_thermal_init.C | 5 +++--
+ 1 files changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+index a98b58d..b90d1d6 100644
+--- a/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
++++ b/src/usr/hwpf/hwp/dram_initialization/mss_thermal_init/mss_thermal_init.C
+@@ -22,7 +22,7 @@
+ /* permissions and limitations under the License. */
+ /* */
+ /* IBM_PROLOG_END_TAG */
+-// $Id: mss_thermal_init.C,v 1.20 2015/03/02 20:43:37 pardeik Exp $
++// $Id: mss_thermal_init.C,v 1.20a CHANGED IN OPENPOWER PATCH brianh Exp $
+ // $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/centaur/working/procedures/ipl/fapi/mss_thermal_init.C,v $
+ //------------------------------------------------------------------------------
+ // *! (C) Copyright International Business Machines Corp. 2011
+@@ -49,6 +49,7 @@
+ //------------------------------------------------------------------------------
+ // Version:| Author: | Date: | Comment:
+ //---------|----------|---------|-----------------------------------------------
++// 1.20a | brianh |31-MAR-15| under 1.18
+ // 1.20 | pardeik |02-MAR-15| initialize l_dimm_ranks_array to zero
+ // | use const variables in for loops instead of numbers
+ // 1.18 | pardeik |12-FEB-15| change ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP to
+@@ -295,7 +296,7 @@ fapi::ReturnCode mss_thermal_init(const fapi::Target & i_target)
+ else
+ {
+ // sensor cache address map for non custom dimm temperature sensors (which i2c bus and i2c address they are)
+- l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, &i_target, l_dimm_sensor_cache_addr_map);
++ l_rc = FAPI_ATTR_GET(ATTR_MRW_MEM_SENSOR_CACHE_ADDR_MAP, NULL, l_dimm_sensor_cache_addr_map);
+ if (l_rc) return l_rc;
+ }
+
+--
+1.7.4.1
+
diff --git a/openpower/package/hostboot/hostboot-0010-Support-partial-good-Xbus.patch b/openpower/package/hostboot/hostboot-0010-Support-partial-good-Xbus.patch
deleted file mode 100644
index df1a728..0000000
--- a/openpower/package/hostboot/hostboot-0010-Support-partial-good-Xbus.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 07b936c1c5f97314719e7e988e6c07810637b8c1 Mon Sep 17 00:00:00 2001
-From: Dean Sanner <dsanner@us.ibm.com>
-Date: Wed, 11 Mar 2015 09:11:14 -0500
-Subject: [PATCH 3/8] Support partial good Xbus
-
-Change-Id: I245cd9947d5b7a05ff9a8f92ff18c658b1fe09d6
-Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16300
-Tested-by: Jenkins Server
-Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-Reviewed-by: Brian H. Horton <brianh@linux.ibm.com>
-Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-(cherry picked from commit a0f4a934254572ce49a1ddf5e4d5d944b52779be)
----
- src/usr/hwpf/plat/fapiPlatAttributeService.C | 22 ++++++++++++++++++----
- 1 file changed, 18 insertions(+), 4 deletions(-)
-
-diff --git a/src/usr/hwpf/plat/fapiPlatAttributeService.C b/src/usr/hwpf/plat/fapiPlatAttributeService.C
-index 6e4f400..7da841a 100644
---- a/src/usr/hwpf/plat/fapiPlatAttributeService.C
-+++ b/src/usr/hwpf/plat/fapiPlatAttributeService.C
-@@ -58,11 +58,14 @@
- #include <hwpf/hwp/pll_accessors/getPllRingInfoAttr.H>
- #include <hwpf/hwp/winkle_ring_accessors/getL3DeltaDataAttr.H>
- #include <fapiAttributeIds.H>
-+#include <hwas/common/hwasCommon.H>
-+
- // The following file checks at compile time that all HWPF attributes are
- // handled by Hostboot. This is done to ensure that the HTML file listing
- // supported HWPF attributes lists attributes handled by Hostboot
- #include <fapiAttributePlatCheck.H>
-
-+
- //******************************************************************************
- // Implementation
- //******************************************************************************
-@@ -1239,6 +1242,7 @@ fapi::ReturnCode fapiPlatGetEnableAttr ( fapi::AttributeId i_id,
- {
- fapi::ReturnCode l_rc;
- TARGETING::Target * l_pTarget = NULL;
-+ o_enable = 0;
-
- // Get the Targeting Target
- l_rc = getTargetingTarget(i_pFapiTarget, l_pTarget);
-@@ -1271,10 +1275,20 @@ fapi::ReturnCode fapiPlatGetEnableAttr ( fapi::AttributeId i_id,
- o_enable = 1;
- break;
- case fapi::ATTR_PROC_X_ENABLE:
-- // The enable flag reflects the state of the pervasive chiplet,
-- // NOT the bus logic, so always return true since we don't
-- // support partial good on the XBUS chiplet
-- o_enable = 1;
-+ // Need to support having the X bus chiplet partial good
-+ // Look at the saved away PG data
-+ TARGETING::ATTR_CHIP_REGIONS_TO_ENABLE_type l_chipRegionData;
-+ l_rc = FAPI_ATTR_GET(ATTR_CHIP_REGIONS_TO_ENABLE, i_pFapiTarget,
-+ l_chipRegionData);
-+ if (l_rc) {
-+ FAPI_ERR("fapi_attr_get( ATTR_CHIP_REGIONS_TO_ENABLE ) failed. With rc = 0x%x",
-+ (uint32_t) l_rc );
-+ break;
-+ }
-+ else if (l_chipRegionData[HWAS::VPD_CP00_PG_XBUS_INDEX] != 0)
-+ {
-+ o_enable = 0x1;
-+ }
- break;
- default:
- o_enable = 0;
---
-1.8.2.2
-
diff --git a/openpower/package/hostboot/hostboot-0011-Pull-model-name-and-serial-from-OSYS-record-if-avail.patch b/openpower/package/hostboot/hostboot-0011-Pull-model-name-and-serial-from-OSYS-record-if-avail.patch
deleted file mode 100644
index 0f20e0b..0000000
--- a/openpower/package/hostboot/hostboot-0011-Pull-model-name-and-serial-from-OSYS-record-if-avail.patch
+++ /dev/null
@@ -1,213 +0,0 @@
-From 438ebf4b5acbaab0da69009d4248a6aac45fbed6 Mon Sep 17 00:00:00 2001
-From: Dan Crowell <dcrowell@us.ibm.com>
-Date: Wed, 11 Mar 2015 16:44:59 -0500
-Subject: [PATCH 3/5] Pull model name and serial from OSYS record if available
-
-The supported level of OP planar VPD has the system model
-name inside OSYS:MM, not OPFR:DR.
-
-Change-Id: Iaa9c4e00325f8fa6efb7a9fca1275bcea2759308
-Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16308
-Reviewed-by: William H. Schwartz <whs@us.ibm.com>
-Tested-by: Jenkins Server
-Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
-(cherry picked from commit 2114a66c76558f41cd305fc294ccdfaf6607c0e5)
----
- src/usr/devtree/bld_devtree.C | 142 +++++++++++++++++++++++++++++++++++++-----
- 1 file changed, 126 insertions(+), 16 deletions(-)
-
-diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
-index f2e9438..622178a 100644
---- a/src/usr/devtree/bld_devtree.C
-+++ b/src/usr/devtree/bld_devtree.C
-@@ -1034,18 +1034,26 @@ errlHndl_t bld_fdt_system(devTree * i_dt, bool i_smallTree)
- // Nothing to do for small trees currently.
- if (!i_smallTree)
- {
-+ //===== compatible =====
- /* Fetch the MRW-defined compatible model from attributes */
- ATTR_OPAL_MODEL_type l_model = {0};
- TARGETING::Target* sys = NULL;
- TARGETING::targetService().getTopLevelTarget(sys);
- sys->tryGetAttr<TARGETING::ATTR_OPAL_MODEL>(l_model);
-
-- /* Add compatibility node */
-+ /* Add compatibility value */
- const char* l_compats[] = { "ibm,powernv", l_model, NULL };
- i_dt->addPropertyStrings(rootNode, "compatible", l_compats);
-
-- /* Add system model node */
-- // Based off of the DR field in the OPFR
-+ //===== model =====
-+ /* Add system model value
-+ Depending on the vintage of the planar VPD, there are 3 places
-+ we need to look for this data.
-+ 1) OSYS:MM
-+ 2) OPFR:DR
-+ 3) Default to 'unknown'
-+ */
-+ bool foundvpd = false;
- // TODO RTC 118373 -- update to account for firestone/memory riser
- TARGETING::TargetHandleList l_membTargetList;
- getAllChips(l_membTargetList, TYPE_MEMBUF);
-@@ -1061,42 +1069,144 @@ errlHndl_t bld_fdt_system(devTree * i_dt, bool i_smallTree)
- errhdl = deviceRead( l_pMem,
- NULL,
- vpdSize,
-- DEVICE_CVPD_ADDRESS( CVPD::OPFR,
-- CVPD::DR ));
-+ DEVICE_CVPD_ADDRESS( CVPD::OSYS,
-+ CVPD::MM ));
-
- if(errhdl)
- {
-- TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't get DR size for HUID=0x%.8X",
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't get OSYS:MM size for HUID=0x%.8X",
- TARGETING::get_huid(l_pMem));
-- i_dt->addPropertyString(rootNode, "model", "unknown");
-- errlCommit(errhdl, DEVTREE_COMP_ID);
-+
-+ // Try the OPFR record
-+ errlHndl_t opfr_errhdl = deviceRead( l_pMem,
-+ NULL,
-+ vpdSize,
-+ DEVICE_CVPD_ADDRESS( CVPD::OPFR,
-+ CVPD::DR ));
-+ if(opfr_errhdl)
-+ {
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't get OPFR:DR size for HUID=0x%.8X",
-+ TARGETING::get_huid(l_pMem));
-+ delete opfr_errhdl; //delete OPFR log, VPD is just bad
-+ }
-+ else
-+ {
-+ delete errhdl; //ignore lack of OSYS due to older vpd
-+ errhdl = NULL;
-+ char drBuf[vpdSize+1];
-+ memset(&drBuf, 0x0, (vpdSize+1)); //null terminated str
-+ errhdl = deviceRead( l_pMem,
-+ reinterpret_cast<void*>( &drBuf ),
-+ vpdSize,
-+ DEVICE_CVPD_ADDRESS( CVPD::OPFR,
-+ CVPD::DR ));
-+
-+ if(errhdl)
-+ {
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't read OPFR:DR for HUID=0x%.8X",
-+ TARGETING::get_huid(l_pMem));
-+ }
-+ else
-+ {
-+ foundvpd = true;
-+ i_dt->addPropertyString(rootNode, "model", drBuf);
-+ }
-+ }
- }
- else
- {
-- char drBuf[vpdSize+1];
-- memset(&drBuf, 0x0, (vpdSize+1)); //ensure null terminated str
-+ char mmBuf[vpdSize+1];
-+ memset(&mmBuf, 0x0, (vpdSize+1)); //ensure null terminated str
- errhdl = deviceRead( l_pMem,
-- reinterpret_cast<void*>( &drBuf ),
-+ reinterpret_cast<void*>( &mmBuf ),
- vpdSize,
-- DEVICE_CVPD_ADDRESS( CVPD::OPFR,
-- CVPD::DR ));
-+ DEVICE_CVPD_ADDRESS( CVPD::OSYS,
-+ CVPD::MM ));
-
- if(errhdl)
- {
-- TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't read DR for HUID=0x%.8X",
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't read OSYS:MM for HUID=0x%.8X",
- TARGETING::get_huid(l_pMem));
- }
- else
- {
-- i_dt->addPropertyString(rootNode, "model", drBuf);
-+ foundvpd = true;
-+ i_dt->addPropertyString(rootNode, "model", mmBuf);
- }
- }
- }
-- else //chassis info not found, default to unknown
-+
-+ // just commit any errors we get, this isn't critical
-+ if( errhdl )
-+ {
-+ errlCommit(errhdl, DEVTREE_COMP_ID); //commit original OSYS log
-+ }
-+
-+ if( !foundvpd ) //chassis info not found, default to unknown
- {
- TRACFCOMP(g_trac_devtree,ERR_MRK" VPD not found, model defaulted to unknown");
- i_dt->addPropertyString(rootNode, "model", "unknown");
- }
-+
-+ //===== system-id =====
-+ /* Add system-id value
-+ 1) OSYS:SS
-+ 2) Default to 'unavailable'
-+ */
-+ // TODO RTC 118373 -- update to account for firestone/memory riser
-+ foundvpd = false;
-+ if( l_membTargetList.size() )
-+ {
-+ // TODO RTC 118373 - Should be able to read from attribute
-+ TARGETING::Target * l_pMem = l_membTargetList[0];
-+ size_t vpdSize = 0x0;
-+
-+ // Note: First read with NULL for o_buffer sets vpdSize to the
-+ // correct length
-+ errhdl = deviceRead( l_pMem,
-+ NULL,
-+ vpdSize,
-+ DEVICE_CVPD_ADDRESS( CVPD::OSYS,
-+ CVPD::SS ));
-+
-+ if(errhdl)
-+ {
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't get OSYS:SS size for HUID=0x%.8X",
-+ TARGETING::get_huid(l_pMem));
-+ // Note - not supporting old vpd versions without OSYS here
-+ }
-+ else
-+ {
-+ char ssBuf[vpdSize+1];
-+ memset(&ssBuf, 0x0, (vpdSize+1)); //ensure null terminated str
-+ errhdl = deviceRead( l_pMem,
-+ reinterpret_cast<void*>( &ssBuf ),
-+ vpdSize,
-+ DEVICE_CVPD_ADDRESS( CVPD::OSYS,
-+ CVPD::SS ));
-+
-+ if(errhdl)
-+ {
-+ TRACFCOMP(g_trac_devtree,ERR_MRK" Couldn't read OSYS:SS for HUID=0x%.8X",
-+ TARGETING::get_huid(l_pMem));
-+ }
-+ else
-+ {
-+ foundvpd = true;
-+ i_dt->addPropertyString(rootNode, "system-id", ssBuf);
-+ }
-+ }
-+ }
-+ // just commit any errors we get, this isn't critical
-+ if( errhdl )
-+ {
-+ errlCommit(errhdl, DEVTREE_COMP_ID);
-+ }
-+
-+ if( !foundvpd ) //serial number not found, default to unavailable
-+ {
-+ i_dt->addPropertyString(rootNode, "system-id", "unavailable");
-+ }
- }
-
- return errhdl;
---
-1.8.2.2
-
diff --git a/openpower/package/hostboot/hostboot-0013-Enable-vrml-mvpd.patch b/openpower/package/hostboot/hostboot-0013-Enable-vrml-mvpd.patch
deleted file mode 100644
index 04118e9..0000000
--- a/openpower/package/hostboot/hostboot-0013-Enable-vrml-mvpd.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From a5d5840c4780a39be436e2dde2a53037b1b82635 Mon Sep 17 00:00:00 2001
-From: Bill Hoffa <wghoffa@us.ibm.com>
-Date: Mon, 30 Mar 2015 19:22:44 -0500
-Subject: [PATCH] Add VRML MVPD Enablement for Habanero
-
-Change-Id: I7dd2d155e295a5fee09010ba173c82748e25221d
----
- src/include/usr/vpd/mvpdenums.H | 1 +
- src/usr/vpd/mvpd.H | 1 +
- 2 files changed, 2 insertions(+)
-
-diff --git a/src/include/usr/vpd/mvpdenums.H b/src/include/usr/vpd/mvpdenums.H
-index 950245f..fd4ddaf 100644
---- a/src/include/usr/vpd/mvpdenums.H
-+++ b/src/include/usr/vpd/mvpdenums.H
-@@ -79,6 +79,7 @@ enum mvpdRecord
- LWPE = 0x20,
- VWML = 0x21,
- MER0 = 0x22,
-+ VRML = 0x23,
-
- // Last Record
- MVPD_LAST_RECORD,
-diff --git a/src/usr/vpd/mvpd.H b/src/usr/vpd/mvpd.H
-index 60a8491..e9fe905 100644
---- a/src/usr/vpd/mvpd.H
-+++ b/src/usr/vpd/mvpd.H
-@@ -88,6 +88,7 @@ namespace MVPD
- { LWPE, "LWPE" },
- { VWML, "VWML" },
- { MER0, "MER0" },
-+ { VRML, "VRML" },
- // -------------------------------------------------------------------
- // DO NOT USE!! This is for test purposes ONLY!
- { MVPD_TEST_RECORD, "TEST" },
---
-1.8.2.2
-
diff --git a/openpower/package/hostboot/hostboot-0016-Initialize-I2C-Switches-in-struct-to-zero.patch b/openpower/package/hostboot/hostboot-0016-Initialize-I2C-Switches-in-struct-to-zero.patch
deleted file mode 100644
index d7da480..0000000
--- a/openpower/package/hostboot/hostboot-0016-Initialize-I2C-Switches-in-struct-to-zero.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From 4c31ecf3b63f4f21e677d7359f64de22cd8fc1eb Mon Sep 17 00:00:00 2001
-From: Mike Baiocchi <baiocchi@us.ibm.com>
-Date: Wed, 18 Mar 2015 10:31:21 -0500
-Subject: [PATCH] Initialize I2C Switches in struct to zero
-
-There are multiple uses for the I2C Switches in the misc_args_t
-struct used in I2C operations. The struct was not defaulting the
-switches value to zero and there were negative consequences of this
-early in the IPL for the i2cPresence() function.
-
-Fixes open-power/hostboot#18
-
-Change-Id: I83d34770ff04cfe31bf07b320d8821c8fa80c705
-CQ: SW2999529
-Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/16447
-Tested-by: Jenkins Server
-Reviewed-by: MATTHEW A. PLOETZ <maploetz@us.ibm.com>
-Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
-Reviewed-by: A. Patrick Williams III <iawillia@us.ibm.com>
----
- src/usr/i2c/i2c.C | 4 +++-
- src/usr/i2c/i2c_common.H | 5 ++++-
- 2 files changed, 7 insertions(+), 2 deletions(-)
-
-diff --git a/src/usr/i2c/i2c.C b/src/usr/i2c/i2c.C
-index 1f2b8a0..f8583b8 100755
---- a/src/usr/i2c/i2c.C
-+++ b/src/usr/i2c/i2c.C
-@@ -688,7 +688,9 @@ bool i2cPresence( TARGETING::Target * i_target,
-
-
-
-- //Set Host vs FSI switches
-+ // Set I2C Mode (Host vs FSI) for the target
-+ args.switches.useHostI2C = 0;
-+ args.switches.useFsiI2C = 0;
- i2cSetSwitches( i_target, args );
-
- err = i2cSetBusVariables(i_target,
-diff --git a/src/usr/i2c/i2c_common.H b/src/usr/i2c/i2c_common.H
-index 68865a5..1772ea2 100644
---- a/src/usr/i2c/i2c_common.H
-+++ b/src/usr/i2c/i2c_common.H
-@@ -75,7 +75,10 @@ struct misc_args_t
- polling_interval_ns(0),
- timeout_count(0),
- offset_length(0),
-- offset_buffer(NULL){};
-+ offset_buffer(NULL)
-+ {
-+ memset(&switches, 0x0, sizeof(switches));
-+ };
-
- };
-
---
-2.3.0
-
diff --git a/openpower/package/hostboot/hostboot.mk b/openpower/package/hostboot/hostboot.mk
index 478f3ed..aa689ce 100644
--- a/openpower/package/hostboot/hostboot.mk
+++ b/openpower/package/hostboot/hostboot.mk
@@ -4,7 +4,7 @@
#
################################################################################
-HOSTBOOT_VERSION ?= bda236e6e0c7d3aa5165160abbd5ead92ac0a68e
+HOSTBOOT_VERSION ?= f18b0d9ab1a518dc5556bb01b264b67ad63f6f00
HOSTBOOT_SITE ?= $(call github,open-power,hostboot,$(HOSTBOOT_VERSION))
HOSTBOOT_LICENSE = Apache-2.0
diff --git a/openpower/package/palmetto-xml/palmetto-xml-0001-Revert-Merge-pull-request-12-from-open-power-bofferd.patch b/openpower/package/palmetto-xml/palmetto-xml-0001-Revert-Merge-pull-request-12-from-open-power-bofferd.patch
deleted file mode 100644
index 1eea695..0000000
--- a/openpower/package/palmetto-xml/palmetto-xml-0001-Revert-Merge-pull-request-12-from-open-power-bofferd.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From 55eae8d646b3c95df32b67ef8d67887581f94fa0 Mon Sep 17 00:00:00 2001
-From: Bill Hoffa <wghoffa@us.ibm.com>
-Date: Tue, 31 Mar 2015 08:15:06 -0500
-Subject: [PATCH] Revert "Merge pull request #12 from
- open-power/bofferdn-pal-loadline"
-
-This reverts commit dbe13549a81c15c81e1fbd2d3de80ea91dd20503, reversing
-changes made to 167ded68387aa69fabb28e6cafaa6ae4bf165a40.
-
-Conflicts:
- palmetto.xml
----
- palmetto.xml | 48 ++++++++++++++++++++++++------------------------
- 1 file changed, 24 insertions(+), 24 deletions(-)
-
-diff --git a/palmetto.xml b/palmetto.xml
-index 6df6652..89669ab 100644
---- a/palmetto.xml
-+++ b/palmetto.xml
-@@ -2854,6 +2854,30 @@
- <default>1</default>
- </attribute>
- <attribute>
-+ <id>PROC_R_DISTLOSS_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_DISTLOSS_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_LOADLINE_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_R_LOADLINE_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_VRM_VOFFSET_VCS</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
-+ <id>PROC_VRM_VOFFSET_VDD</id>
-+ <default></default>
-+ </attribute>
-+ <attribute>
- <id>PROC_X_BUS_WIDTH</id>
- <default>2</default>
- </attribute>
-@@ -3735,30 +3759,6 @@
- <default>0</default>
- </attribute>
- <attribute>
-- <id>PROC_R_DISTLOSS_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_DISTLOSS_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_LOADLINE_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_R_LOADLINE_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_VRM_VOFFSET_VCS</id>
-- <default></default>
-- </attribute>
-- <attribute>
-- <id>PROC_VRM_VOFFSET_VDD</id>
-- <default></default>
-- </attribute>
-- <attribute>
- <id>PSI_BRIDGE_BASE_ADDR</id>
- <default>0,0x0000000000000000</default>
- </attribute>
---
-1.8.2.2
-