diff --git a/openpower/package/hostboot/hostboot-0004-Downgrade-OCC-Config-Data-Version-if-no-FIR-Master.patch b/openpower/package/hostboot/hostboot-0004-Downgrade-OCC-Config-Data-Version-if-no-FIR-Master.patch
new file mode 100644
index 0000000..4cda4f5
--- /dev/null
+++ b/openpower/package/hostboot/hostboot-0004-Downgrade-OCC-Config-Data-Version-if-no-FIR-Master.patch
@@ -0,0 +1,42 @@
+From 93266f96f39f038fc8ad396a5df316c07980f4bf Mon Sep 17 00:00:00 2001
+From: Dan Crowell <dcrowell@us.ibm.com>
+Date: Sat, 28 Feb 2015 11:54:47 -0600
+Subject: [PATCH 3/4] Downgrade OCC Config Data Version if no FIR Master
+
+Change-Id: Idc48298a9c3068da2216172da474ebff93eb3839
+(cherry picked from commit f84f34cc5628d9e7d7d55d0e95462b3fe22d80d5)
+---
+ src/include/usr/hwpf/hwp/occ/occ_common.H |    2 ++
+ src/usr/hwpf/hwp/occ/occ_common.C         |    3 +++
+ 2 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/src/include/usr/hwpf/hwp/occ/occ_common.H b/src/include/usr/hwpf/hwp/occ/occ_common.H
+index ca7ab39..7ddb302 100644
+--- a/src/include/usr/hwpf/hwp/occ/occ_common.H
++++ b/src/include/usr/hwpf/hwp/occ/occ_common.H
+@@ -58,6 +58,8 @@ namespace HBOCC
+     enum
+     {
+         OccHostDataVersion = 3,
++        PRE_FIR_MASTER_VERSION = 2,
++
+         OCC_LIDID = 0x81e00430,
+         OCC_IBSCOM_RANGE_IN_MB = MEGABYTE,
+ 
+diff --git a/src/usr/hwpf/hwp/occ/occ_common.C b/src/usr/hwpf/hwp/occ/occ_common.C
+index 98e6382..0373727 100644
+--- a/src/usr/hwpf/hwp/occ/occ_common.C
++++ b/src/usr/hwpf/hwp/occ/occ_common.C
+@@ -170,6 +170,9 @@ namespace HBOCC
+         }
+ #else
+         config_data->firMaster = 0;
++        //force to an older version so we can support
++        // older levels of OCC
++        config_data->version = PRE_FIR_MASTER_VERSION;
+ #endif
+ 
+         TRACUCOMP( g_fapiTd,
+-- 
+1.7.4.1
+
diff --git a/openpower/package/hostboot/hostboot-0004-revert-OCC-v3.patch b/openpower/package/hostboot/hostboot-0004-revert-OCC-v3.patch
deleted file mode 100644
index 5999ffc..0000000
--- a/openpower/package/hostboot/hostboot-0004-revert-OCC-v3.patch
+++ /dev/null
@@ -1,205 +0,0 @@
-From 4619901bd09eccbe26d430195c4e8019f6993b0b Mon Sep 17 00:00:00 2001
-From: Matt Ploetz <maploetz@us.ibm.com>
-Date: Mon, 23 Feb 2015 17:09:14 -0600
-Subject: [PATCH] Revert "Set FIR master in HOMER config data"
-
-This reverts commit 84023756531d9c48d2e4939326f4048f2dadbe28.
----
- src/include/usr/hwpf/hwp/occ/occ_common.H | 27 ++----------------
- src/usr/diag/HBconfig                     |  6 ----
- src/usr/hwpf/hwp/occ/occ.C                |  2 +-
- src/usr/hwpf/hwp/occ/occ_common.C         | 46 +++++++++++++++++++------------
- src/usr/hwpf/hwp/occ/runtime/rt_occ.C     |  2 +-
- 5 files changed, 33 insertions(+), 50 deletions(-)
-
-diff --git a/src/include/usr/hwpf/hwp/occ/occ_common.H b/src/include/usr/hwpf/hwp/occ/occ_common.H
-index 8245539..1886e51 100644
---- a/src/include/usr/hwpf/hwp/occ/occ_common.H
-+++ b/src/include/usr/hwpf/hwp/occ/occ_common.H
-@@ -36,38 +36,19 @@ namespace HBOCC
-     struct occHostConfigDataArea_t
-     {
-         uint32_t version;
--
--        //For computation of timebase frequency
-         uint32_t nestFrequency;
--
--        // For determining the interrupt type to Host
--        //  0x00000000 = Use FSI2HOST Mailbox
--        //  0x00000001 = Use OCC interrupt line through PSIHB complex
-         uint32_t interruptType;
--
--        // For informing OCC if it is the FIR master:
--        //  0x00000000 = Default
--        //  0x00000001 = FIR Master
--        uint32_t firMaster;
--
--        // FIR collection configuration data needed by FIR Master
--        //  OCC in the event of a checkstop
--        uint8_t firdataConfig[3072];
-     };
- 
-     enum
-     {
--        OccHostDataVersion = 3,
-+        OccHostDataVersion = 2,
-         OCC_LIDID = 0x81e00430,
-         OCC_IBSCOM_RANGE_IN_MB = MEGABYTE,
- 
-         // Interrupt Types
-         USE_FSI2HOST_MAILBOX = 0x00000000,
--        USE_PSIHB_COMPLEX    = 0x00000001,
--
--        // FIR Master
--        NOT_FIR_MASTER = 0x00000000,
--        IS_FIR_MASTER  = 0x00000001
-+        USE_PSIHB_COMPLEX    = 0x00000001
-     };
- 
-     enum occAction_t
-@@ -78,15 +59,13 @@ namespace HBOCC
-     /**
-      * @brief Sets up OCC Host data
-      *
--     * @param[in] i_proc:         target processor to load
-      * @param[in] i_occHostDataVirtAddr Virtual
-      *                       address of current
-      *                       proc's Host data area.
-      *
-      * @return errlHndl_t  Error log Host data setup failed
-      */
--    errlHndl_t loadHostDataToHomer(TARGETING::Target* i_proc,
--                                   void* i_occHostDataVirtAddr);
-+    errlHndl_t loadHostDataToHomer(void* i_occHostDataVirtAddr);
- 
-     /**
-      * @brief Execute procedures and steps required to load
-diff --git a/src/usr/diag/HBconfig b/src/usr/diag/HBconfig
-index 973cecd..a516133 100644
---- a/src/usr/diag/HBconfig
-+++ b/src/usr/diag/HBconfig
-@@ -2,9 +2,3 @@ config HBRT_PRD
-     default n
-     help
-         Enable HBRT PRD.
--
--config ENABLE_CHECKSTOP_ANALYSIS
--    default n
--    help
--        Enable collection of FIR data by OCC for checkstops and
--        post-checkstop analysis by PRD on system reboot
-diff --git a/src/usr/hwpf/hwp/occ/occ.C b/src/usr/hwpf/hwp/occ/occ.C
-index ac2f4b1..f56c909 100644
---- a/src/usr/hwpf/hwp/occ/occ.C
-+++ b/src/usr/hwpf/hwp/occ/occ.C
-@@ -133,7 +133,7 @@ namespace HBOCC
-                                            (i_homerVirtAddrBase) +
-                                 tmpOffset + HOMER_OFFSET_TO_OCC_HOST_DATA;
-             void* occHostVirt = reinterpret_cast<void*>(i_homerHostVirtAddr);
--            l_errl = HBOCC::loadHostDataToHomer(i_target,occHostVirt);
-+            l_errl = HBOCC::loadHostDataToHomer(occHostVirt);
-             if( l_errl != NULL )
-             {
-                 TRACFCOMP( g_fapiImpTd, ERR_MRK"loading Host Data Area failed!" );
-diff --git a/src/usr/hwpf/hwp/occ/occ_common.C b/src/usr/hwpf/hwp/occ/occ_common.C
-index e444b26..97d36f4 100644
---- a/src/usr/hwpf/hwp/occ/occ_common.C
-+++ b/src/usr/hwpf/hwp/occ/occ_common.C
-@@ -119,9 +119,14 @@ namespace HBOCC
- 
-     /**
-      * @brief Sets up OCC Host data
-+     *
-+     * @param[in] i_occHostDataVirtAddr Virtual
-+     *                       address of current
-+     *                       proc's Host data area.
-+     *
-+     * @return errlHndl_t  Error log Host data setup failed
-      */
--    errlHndl_t loadHostDataToHomer( TARGETING::Target* i_proc,
--                                    void* i_occHostDataVirtAddr)
-+    errlHndl_t loadHostDataToHomer(void* i_occHostDataVirtAddr)
-     {
-         TRACUCOMP( g_fapiTd,
-                    ENTER_MRK"loadHostDataToHomer(%p)",
-@@ -156,22 +161,6 @@ namespace HBOCC
-             config_data->interruptType = USE_PSIHB_COMPLEX;
-         }
- 
--#ifdef CONFIG_ENABLE_CHECKSTOP_ANALYSIS
--        // Figure out the FIR master
--        TARGETING::Target* masterproc = NULL;
--        tS.masterProcChipTargetHandle( masterproc );
--        if( masterproc == i_proc )
--        {
--            config_data->firMaster = IS_FIR_MASTER;
--        }
--        else
--        {
--            config_data->firMaster = NOT_FIR_MASTER;
--        }
--#else
--        config_data->firMaster = 0;
--#endif
--
-         TRACUCOMP( g_fapiTd,
-                    EXIT_MRK"loadHostDataToHomer");
- 
-@@ -181,6 +170,16 @@ namespace HBOCC
-     /**
-      * @brief Execute procedures and steps necessary
-      *        to load OCC data in specified processor
-+     *
-+     * @param[in] i_target   Target proc to load
-+     * @param[in] i_homerVirtAddrBase Virtual
-+     *                       address of current
-+     *                       proc's HOMER
-+     * @param[in] i_homerPhysAddrBase Physical
-+     *                       address of current
-+     *                       proc's HOMER
-+     *
-+     * @return errlHndl_t  Error log image load failed
-      */
-      errlHndl_t loadOCC(TARGETING::Target* i_target,
-                     uint64_t i_homerPhysAddr,
-@@ -300,6 +299,12 @@ namespace HBOCC
-      * @brief Start OCC for specified DCM pair of processors.
-      *        If 2nd input is NULL, OCC will be setup on just
-      *        one target.
-+     *
-+     * @param[in] i_target0:    target of first processor in DCM pair
-+     * @param[in] i_target1:    target of second processor in DCM pair
-+     * @param[out] o_failedTarget failed target in case of an error
-+     *
-+     * @return errlHndl_t  Error log of startOCC failed
-      */
-     errlHndl_t startOCC (Target* i_target0,
-                          Target* i_target1,
-@@ -418,6 +423,11 @@ namespace HBOCC
-      * @brief Stop OCC for specified DCM pair of processors.
-      *        If 2nd input is NULL, OCC will be setup on just
-      *        one target.
-+     *
-+     * @param[in] i_target0:    target of first processor in DCM pair
-+     * @param[in] i_target1:    target of second processor in DCM pair
-+     *
-+     * @return errlHndl_t  Error log of stopOCC failed
-      */
-     errlHndl_t stopOCC(TARGETING::Target * i_target0,
-                        TARGETING::Target * i_target1)
-diff --git a/src/usr/hwpf/hwp/occ/runtime/rt_occ.C b/src/usr/hwpf/hwp/occ/runtime/rt_occ.C
-index 1bc02a8..8583801 100644
---- a/src/usr/hwpf/hwp/occ/runtime/rt_occ.C
-+++ b/src/usr/hwpf/hwp/occ/runtime/rt_occ.C
-@@ -179,7 +179,7 @@ namespace RT_OCC
- 
-             void* occHostVirt = reinterpret_cast <void *> (i_homer_addr_va +
-                                 HOMER_OFFSET_TO_OCC_HOST_DATA);
--            err = HBOCC::loadHostDataToHomer(proc_target,occHostVirt);
-+            err = HBOCC::loadHostDataToHomer(occHostVirt);
-             if( err != NULL )
-             {
-                 TRACFCOMP( g_fapiImpTd, ERR_MRK"loading Host Data Area failed!" );
--- 
-1.8.2.2
-
diff --git a/openpower/package/hostboot/hostboot-0006-Provide-OCC-Target-with-FRU_ID-attribute.patch b/openpower/package/hostboot/hostboot-0006-Provide-OCC-Target-with-FRU_ID-attribute.patch
deleted file mode 100644
index a459876..0000000
--- a/openpower/package/hostboot/hostboot-0006-Provide-OCC-Target-with-FRU_ID-attribute.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 27a08856a62b32d028315951da06bf091bd22bf6 Mon Sep 17 00:00:00 2001
-From: Bill Hoffa <wghoffa@us.ibm.com>
-Date: Thu, 26 Feb 2015 12:50:20 -0600
-Subject: [PATCH 1/5] Provide OCC Target with FRU_ID attribute
-
-Required with github commits:
-https://github.com/open-power/habanero-xml/commit/dc738f40fc6e6c63c2bf6e25dca0f85987c870b8
-and
-https://github.com/open-power/palmetto-xml/commit/84f5bf5cc10459a85340cd0cc82a8c65b5bc4c97
-
-Change-Id: I8dd08fe5b4649f1398675c47db3abbdb8a5363b0
-RTC:124817
-(cherry picked from commit 15d270e5f3f7b49fd26e2656b6d5b617aea207d9)
----
- src/usr/targeting/common/xmltohb/target_types.xml |    3 +++
- 1 files changed, 3 insertions(+), 0 deletions(-)
-
-diff --git a/src/usr/targeting/common/xmltohb/target_types.xml b/src/usr/targeting/common/xmltohb/target_types.xml
-index 4dcc796..6dc4e58 100644
---- a/src/usr/targeting/common/xmltohb/target_types.xml
-+++ b/src/usr/targeting/common/xmltohb/target_types.xml
-@@ -1726,6 +1726,9 @@
-     <attribute>
-         <id>OCC_MASTER_CAPABLE</id>
-     </attribute>
-+    <attribute>
-+        <id>FRU_ID</id>
-+    </attribute>
- </targetType>
- 
- </attributes>
--- 
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0006-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch b/openpower/package/hostboot/hostboot-0006-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch
new file mode 100644
index 0000000..bb5a0ae
--- /dev/null
+++ b/openpower/package/hostboot/hostboot-0006-Revert-SW294127-INITPROC-FSP-Hostboot-fast-exit-powe.patch
@@ -0,0 +1,544 @@
+From 114bf3bb36fffe6c3c9c5894ebaae5772edb35ff Mon Sep 17 00:00:00 2001
+From: Andrew Geissler <andrewg@us.ibm.com>
+Date: Sat, 28 Feb 2015 12:28:05 -0600
+Subject: [PATCH] Revert "SW294127:INITPROC: FSP&Hostboot - fast exit power down"
+
+This reverts commit bffe97031429bd5656930f7453c496ce2594e5e6.
+---
+ .../mss_draminit_mc/mss_draminit_mc.C              |   19 +-
+ src/usr/hwpf/hwp/initfiles/mba_def.initfile        |  423 +++++---------------
+ 2 files changed, 118 insertions(+), 324 deletions(-)
+
+diff --git a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+index 53f3132..350efb7 100644
+--- a/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
++++ b/src/usr/hwpf/hwp/dram_training/mss_draminit_mc/mss_draminit_mc.C
+@@ -5,7 +5,7 @@
+ /*                                                                        */
+ /* OpenPOWER HostBoot Project                                             */
+ /*                                                                        */
+-/* Contributors Listed Below - COPYRIGHT 2012,2015                        */
++/* Contributors Listed Below - COPYRIGHT 2012,2014                        */
+ /* [+] International Business Machines Corp.                              */
+ /*                                                                        */
+ /*                                                                        */
+@@ -22,7 +22,7 @@
+ /* permissions and limitations under the License.                         */
+ /*                                                                        */
+ /* IBM_PROLOG_END_TAG                                                     */
+-// $Id: mss_draminit_mc.C,v 1.48 2014/12/05 15:37:43 dcadiga Exp $
++// $Id: mss_draminit_mc.C,v 1.47 2014/09/24 14:48:18 dcadiga Exp $
+ //------------------------------------------------------------------------------
+ // *! (C) Copyright International Business Machines Corp. 2011
+ // *! All Rights Reserved -- Property of IBM
+@@ -46,7 +46,6 @@
+ //------------------------------------------------------------------------------
+ // Version:|  Author: |  Date:  | Comment:
+ //---------|----------|---------|-----------------------------------------------
+-//  1.48   | dcadiga  |05-DEC-14| Powerdown control at initfile
+ //  1.47   | dcadiga  |09-SEP-14| Removed SPARE cke disable step
+ //  1.46   | gollub   |07-APR-14| Removed call to mss_unmask_inband_errors (moved it to proc_cen_framelock)
+ //  1.45   | dcadiga  |14-FEB-14| Periodic Cal Fix for DD2
+@@ -255,14 +254,12 @@ ReturnCode mss_draminit_mc_cloned(Target& i_target)
+ 
+         // Step Five: Setup Power Management
+         FAPI_INF( "+++ Setting Up Power Management +++");
+-        FAPI_INF( "+++ POWER MANAGEMENT HANDLED AT INITFILE +++");
+-        //Procedure commented out because domain reduction enablement now handled at the initfile
+-        //rc = mss_enable_power_management(l_mbaChiplets[i]);
+-        //if(rc)
+-        //{
+-        //   FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
+-        //   return rc;
+-        //}
++        rc = mss_enable_power_management(l_mbaChiplets[i]);
++        if(rc)
++        {
++           FAPI_ERR("---Error During Power Management Setup and Enable rc = 0x%08X (creator = %d)---", uint32_t(rc), rc.getCreator());
++           return rc;
++        }
+   
+     }
+ 
+diff --git a/src/usr/hwpf/hwp/initfiles/mba_def.initfile b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+index 61eba9e..88aafb9 100644
+--- a/src/usr/hwpf/hwp/initfiles/mba_def.initfile
++++ b/src/usr/hwpf/hwp/initfiles/mba_def.initfile
+@@ -1,9 +1,9 @@
+-#-- $Id: mba_def.initfile,v 1.70 2014/12/05 16:21:33 yctschan Exp $
++
++#-- $Id: mba_def.initfile,v 1.69 2014/09/24 14:44:15 asaetow Exp $
+ #-- CHANGE HISTORY:
+ #--------------------------------------------------------------------------------
+ #-- Version:|Author: | Date:  | Comment:
+ #-- --------|--------|--------|--------------------------------------------------
+-#--     1.70|yctschan|12/05/14| Updated settings for fast exit power down
+ #--     1.69|asaetow | 9/24/14| Force SpareCKE sync. Spare DRAM workaround.
+ #--     1.68|jdsloat | 4/04/14| Turned off Power controls for GA1 concerns - Turn back on at a later date
+ #--     1.67|tschang | 4/01/14| Adjusted the PUP Avail and SEPD/FEPD time.
+@@ -144,12 +144,93 @@ define def_equal_test     =  (SYS.ATTR_SCRATCH_UINT32_1 == SYS.ATTR_SCRATCH_UINT
+ #    <valueType>uint32</valueType>
+ #    <enum>DISABLE = 0</enum>
+ 
++#<attribute>
++#    <id>ATTR_EFF_DIMM_RANKS_CONFIGED</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Bit wise representation of master ranks in each DIMM that are used for reads and writes. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
++#Dimensions are [port][dimm]  A/B=Mba_0 C/D=Mba_1 There are only two DIMM ranks: DIMM0 and DIMM1 where DIMM0 is the furthest from the centaur.
++#creator: mss_eff_cnfg
++#consumer: various
++#firmware notes: none</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#    <array> 2 2</array>
++#    <persistRuntime/>
++#</attribute>
++#
++#<attribute>
++#    <id>ATTR_EFF_NUM_MASTER_RANKS_PER_DIMM</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Specifies the number of master ranks per DIMM.</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#    <array> 2 2</array>
++#</attribute>
++#
++#<attribute>
++#    <id>ATTR_EFF_NUM_RANKS_PER_DIMM</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Number of ranks in each DIMM. Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.
++#values are 0,1,2, 4 up to 32
++#creator: mss_eff_cnfg
++#consumer: various
++#firmware notes: none</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#    <array> 2 2</array>
++#    <persistRuntime/>
++#</attribute>
++#
++#<attribute>
++#    <id>ATTR_EFF_DRAM_BANKS</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Number of DRAM banks.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
++#creator: mss_eff_cnfg
++#consumer: various
++#firmware notes: none</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#</attribute>
++#
++#<attribute>
++#    <id>ATTR_EFF_DRAM_ROWS</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Number of DRAM rows.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
++#creator: mss_eff_cnfg
++#consumer: various
++#firmware notes: none</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#</attribute>
++#
++#<attribute>
++#    <id>ATTR_EFF_DRAM_COLS</id>
++#    <targetType>TARGET_TYPE_MBA_CHIPLET</targetType>
++#    <description>Number of DRAM columns.  Used in various locations and is computed in mss_eff_cnfg. Can be overwritten by ODM vendors if done from the PNOR or odm_eff_cnfg.  Each memory channel will have a value.
++#creator: mss_eff_cnfg
++#consumer: various
++#firmware notes: none</description>
++#    <valueType>uint8</valueType>
++#    <writeable/>
++#    <odmVisable/>
++#    <odmChangeable/>
++#</attribute
+ 
+ 
+ # mba tmr0 register timings are added to the value below
+ define def_margin1      = (1);
+ define def_margin2      = (0);
+-define def_margin_pup_fast   = (0);
++define def_margin_pup_fast   = (7);
+ define def_margin_pup_slow   = (0);
+ define def_margin_rdtag = (4);
+ 
+@@ -263,22 +344,6 @@ define def_C3c_C4C_ddr4                       = ((def_2b_1socket_ddr4)||(def_2b_
+ define def_C4A_ddr4                           = ((def_2a_1socket_ddr4)||(def_2a_2socket_ddr4)||(def_3a_ddr4_cdimm  )||(def_7a_1socket_ddr4)||(def_7a_2socket_ddr4)||(def_3a_1socket_ddr4)||(def_3a_2socket_ddr4)||(def_4a_ddr4_cdimm));
+ define def_IS5D                               = ((def_5d_1socket     )||(def_5d_2socket));
+ 
+-# ODT Mappings
+-define  def_odt_mapping_1a           = (def_1a_1socket);
+-define  def_odt_mapping_1b1dimm      = (def_1b_1socket      ||def_3a_1socket      ||def_3a_1socket_ddr4 ||def_3b_1socket      ||def_3c_1socket_ddr4);
+-define  def_odt_mapping_1b2dimm      = (def_3c_2socket_ddr4   ||def_1b_2socket        ||def_3a_2socket        ||def_3a_2socket_ddr4   ||def_3b_2socket);
+-#define  def_odt_mapping_1bcdimm      = (def_1a_2socket        ||def_1b_cdimm        ||def_3a_cdimm        ||def_3a_ddr4_cdimm   ||def_3b_cdimm        ||def_3b_ddr4_cdimm   ||def_3c_cdimm        ||def_3c_ddr4_cdimm);
+-define  def_odt_mapping_1bcdimm      = (def_1a_2socket        ||def_3a_cdimm        ||def_3a_ddr4_cdimm   ||def_3b_cdimm        ||def_3b_ddr4_cdimm   ||def_3c_cdimm        ||def_3c_ddr4_cdimm);
+-define  def_odt_mapping_1c2dimm      = (def_1c_2socket_odt);
+-define  def_odt_mapping_1c1dimm      = (def_1c_1socket_odt);
+-define  def_odt_mapping_1ccdimm      = (def_1c_cdimm        ||def_4a_cdimm        ||def_4a_ddr4_cdimm   ||def_4b_ddr4_cdimm   ||def_4c_ddr4_cdimm);
+-define  def_odt_mapping_1dx82dimm    = (def_1d_2socket);
+-define  def_odt_mapping_1dx4         = (def_1d_1socket);
+-define  def_odt_mapping_2abc         = (def_2a_1socket      ||def_2a_2socket        ||def_2a_1socket_ddr4 ||def_2a_2socket_ddr4   ||def_2a_cdimm        ||def_2a_ddr4_cdimm   ||def_2b_1socket      ||def_2b_2socket        ||def_2b_1socket_ddr4 ||def_2b_2socket_ddr4   ||def_2b_cdimm        ||def_2b_ddr4_cdimm   ||def_2c_1socket      ||def_2c_2socket        ||def_2c_1socket_ddr4 ||def_2c_2socket_ddr4   ||def_2c_ddr4_cdimm);
+-define  def_odt_mapping_56781lrdm    = (def_5b_1socket      ||def_5c_1socket      ||def_7a_1socket      ||def_7a_1socket_ddr4 ||def_7b_1socket      ||def_7b_1socket_ddr4 ||def_7c_1socket      ||def_7c_1socket_ddr4);
+-define  def_odt_mapping_56782lrdm    = (def_5b_2socket        ||def_5c_2socket        ||def_7a_2socket        ||def_7a_2socket_ddr4   ||def_7b_2socket        ||def_7b_2socket_ddr4   ||def_7c_2socket        ||def_7c_2socket_ddr4);
+-define  def_odt_mapping_5d1dimm      = (def_5d_1socket);
+-define  def_odt_mapping_5d2dimm      = (def_5d_2socket);
+ 
+ 
+ #gdial std_size           (            MBA_SRQ.mba_tmr1q_cfg_tfaw, MBA_SRQ.pc.MBAREF0Q_cfg_trfc,  MBA_SRQ.pc.MBAREF0Q_cfg_refr_tsv_stack, MBA_SRQ.pc.MBARPC0Q_cfg_pup_pdn, MBA_SRQ.pc.MBARPC0Q_cfg_pdn_pup, MBA_SRQ.pc.MBARPC0Q_cfg_pup_avail, MBA_SRQ.mba_tmr0q_RRSMSR_dly  , MBA_SRQ.mba_tmr0q_RRSMDR_dly, MBA_SRQ.mba_tmr0q_WWSMSR_dly, MBA_SRQ.mba_tmr0q_WWSMDR_dly  , MBA_SRQ.MBA_TMR0Q_Trrd,   MBA_SRQ.srqdbg.cfg_std_size_id)=
+@@ -1944,31 +2009,29 @@ scom 0x03010432    {
+ #
+ scom 0x03010434    {
+     bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+-    2       ,   0b0       ,           1            ,   (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0); # cfg_min_max_domains       36
+-    2       ,   0b1       ,           1            ,   (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0); # cfg_min_max_domains       36
+-#    3:5     ,   0b001       ,           1            ,   any; # cfg_min_max_domains       36
+-    6:10    ,   0b00100  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly4  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail   - performance enhancemnt
+-    6:10    ,   0b00011  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly4  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail   - performance enhancemnt
+-    6:10    ,   0b00101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly5  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00100  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly5  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00110  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly6  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00101  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly6  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00111  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly7  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00110  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly7  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b01000  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly8  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b00111  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly8  == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b01101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b01100  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b10000  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b01111  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b10100  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b10011  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b10111  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b10110  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b11010  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b11001  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b11101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 1) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
+-    6:10    ,   0b11100  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && ((CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 2) || (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE == 3)); # MBARPC0Q_cfg_pup_avail     36
++#    3:5     ,   0b010       ,           1            ,   any; # cfg_min_max_domains       36
++    6:10    ,   0b00100  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly4  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail   - performance enhancemnt
++    6:10    ,   0b00100  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly4  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail   - performance enhancemnt
++    6:10    ,   0b00101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly5  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b00101  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly5  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b00110  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly6  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b00110  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly6  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b00111  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly7  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b00111  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly7  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b01000  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly8  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b01000  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly8  == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b01101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b01101  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly13 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10000  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10000  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly16 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10100  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10100  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly20 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10111  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b10111  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly23 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b11010  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b11010  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly26 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b11101  + def_margin_pup_slow   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 0); # MBARPC0Q_cfg_pup_avail     36
++    6:10    ,   0b11101  + def_margin_pup_fast   ,           1            ,   (def_MBARPC0Q_cfg_pup_avail_dly29 == 1) && (ATTR_EFF_DRAM_DLL_PPD == 1); # MBARPC0Q_cfg_pup_avail     36
+     11:15   ,   0b00011     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly3 == 1); # MBARPC0Q_cfg_pup_pup       37
+     11:15   ,   0b00100     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly4 == 1); # MBARPC0Q_cfg_pup_pup       37
+     11:15   ,   0b00101     ,           1            ,   (def_MBARPC0Q_cfg_pdn_pup_dly5 == 1); # MBARPC0Q_cfg_pup_pup       37
+@@ -1977,286 +2040,20 @@ scom 0x03010434    {
+     16:20   ,   0b00100     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly4 == 1); # MBARPC0Q_cfg_pup_pdn       38
+     16:20   ,   0b00101     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly5 == 1); # MBARPC0Q_cfg_pup_pdn       38
+     16:20   ,   0b00110     ,           1            ,   (def_MBARPC0Q_cfg_pup_pdn_dly6 == 1); # MBARPC0Q_cfg_pup_pdn       38
+-    22      ,   0b0         ,           1            ,   (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 0);
+-    22      ,   0b1         ,           1            ,   (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED != 0);
++    22      ,   0b0         ,           1            ,   any; # cfg_min_domain_reduction_enable set to 1 to enable power controls
+     23:32   ,   0b0000000011,           1            ,   any; # Set min doman reduction time to 30.7 us (10.245us * 3)
+     42      ,   0b1         ,           1            ,   any; # Force SpareCKE sync
+-    43      ,   0b1         ,           1            ,   any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval
++    43      ,   0b0         ,           1            ,   any; # Use 1 in 8k 2:1 cycle pulses for min domain reduction time interval
+ }
+ 
+-# had to shifts the data to be able to get it into the proper positions
+-define shift_pwr_map1 = (ATTR_VPD_CKE_PWR_MAP >> 60);
+-define shift_pwr_map2 = (ATTR_VPD_CKE_PWR_MAP >> 56);
+-define shift_pwr_map3 = (ATTR_VPD_CKE_PWR_MAP >> 52);
+-define shift_pwr_map4 = (ATTR_VPD_CKE_PWR_MAP >> 48);
+-define shift_pwr_map5 = (ATTR_VPD_CKE_PWR_MAP >> 44);
+-define shift_pwr_map6 = (ATTR_VPD_CKE_PWR_MAP >> 40);
+-define shift_pwr_map7 = (ATTR_VPD_CKE_PWR_MAP >> 36);
+-define shift_pwr_map8 = (ATTR_VPD_CKE_PWR_MAP >> 32);
+-define shift_pwr_map9 = (ATTR_VPD_CKE_PWR_MAP >> 28);
+-define shift_pwr_map10 = (ATTR_VPD_CKE_PWR_MAP >> 24);
+-define shift_pwr_map11 = (ATTR_VPD_CKE_PWR_MAP >> 20);
+-define shift_pwr_map12 = (ATTR_VPD_CKE_PWR_MAP >> 16);
+-define shift_pwr_map13 = (ATTR_VPD_CKE_PWR_MAP >> 12);
+-define shift_pwr_map14 = (ATTR_VPD_CKE_PWR_MAP >> 8);
+-define shift_pwr_map15 = (ATTR_VPD_CKE_PWR_MAP >> 4);
+-
+ # MBAPC1Q    power control settings reg 1
+ #
+ scom 0x03010435    {
+     bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+-    0:3    ,   shift_pwr_map1 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-    0:3     ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk0_rd_cke    36
+-    0:3     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-    0:3     ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-    0:3     ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-    0:3     ,   0x9         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-    0:3     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-    0:3     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-    0:3     ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-    0:3     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-    0:3     ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-    0:3     ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-    0:3     ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-    0:3     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-    0:3     ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_rd_cke    36
+-    4:7    ,   shift_pwr_map2 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-    4:7     ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk1_rd_cke    36
+-    4:7     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-    4:7     ,   0xE         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-    4:7     ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-    4:7     ,   0x5         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-    4:7     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-    4:7     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-    4:7     ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-    4:7     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-    4:7     ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-    4:7     ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-    4:7     ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-    4:7     ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-    4:7     ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-    8:11   ,   shift_pwr_map3 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk2_rd_cke    36
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   8:11    ,   0x9         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   8:11    ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   8:11    ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   8:11    ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   8:11    ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   8:11    ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   8:11    ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   12:15   ,   shift_pwr_map4 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk3_rd_cke    36
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   12:15   ,   0x5         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   12:15   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   12:15   ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   12:15   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   12:15   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   12:15   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   12:15   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   16:19   ,   shift_pwr_map5 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk4_rd_cke    36
+-   16:19   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   16:19   ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   16:19   ,   0xA         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   16:19   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   16:19   ,   0x3         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   16:19   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   16:19   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   16:19   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   16:19   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   16:19   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   20:23   ,   shift_pwr_map6 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk5_rd_cke    36
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   20:23   ,   0xB         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   20:23   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   20:23   ,   0x9         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   20:23   ,   0x3         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   20:23   ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   20:23   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   20:23   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   20:23   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   20:23   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-}
+-
+-
+-scom 0x03010435    {
+-    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+-   24:27   ,   shift_pwr_map7 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk6_rd_cke    37
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   24:27   ,   0xA         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   24:27   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   24:27   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   24:27   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   24:27   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   28:31   ,   shift_pwr_map8 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk7_rd_cke    37
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   28:31   ,   0x9         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   28:31   ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   28:31   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   28:31   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   28:31   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   32:35   ,   shift_pwr_map9 ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk0_wr_cke    38
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   32:35   ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   32:35   ,   0xA         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   32:35   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   32:35   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   32:35   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   32:35   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   32:35   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   32:35   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   36:39   ,   shift_pwr_map10,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   32:35   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1); # cfg_mrnk0_wr_cke    38
+-   36:39   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1);
+-   36:39   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   36:39   ,   0xE         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   36:39   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   36:39   ,   0x6         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   36:39   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   36:39   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   36:39   ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   36:39   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   36:39   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   36:39   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   36:39   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   36:39   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   36:39   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   40:43   ,   shift_pwr_map11,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk2_wr_cke    38
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   40:43   ,   0xA         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   40:43   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   40:43   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   40:43   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   40:43   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   40:43   ,   0x8         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   40:43   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   44:47   ,   shift_pwr_map12,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk3_wr_cke    38
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   44:47   ,   0x6         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   44:47   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   44:47   ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   44:47   ,   0xC         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   44:47   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   44:47   ,   0x4         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   44:47   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
++    0:63    ,   ATTR_VPD_CKE_PWR_MAP ,          1            ,    any; # data from VP now
+ }
+ 
+ 
+-scom 0x03010435    {
+-    bits    ,   scom_data   ,       ATTR_FUNCTIONAL,   expr;
+-   48:51   ,   shift_pwr_map13,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   48:51   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk4_wr_cke    38
+-   48:51   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   48:51   ,   0x7         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   48:51   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   48:51   ,   0x6         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   48:51   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   48:51   ,   0x3         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   48:51   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   48:51   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   48:51   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   48:51   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   48:51   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   48:51   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   48:51   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   52:55   ,   shift_pwr_map14,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk5_wr_cke    38
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   52:55   ,   0xB         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   52:55   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   52:55   ,   0x5         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   52:55   ,   0x3         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   52:55   ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   52:55   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   52:55   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   52:55   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   52:55   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   56:59   ,   shift_pwr_map15,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk6_wr_cke    38
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   56:59   ,   0x6         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   56:59   ,   0xF         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   56:59   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   56:59   ,   0x2         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   56:59   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-   60:63   ,   ATTR_VPD_CKE_PWR_MAP,     1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 1) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 2); # slow exit pdown
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1a        == 1); # cfg_mrnk7_wr_cke    38
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b1dimm   == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1b2dimm   == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1bcdimm   == 1);
+-   60:63   ,   0x5         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c2dimm   == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1c1dimm   == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1ccdimm   == 1);
+-   60:63   ,   0xD         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx82dimm == 1);
+-   60:63   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_1dx4      == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_2abc      == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56781lrdm == 1);
+-   60:63   ,   0x1         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_56782lrdm == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d1dimm   == 1);
+-   60:63   ,   0x0         ,          1            ,    (SYS.ATTR_MRW_POWER_CONTROL_REQUESTED == 2) && (CENTAUR.ATTR_VPD_POWER_CONTROL_CAPABLE != 1) && (def_odt_mapping_5d2dimm   == 1);
+-}
+ 
+ ###########################
+ # MBA CKE mapping tables  #
+-- 
+1.7.4.1
+
diff --git a/openpower/package/hostboot/hostboot-0007-Update-dev-tree-with-additional-sensor-information.patch b/openpower/package/hostboot/hostboot-0007-Update-dev-tree-with-additional-sensor-information.patch
deleted file mode 100644
index c83b019..0000000
--- a/openpower/package/hostboot/hostboot-0007-Update-dev-tree-with-additional-sensor-information.patch
+++ /dev/null
@@ -1,510 +0,0 @@
-From d8c341b72aad30bff1417f1a2cec82af9cc14786 Mon Sep 17 00:00:00 2001
-From: Richard J. Knight <rjknight@us.ibm.com>
-Date: Thu, 19 Feb 2015 23:47:03 -0600
-Subject: [PATCH 2/5] Update dev tree with additional sensor information
-
-    -Add sensor type, reading type and specific offsets.
-    -Add IPMI entity ID and instance information for sensors
-    -Include IPMI Enity instance in targets which have ipmi sensors
-     attribute
-
-Change-Id: I02b0a5046c67e2e00af30a0c78cbcc182ae4c0cd
-RTC:123186
-(cherry picked from commit ff8c81ac1ab76d9835165a8dae4a0e3b1e5a0055)
----
- src/include/usr/ipmi/ipmisensor.H                  |   96 ++++++++++++++++++++
- src/usr/devtree/bld_devtree.C                      |   89 ++++++++++++++-----
- src/usr/ipmi/ipmisensor.C                          |   76 ++++++++++++++++
- src/usr/targeting/common/Targets.pm                |    2 +-
- .../common/xmltohb/attribute_types_hb.xml          |   73 +++++++++++++++
- .../targeting/common/xmltohb/target_types_hb.xml   |   12 ++-
- 6 files changed, 322 insertions(+), 26 deletions(-)
-
-diff --git a/src/include/usr/ipmi/ipmisensor.H b/src/include/usr/ipmi/ipmisensor.H
-index 7b4e3fa..ef00bfa 100644
---- a/src/include/usr/ipmi/ipmisensor.H
-+++ b/src/include/usr/ipmi/ipmisensor.H
-@@ -48,6 +48,20 @@ namespace SENSOR
-     const uint8_t INVALID_TYPE = 0xFF;
- 
-     /**
-+     *  @enum sensorReadingTypes
-+     *  Sensor specific completion codes, defined in IPMI Spec.
-+     *
-+     */
-+    enum sensorReadingType
-+    {
-+        THRESHOLD                   = 0x01,
-+        DIGITAL_ASSERT_DEASSERT     = 0x03,
-+        DIGITAL_ENABLE_DISABLE      = 0x09,
-+        SENSOR_SPECIFIC             = 0x6f,
-+    };
-+
-+
-+    /**
-      *  @enum procStatusSensorOffsets
-      *  Sensor specific completion codes, defined in IPMI Spec.
-      *
-@@ -90,6 +104,74 @@ namespace SENSOR
-         CRITICAL_OVER_TEMP              = 0x0A,
-     };
- 
-+    /**
-+     *  @enum firmwareBootProgressSensorOffsets
-+     *  Boot progress specific offsets defined in IPMI Spec.
-+     *
-+     */
-+    enum firmwareProgressSensorOffsets
-+    {
-+        // offset 02h
-+        SYSTEM_FIRMWARE_PROGRESS = 0x02,
-+    };
-+
-+    /**
-+     *  @enum discrete09_Offsets
-+     *
-+     *      Offsets specific to IPMI sensor reading type 09
-+     *      digital discrete senosrs. These offsets result in
-+     *      Device Enabled or Device Disabled events in the
-+     *      BMC event log.
-+     *
-+     */
-+    enum discrete09_Offsets
-+    {
-+        // offset 00h
-+        DEVICE_DISABLED = 0x0,
-+
-+        //offset 01h
-+        DEVICE_ENABLED  = 0x1,
-+    };
-+
-+     /**
-+     *  @enum discrete03_Offsets
-+     *
-+     *      Offsets specific to IPMI sensor reading type 03
-+     *      digital discrete senosrs. These offsets result in generic
-+     *      State Asserted or State Deasserted events in the
-+     *      BMC event log.
-+     *
-+     */
-+    enum discrete03_Offsets
-+    {
-+        // offset 00h
-+        DEASSERTED = 0x00,
-+
-+        //offset 01h
-+        ASSERTED   = 0x01,
-+    };
-+
-+     /**
-+     *  @enum acpiPowerState_Offsets
-+     *
-+     *      Offsets specific to IPMI ACPI Power state
-+     *      senosrs. These offsets result in power
-+     *      state messages in the BMC event log.
-+     *
-+     */
-+    enum acpiPowerState_Offsets
-+    {
-+        // offset 0h
-+        S0_G0_WORKING   = 0x00,
-+
-+        // offset 05h
-+        G5_SOFT_OFF     = 0x05,
-+
-+        //offset 0Bh
-+        LEGACY_ON       = 0x0B,
-+
-+    };
-+
-     //**  Bit definition for set sensor reading cmd operation field
-     //      [7:6] 10b - write given values to event data bytes let BMC handle
-     //                  offset in event data 1 when an external event is
-@@ -827,6 +909,20 @@ namespace SENSOR
-     errlHndl_t getAPSSChannelSensorNumbers(
-                                      const uint16_t (* &o_sensor_numbers)[16]);
- 
-+    /**
-+     *   Helper function to return a mask of the supported masks for the
-+     *   sensor passed in.
-+     *
-+     *  @param[i] - sensor name to determine the offset for.
-+     *  @param[o] - sensor reading type, defined in IPMI spec for the
-+     *              passed in sensor number.
-+     *
-+     *
-+     *  @return sensor offsets
-+     */
-+    uint16_t getSensorOffsets(TARGETING::SENSOR_NAME i_name,
-+                              sensorReadingType &o_readType );
-+
- 
- 
- }; // end namespace
-diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
-index dd81392..f4647a3 100644
---- a/src/usr/devtree/bld_devtree.C
-+++ b/src/usr/devtree/bld_devtree.C
-@@ -1299,17 +1299,40 @@ errlHndl_t bld_fdt_mem(devTree * i_dt, bool i_smallTree)
-     return errhdl;
- }
- 
-+
-+#ifdef CONFIG_BMC_IPMI
-+enum
-+{
-+    ENTITY_ID_MASK      = 0x00FF,
-+    SENSOR_TYPE_MASK    = 0xFF00,
-+};
-+
- /* create a node for each IPMI sensor in the system, the sensor unit number
-    corresponds to the BMC assigned sensor number */
- uint32_t bld_sensor_node(devTree * i_dt, const dtOffset_t & i_parentNode,
--                         const uint16_t sensorData[] )
-+                         const uint16_t sensorData[],
-+                         uint32_t instance, uint32_t chipId )
- {
- 
--    const uint32_t sensorNumber = sensorData[
-+    SENSOR::sensorReadingType readType;
-+
-+    // pass in the sensor name to get back the supported offsets and the event
-+    // reading type for this sensor.
-+    uint32_t offsets = SENSOR::getSensorOffsets(
-+             static_cast<TARGETING::SENSOR_NAME>(
-+                 sensorData[TARGETING::IPMI_SENSOR_ARRAY_NAME_OFFSET]),
-+             readType);
-+
-+    const uint16_t sensorNumber = sensorData[
-                         TARGETING::IPMI_SENSOR_ARRAY_NUMBER_OFFSET];
- 
--    const uint32_t sensorName =
--                        sensorData[TARGETING::IPMI_SENSOR_ARRAY_NAME_OFFSET];
-+    // the sensor name is a combination of the sensor type + entity ID
-+    const uint16_t sensorType = (
-+        sensorData[TARGETING::IPMI_SENSOR_ARRAY_NAME_OFFSET]
-+                    & SENSOR_TYPE_MASK) >> 8;
-+
-+    const uint16_t entityId =
-+        sensorData[TARGETING::IPMI_SENSOR_ARRAY_NAME_OFFSET] & ENTITY_ID_MASK;
- 
-     /* Build sensor node based on sensor number */
-     dtOffset_t sensorNode = i_dt->addNode(i_parentNode, "sensor", sensorNumber);
-@@ -1317,22 +1340,35 @@ uint32_t bld_sensor_node(devTree * i_dt, const dtOffset_t & i_parentNode,
-     i_dt->addPropertyCell32(sensorNode, "reg", sensorNumber);
- 
-     // add sensor type
--    i_dt->addPropertyCell32(sensorNode, "ipmi-sensor-type", sensorName);
--
--   // @TODO RTC:113902
--    // get more info from Ben H. regarding what info he needs
--    // add the name of the sensor
--    //i_dt->addPropertyString(sensorNode, "name", sensorToString( sensorName ));
--    //   i_dt->addPropertyCell32(sensorNode, "ipmi-entity-type",
--    //                                          sensorData[ENTITY_TYPE_OFFSET]);
--    //   i_dt->addPropertyCell32(sensorNode, "ipmi-reading-type",
--    //                                         sensorData[READING_TYPE_OFFSET]);
--
--    /* return the phandle for this sensor, might need to add it to the
--    cpus node per Ben H. proposal */
-+    i_dt->addPropertyCell32(sensorNode, "ipmi-sensor-type", sensorType);
-+    i_dt->addPropertyCell32(sensorNode, "ipmi-entity-id", entityId);
-+    i_dt->addPropertyCell32(sensorNode, "ipmi-entity-instance", instance);
-+    i_dt->addPropertyCell32(sensorNode, "ipmi-sensor-offsets", offsets);
-+    i_dt->addPropertyCell32(sensorNode, "ipmi-sensor-reading-type", readType);
-+
-+    // currently we only add the chip ID to the OCC sensor
-+    if(chipId != 0xFF )
-+    {
-+        i_dt->addPropertyCell32(sensorNode, "ibm,chip-id", chipId);
-+    }
-+
-+    /* return the phandle for this sensor */
-     return i_dt->getPhandle(sensorNode);
- }
- 
-+// return the IPMI entity instance from the SDR for this
-+// target.
-+uint32_t getInstanceNumber( TARGETING::Target * i_pTarget )
-+{
-+    AttributeTraits<ATTR_IPMI_INSTANCE>::Type l_instance;
-+
-+   l_instance = i_pTarget->getAttr<TARGETING::ATTR_IPMI_INSTANCE>();
-+
-+   return l_instance;
-+
-+}
-+
-+// build the sensor node for a given target
- uint32_t bld_sensor_node(devTree * i_dt, const dtOffset_t & i_sensorNode,
-         TARGETING::Target * i_pTarget )
- {
-@@ -1344,6 +1380,17 @@ uint32_t bld_sensor_node(devTree * i_dt, const dtOffset_t & i_sensorNode,
-      * for each sensor */
-     if ( i_pTarget->tryGetAttr<ATTR_IPMI_SENSORS>(l_sensors) )
-     {
-+        uint32_t chipId = 0xFF;
-+
-+        // add the chip id to the OCC sensor since OPAL needs it to figure out
-+        // which OCC it is.
-+        if( TARGETING::TYPE_OCC == i_pTarget->getAttr<TARGETING::ATTR_TYPE>())
-+        {
-+            ConstTargetHandle_t proc = getParentChip(i_pTarget);
-+
-+            chipId = getProcChipId( proc );
-+        }
-+
-         for(uint16_t i=0; i< array_rows; i++)
-         {
-             /*  if the sensor number is 0xFF move on */
-@@ -1351,7 +1398,8 @@ uint32_t bld_sensor_node(devTree * i_dt, const dtOffset_t & i_sensorNode,
-             {
-                 /* use this row to create the next sensor node - ignoring
-                  * return value for now */
--                bld_sensor_node(i_dt, i_sensorNode, l_sensors[i] );
-+                bld_sensor_node(i_dt, i_sensorNode, l_sensors[i],
-+                        getInstanceNumber(i_pTarget) , chipId );
-             }
-             else
-             {
-@@ -1394,10 +1442,6 @@ errlHndl_t bld_fdt_sensors(devTree * i_dt, const dtOffset_t & i_parentNode,
-     i_dt->addPropertyCell32(sensorNode, "#address-cells", 1);
-     i_dt->addPropertyCell32(sensorNode, "#size-cells", 0);
- 
--    // pass ALL IPMI_SENSORS to opal
--    // @TODO RTC:113902 - add remaining sensor info and limit sensors
--    // and adjust the sensors passed to opal to match their requirements
--
-     /*  loop through all the targets and get the IPMI sensor data if it
-         exists */
-     for (TargetIterator itr = TARGETING::targetService().begin();
-@@ -1454,6 +1498,7 @@ errlHndl_t bld_fdt_bmc(devTree * i_dt, bool i_smallTree)
- 
-     return errhdl;
- }
-+#endif
- 
- errlHndl_t bld_fdt_vpd(devTree * i_dt, bool i_smallTree)
- {
-diff --git a/src/usr/ipmi/ipmisensor.C b/src/usr/ipmi/ipmisensor.C
-index 3e15e91..fc7284b 100644
---- a/src/usr/ipmi/ipmisensor.C
-+++ b/src/usr/ipmi/ipmisensor.C
-@@ -1121,4 +1121,80 @@ namespace SENSOR
-         return NULL;
-     }
- 
-+    uint16_t getSensorOffsets( TARGETING::SENSOR_NAME i_name,
-+                             sensorReadingType &o_readType )
-+    {
-+
-+        uint16_t offsets = 0;
-+
-+        // most of our sensors use generic sensor specific reading types
-+        // so use that as the default value
-+        o_readType = SENSOR_SPECIFIC;
-+
-+        // sensor type is lower byte of sensor name, if we dont match
-+        // based on name, then try the sensor type
-+        uint16_t t = ( i_name >> 8 ) & 0x00FF;
-+
-+        switch( i_name )
-+        {
-+            case TARGETING::SENSOR_NAME_FW_BOOT_PROGRESS:
-+                {
-+                    offsets = ( 1 << SYSTEM_FIRMWARE_PROGRESS );
-+                    break;
-+                }
-+            case TARGETING::SENSOR_NAME_OCC_ACTIVE:
-+                {
-+                    offsets = ( 1 << DEVICE_DISABLED ) |
-+                              ( 1 << DEVICE_ENABLED );
-+                    o_readType = DIGITAL_ENABLE_DISABLE;
-+                    break;
-+                }
-+            case TARGETING::SENSOR_NAME_HOST_STATUS:
-+                {
-+                    offsets = ( 1 << S0_G0_WORKING ) |
-+                              ( 1 << G5_SOFT_OFF )   |
-+                              ( 1 << LEGACY_ON );
-+                    break;
-+                }
-+            case TARGETING::SENSOR_NAME_PCI_ACTIVE:
-+            case TARGETING::SENSOR_NAME_OS_BOOT:
-+                {
-+                    // default all offsets enabled
-+                    offsets = 0x7FFF;
-+                    break;
-+                }
-+
-+                default:
-+                {
-+                    // try sensor type
-+                    switch (t)
-+                    {
-+                        case TARGETING::SENSOR_TYPE_FAULT:
-+                            offsets = ( 1 << ASSERTED );
-+                            o_readType = DIGITAL_ASSERT_DEASSERT;
-+                            break;
-+
-+                        case TARGETING::SENSOR_TYPE_PROCESSOR:
-+                            offsets = ( 1 << PROC_PRESENCE_DETECTED ) |
-+                                      ( 1 << PROC_DISABLED )         |
-+                                      ( 1 << IERR );
-+                            break;
-+
-+                        case TARGETING::SENSOR_TYPE_MEMORY:
-+                            offsets = ( 1 << MEMORY_DEVICE_DISABLED ) |
-+                                      ( 1 << MEM_DEVICE_PRESENCE_DETECTED );
-+                            break;
-+                        default:
-+                            offsets = 0;
-+                            o_readType = THRESHOLD;
-+                            break;
-+                    }
-+
-+                }
-+        }
-+
-+        return offsets;
-+    }
-+
-+
- }; // end name space
-diff --git a/src/usr/targeting/common/Targets.pm b/src/usr/targeting/common/Targets.pm
-index eb1ea1f..29f6bcb 100644
---- a/src/usr/targeting/common/Targets.pm
-+++ b/src/usr/targeting/common/Targets.pm
-@@ -195,7 +195,7 @@ sub printAttribute
-     $filter{ENTITY_ID_LOOKUP}               = 1;
-     $filter{ENTITY_INSTANCE}                = 1;
-     $filter{MBA_NUM}                        = 1;
--    $filter{IPMI_INSTANCE}                  = 1;
-+    $filter{IPMI_INSTANCE}                  = 0;
-     $filter{IPMI_NAME}                      = 1;
-     $filter{INSTANCE_ID}                    = 1;
-     #$filter{ADC_CHANNEL_SENSOR_NUMBERS}     = 1;
-diff --git a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
-index 3bb57e6..74fb492 100644
---- a/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
-+++ b/src/usr/targeting/common/xmltohb/attribute_types_hb.xml
-@@ -822,6 +822,16 @@
-     <writeable/>
-     <hbOnly/>
- </attribute>
-+<attribute>
-+    <id>IPMI_INSTANCE</id>
-+    <description>Holds the IPMI instance number for this entity.</description>
-+    <simpleType>
-+        <uint32_t>
-+        </uint32_t>
-+    </simpleType>
-+    <persistency>non-volatile</persistency>
-+    <readable/>
-+</attribute>
- <enumerationType>
-     <id>ENTITY_ID</id>
-     <description>Enumeration indicating the IPMI entity ID, these values are
-@@ -1003,6 +1013,69 @@
-     </enumerator>
- </enumerationType>
- 
-+<enumerationType>
-+    <id>SENSOR_TYPE</id>
-+    <description>Enumeration indicating the IPMI sensor type, these values
-+        are defined in the IPMI specification. These values will be used when
-+    sending sensor reading events to the BMC.</description>
-+    <enumerator>
-+        <name>NA</name>
-+        <value>0</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>TEMPERATURE</name>
-+        <value>0x01</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>PROCESSOR</name>
-+        <value>0x07</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>MEMORY</name>
-+        <value>0x0c</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>SYS_FW_PROGRESS</name>
-+        <value>0x0F</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>SYS_EVENT</name>
-+        <value>0x12</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>OS_BOOT</name>
-+       <value>0x1F</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>APCI_POWER_STATE</name>
-+        <value>0x22</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>FREQ</name>
-+        <value>0xC1</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>POWER</name>
-+        <value>0xC2</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>BOOT_COUNT</name>
-+        <value>0xC3</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>PCI_LINK_PRES</name>
-+        <value>0xC4</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>PWR_LIMIT_ACTIVE</name>
-+        <value>0xC4</value>
-+    </enumerator>
-+    <enumerator>
-+        <name>FAULT</name>
-+        <value>0xC7</value>
-+    </enumerator>
-+</enumerationType>
-+
- <!-- IPMI Sensor numbers are defined in the IPMI spec as 8 bit values. However
- in the hostboot code they will be defined as a uint16_t to allow us to add
- additonal information. An example relates to error logs returned by the OCC,
-diff --git a/src/usr/targeting/common/xmltohb/target_types_hb.xml b/src/usr/targeting/common/xmltohb/target_types_hb.xml
-index 8255b70..bd00b87 100644
---- a/src/usr/targeting/common/xmltohb/target_types_hb.xml
-+++ b/src/usr/targeting/common/xmltohb/target_types_hb.xml
-@@ -33,6 +33,14 @@
-      ================================================================= -->
- 
- <targetTypeExtension>
-+    <id>base</id>
-+    <attribute>
-+        <id>IPMI_INSTANCE</id>
-+        <default>0</default>
-+    </attribute>
-+</targetTypeExtension>
-+
-+<targetTypeExtension>
-     <id>sys-sys-power8</id>
-     <attribute><id>IS_MPIPL_HB</id></attribute>
-     <attribute><id>IBSCOM_ENABLE_OVERRIDE</id></attribute>
-@@ -182,9 +190,7 @@
-     <attribute>
-         <id>PSTATE_TABLE</id>
-     </attribute>
--    <attribute>
--        <id>IPMI_SENSORS</id>
--    </attribute>
-+    <attribute><id>IPMI_SENSORS</id></attribute>
- </targetTypeExtension>
- 
- <targetTypeExtension>
--- 
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0008-Report-pnor-side-booted-up-on-A-B-to-OPAL.patch b/openpower/package/hostboot/hostboot-0008-Report-pnor-side-booted-up-on-A-B-to-OPAL.patch
deleted file mode 100644
index 7abf536..0000000
--- a/openpower/package/hostboot/hostboot-0008-Report-pnor-side-booted-up-on-A-B-to-OPAL.patch
+++ /dev/null
@@ -1,207 +0,0 @@
-From 2dd8eb6b90b7dfe63587292e163e27075f652b40 Mon Sep 17 00:00:00 2001
-From: Bill Schwartz <whs@us.ibm.com>
-Date: Wed, 11 Feb 2015 05:17:23 -0600
-Subject: [PATCH 4/5] Report pnor side booted up on A/B to OPAL
-
-This story will use the getPnorInfo and getSideInfo interfaces
-to fill in devtree entries informing Opal about the existence,
-location, and state of PNOR sides that we know about.  We will pass up a list
-of TOCs associated with the active side and the inactive side.
-
-RTC: 109703
-Change-Id: I740b086a9e22a0bc167141e3565bf813e50d9a00
-(cherry picked from commit b42f65df9fddb3938c096c23ccdcb2568a727120)
----
- src/include/usr/pnor/pnorif.H |    5 ++
- src/usr/devtree/bld_devtree.C |  110 +++++++++++++++++++++++++++++++++++++++++
- src/usr/pnor/pnor_common.H    |    1 -
- src/usr/pnor/pnordd.C         |    3 +-
- 4 files changed, 117 insertions(+), 2 deletions(-)
-
-diff --git a/src/include/usr/pnor/pnorif.H b/src/include/usr/pnor/pnorif.H
-index e12ccf1..0fc5a83 100644
---- a/src/include/usr/pnor/pnorif.H
-+++ b/src/include/usr/pnor/pnorif.H
-@@ -120,6 +120,11 @@ struct SideInfo_t
-     uint64_t hbbMmioOffset; /**< HBB MMIO Offset associated with hbbAddress*/
- };
- 
-+enum
-+{
-+    INVALID_OFFSET = 0xFFFFFFF,  // Invalid primary or alternate TOC
-+};
-+
- /**
-  * @brief Returns information about a given side of pnor
-  *
-diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
-index f4647a3..d90c1fd 100644
---- a/src/usr/devtree/bld_devtree.C
-+++ b/src/usr/devtree/bld_devtree.C
-@@ -405,6 +405,113 @@ void add_i2c_info( const TARGETING::Target* i_targ,
- 
- }
- 
-+void bld_getSideInfo(PNOR::SideId i_side,
-+                     uint32_t     o_TOCaddress[2],
-+                     uint8_t    & o_count,
-+                     bool       & o_isGolden)
-+{
-+    errlHndl_t  errhdl = NULL;
-+    PNOR::SideInfo_t  l_info;
-+
-+    o_count = 0;
-+    o_isGolden = false;
-+
-+    errhdl = getSideInfo (i_side, l_info);
-+    if (!errhdl)
-+    {
-+        // return the valid TOC offsets & count of valid TOCs
-+        if (PNOR::INVALID_OFFSET != l_info.primaryTOC)
-+        {
-+            o_TOCaddress[o_count++] = l_info.primaryTOC;
-+        }
-+        if (PNOR::INVALID_OFFSET != l_info.backupTOC)
-+        {
-+            o_TOCaddress[o_count++] = l_info.backupTOC;
-+        }
-+        o_isGolden      = l_info.isGolden;
-+    }
-+    else
-+    {
-+        // commit error and return 0 TOC offsets
-+        errlCommit(errhdl, DEVTREE_COMP_ID);
-+    }
-+
-+    return;
-+}
-+
-+void bld_fdt_pnor(devTree *   i_dt,
-+                  dtOffset_t  i_parentNode)
-+{
-+    do
-+    {
-+        uint32_t l_active[2]    = {PNOR::INVALID_OFFSET,PNOR::INVALID_OFFSET};
-+        uint32_t l_golden[2]    = {PNOR::INVALID_OFFSET,PNOR::INVALID_OFFSET};
-+        uint8_t  l_count = 0;
-+        bool     l_isGolden = false;
-+        bool     l_goldenFound = false;
-+        uint8_t  l_goldenCount = 0;
-+        PNOR::PnorInfo_t l_pnorInfo;
-+
-+        //Get pnor address and size
-+        getPnorInfo (l_pnorInfo);
-+
-+        dtOffset_t l_pnorNode = i_dt->addNode(i_parentNode,
-+                                              "pnor",
-+                                              l_pnorInfo.mmioOffset);
-+
-+        const uint8_t l_isaLinkage = 0; // 0==Mem
-+        uint32_t pnor_prop[3] = {l_isaLinkage,
-+                                 l_pnorInfo.mmioOffset,
-+                                 l_pnorInfo.flashSize};
-+        i_dt->addPropertyCells32(l_pnorNode, "reg", pnor_prop, 3);
-+
-+        //Add Working/Active parition
-+        bld_getSideInfo(PNOR::WORKING,l_active,l_count,l_isGolden);
-+        if (l_count) // valid TOCs present
-+        {
-+            i_dt->addPropertyCells32(l_pnorNode,
-+                                 "active-image-tocs", l_active, l_count);
-+            // capture golden
-+            if (l_isGolden)
-+            {
-+                l_golden[0] = l_active[0];
-+                l_golden[1] = l_active[1];
-+                l_goldenCount = l_count;
-+                l_goldenFound = true;
-+            }
-+        }
-+
-+#if CONFIG_PNOR_TWO_SIDE_SUPPORT
-+        //Add Alternate parition
-+        uint32_t l_alternate[2] = {PNOR::INVALID_OFFSET,PNOR::INVALID_OFFSET};
-+
-+        bld_getSideInfo(PNOR::ALTERNATE,l_alternate,l_count,l_isGolden);
-+        if (l_count) // valid TOCs present
-+        {
-+            i_dt->addPropertyCells32(l_pnorNode,
-+                                 "alternate-image-tocs",l_alternate,l_count);
-+            // capture golden
-+            if (l_isGolden)
-+            {
-+                l_golden[0] = l_alternate[0];
-+                l_golden[1] = l_alternate[1];
-+                l_goldenCount = l_count;
-+                l_goldenFound = true;
-+            }
-+        }
-+#endif
-+
-+        //Include golden if there is one
-+        if (l_goldenFound)
-+        {
-+            i_dt->addPropertyCells32(l_pnorNode,
-+                                 "golden-image-tocs",l_golden,l_goldenCount);
-+        }
-+
-+    } while (0);
-+
-+    return;
-+}
- 
- void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
-                     const TARGETING::Target * i_pProc, uint32_t i_chipid)
-@@ -488,6 +595,8 @@ void bld_xscom_node(devTree * i_dt, dtOffset_t & i_parentNode,
-         i_dt->addPropertyCell32(lpcNode, "#address-cells", 2);
-         i_dt->addPropertyCell32(lpcNode, "#size-cells", 1);
- 
-+        bld_fdt_pnor (i_dt, lpcNode);
-+
-     }
- 
-     /*NX*/
-@@ -908,6 +1017,7 @@ void load_hbrt_image(uint64_t& io_address)
-     }
- }
- 
-+
- errlHndl_t bld_fdt_system(devTree * i_dt, bool i_smallTree)
- {
-     errlHndl_t errhdl = NULL;
-diff --git a/src/usr/pnor/pnor_common.H b/src/usr/pnor/pnor_common.H
-index dd7ab2e..7213add 100644
---- a/src/usr/pnor/pnor_common.H
-+++ b/src/usr/pnor/pnor_common.H
-@@ -61,7 +61,6 @@ namespace PNOR {
-         SUPPORTED_FFS_VERSION = 0x1,  /**< Supported FFS Version */
-         FFS_TABLE_BASE_ADDR = 0x0,    /**< Currently only have FFS table */
-         TOC_SIZE = 0x8000,
--        INVALID_OFFSET = 0xFFFFFFF,
-     };
- 
-     /**
-diff --git a/src/usr/pnor/pnordd.C b/src/usr/pnor/pnordd.C
-index 13667ce..c0c7b0e 100644
---- a/src/usr/pnor/pnordd.C
-+++ b/src/usr/pnor/pnordd.C
-@@ -46,6 +46,7 @@
- #include <errl/errludstring.H>
- #include <targeting/common/targetservice.H>
- #include "pnordd.H"
-+#include "pnor_common.H"
- #include <pnor/pnorif.H>
- #include <pnor/pnor_reasoncodes.H>
- #include <sys/time.h>
-@@ -196,7 +197,7 @@ bool usingL3Cache()
-  */
- void getPnorInfo( PnorInfo_t& o_pnorInfo )
- {
--    o_pnorInfo.mmioOffset = 0; //LPC_SFC_MMIO_OFFSET;//@fixme-need Prachi's code for this
-+    o_pnorInfo.mmioOffset = LPC_SFC_MMIO_OFFSET|LPC_FW_SPACE;
-     o_pnorInfo.norWorkarounds =
-       Singleton<PnorDD>::instance().getNorWorkarounds();
-     o_pnorInfo.flashSize =
--- 
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot-0009-Change-Opal-Devtree-IPMI-FRU_ID-Name.patch b/openpower/package/hostboot/hostboot-0009-Change-Opal-Devtree-IPMI-FRU_ID-Name.patch
deleted file mode 100644
index 35944b9..0000000
--- a/openpower/package/hostboot/hostboot-0009-Change-Opal-Devtree-IPMI-FRU_ID-Name.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 90c6df43a7b7836f973d0fbae5c751742d305e37 Mon Sep 17 00:00:00 2001
-From: Bill Hoffa <wghoffa@us.ibm.com>
-Date: Fri, 27 Feb 2015 11:33:07 -0600
-Subject: [PATCH 4/5] Change Opal Devtree IPMI FRU_ID Name
-
-Change-Id: I95156302b65c1a1be611d081e842eaf2aac5d03a
-RTC:124830
-(cherry picked from commit 3847eee998f35baeee1a3c085042ff0cdb78e5d1)
----
- src/usr/devtree/bld_devtree.C |    2 +-
- 1 files changed, 1 insertions(+), 1 deletions(-)
-
-diff --git a/src/usr/devtree/bld_devtree.C b/src/usr/devtree/bld_devtree.C
-index d90c1fd..66b0d6f 100644
---- a/src/usr/devtree/bld_devtree.C
-+++ b/src/usr/devtree/bld_devtree.C
-@@ -1600,7 +1600,7 @@ errlHndl_t bld_fdt_bmc(devTree * i_dt, bool i_smallTree)
-     TARGETING::targetService().getTopLevelTarget(pSys);
-     assert(pSys != NULL,
-                "bld_fdt_bmc - Error: Could not find the top level target.");
--    i_dt->addPropertyCell32(bmcNode, "fruId",
-+    i_dt->addPropertyCell32(bmcNode, "firmware-fru-id",
-                                    pSys->getAttr<TARGETING::ATTR_FRU_ID>());
- 
-     /* create a node to hold the sensors */
--- 
-1.7.4.1
-
diff --git a/openpower/package/hostboot/hostboot.mk b/openpower/package/hostboot/hostboot.mk
index a415be2..cdba674 100644
--- a/openpower/package/hostboot/hostboot.mk
+++ b/openpower/package/hostboot/hostboot.mk
@@ -4,7 +4,7 @@
 #
 ################################################################################
 
-HOSTBOOT_VERSION ?= 6c9eac071a9a79921c4b360af53e023dad19666f
+HOSTBOOT_VERSION ?= c1c0f838d21167482e292246435e7c07f8bfa3bd
 HOSTBOOT_SITE ?= $(call github,open-power,hostboot,$(HOSTBOOT_VERSION))
 
 HOSTBOOT_LICENSE = Apache-2.0